Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc	78.29	94.12	85.71			83.33	50.00
tb.dut.u_reg.u_wake_control_cdc	97.73	100.00	90.91			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wake_events_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
78.29	94.12	85.71			83.33	50.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.38	90.62	66.67			84.21	60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	84.46	89.80	66.67			81.40	100.00
u_src_to_dst_req	58.08	92.31	40.00			100.00	0.00

---

Module Instance : tb.dut.u_reg.u_wake_control_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.13	96.08	96.43			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.47	99.76	98.11			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	96.88	87.50	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Covered	T1,T7,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T7,T8

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1168405414	376158	0	0
DstReqKnown_A	14222788	14156540	0	0
SrcAckBusyChk_A	1168405414	1261	0	0
SrcBusyKnown_A	1168405414	1167753296	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168405414	376158	0	0
T1	147621	450	0	0
T2	913848	0	0	0
T3	26989	0	0	0
T7	0	926	0	0
T8	0	274	0	0
T10	0	308	0	0
T11	0	516	0	0
T12	0	275	0	0
T13	0	325	0	0
T14	0	275	0	0
T15	0	1357	0	0
T16	0	937	0	0
T17	31389	0	0	0
T18	13709	0	0	0
T19	19816	0	0	0
T20	33285	0	0	0
T21	25570	0	0	0
T22	20605	0	0	0
T23	7294	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	14222788	14156540	0	0
T1	35858	35844	0	0
T2	33812	33800	0	0
T3	810	794	0	0
T17	220	184	0	0
T18	124	108	0	0
T19	450	438	0	0
T20	996	980	0	0
T21	688	674	0	0
T22	330	320	0	0
T23	258	238	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168405414	1261	0	0
T1	147621	2	0	0
T2	913848	0	0	0
T3	26989	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	31389	0	0	0
T18	13709	0	0	0
T19	19816	0	0	0
T20	33285	0	0	0
T21	25570	0	0	0
T22	20605	0	0	0
T23	7294	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168405414	1167753296	0	0
T1	295242	295230	0	0
T2	1827696	1827552	0	0
T3	53978	53824	0	0
T17	62778	62446	0	0
T18	27418	27284	0	0
T19	39632	39438	0	0
T20	66570	66450	0	0
T21	51140	50994	0	0
T22	41210	41052	0	0
T23	14588	14486	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
TOTAL		17	16	94.12
CONT_ASSIGN	65	0	0
ALWAYS	71	5	4	80.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	7	7	100.00
CONT_ASSIGN	150	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65		unreachable
71	1	1
72	1	1
73	1	1
74		unreachable
75	1	1
76	0	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123		unreachable
124		unreachable
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150		unreachable
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Covered	Percent
Conditions	7	6	85.71
Logical	7	6	85.71
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Unreachable

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T7,T8
1	0	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Not Covered
1	0	Excluded		VC_COV_UNR
1	1	Excluded		VC_COV_UNR

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Line No.	Total	Covered	Percent
Branches		6	5	83.33
IF	71	3	2	66.67
IF	115	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Unreachable
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_events_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	2	50.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	2	50.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	584202707	0	0	0
DstReqKnown_A	7111394	7078270	0	0
SrcAckBusyChk_A	584202707	0	0	0
SrcBusyKnown_A	584202707	583876648	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7111394	7078270	0	0
T1	17929	17922	0	0
T2	16906	16900	0	0
T3	405	397	0	0
T17	110	92	0	0
T18	62	54	0	0
T19	225	219	0	0
T20	498	490	0	0
T21	344	337	0	0
T22	165	160	0	0
T23	129	119	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T7,T8

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T7,T8

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T7,T8
1	1	Covered	T1,T7,T8

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T7,T8
0	0	1	Covered	T1,T7,T8
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg.u_wake_control_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	584202707	376158	0	0
DstReqKnown_A	7111394	7078270	0	0
SrcAckBusyChk_A	584202707	1261	0	0
SrcBusyKnown_A	584202707	583876648	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	376158	0	0
T1	147621	450	0	0
T2	913848	0	0	0
T3	26989	0	0	0
T7	0	926	0	0
T8	0	274	0	0
T10	0	308	0	0
T11	0	516	0	0
T12	0	275	0	0
T13	0	325	0	0
T14	0	275	0	0
T15	0	1357	0	0
T16	0	937	0	0
T17	31389	0	0	0
T18	13709	0	0	0
T19	19816	0	0	0
T20	33285	0	0	0
T21	25570	0	0	0
T22	20605	0	0	0
T23	7294	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7111394	7078270	0	0
T1	17929	17922	0	0
T2	16906	16900	0	0
T3	405	397	0	0
T17	110	92	0	0
T18	62	54	0	0
T19	225	219	0	0
T20	498	490	0	0
T21	344	337	0	0
T22	165	160	0	0
T23	129	119	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	1261	0	0
T1	147621	2	0	0
T2	913848	0	0	0
T3	26989	0	0	0
T7	0	2	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	0	2	0	0
T15	0	2	0	0
T16	0	2	0	0
T17	31389	0	0	0
T18	13709	0	0	0
T19	19816	0	0	0
T20	33285	0	0	0
T21	25570	0	0	0
T22	20605	0	0	0
T23	7294	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	584202707	583876648	0	0
T1	147621	147615	0	0
T2	913848	913776	0	0
T3	26989	26912	0	0
T17	31389	31223	0	0
T18	13709	13642	0	0
T19	19816	19719	0	0
T20	33285	33225	0	0
T21	25570	25497	0	0
T22	20605	20526	0	0
T23	7294	7243	0	0