Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362	1			T2	2		T7	5		T15	8
all_values[1]	362	1			T2	2		T7	5		T15	8
all_values[2]	362	1			T2	2		T7	5		T15	8
all_values[3]	362	1			T2	2		T7	5		T15	8
all_values[4]	362	1			T2	2		T7	5		T15	8
all_values[5]	362	1			T2	2		T7	5		T15	8
all_values[6]	362	1			T2	2		T7	5		T15	8
all_values[7]	362	1			T2	2		T7	5		T15	8
all_values[8]	362	1			T2	2		T7	5		T15	8
all_values[9]	362	1			T2	2		T7	5		T15	8
all_values[10]	362	1			T2	2		T7	5		T15	8
all_values[11]	362	1			T2	2		T7	5		T15	8
all_values[12]	362	1			T2	2		T7	5		T15	8
all_values[13]	362	1			T2	2		T7	5		T15	8
all_values[14]	362	1			T2	2		T7	5		T15	8
all_values[15]	362	1			T2	2		T7	5		T15	8
all_values[16]	362	1			T2	2		T7	5		T15	8
all_values[17]	362	1			T2	2		T7	5		T15	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8658

1

T2

64

T7

128

T15

185

auto[1]

2926

1

T7

32

T15

71

T16

78

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9281

1

T2

63

T7

120

T15

181

auto[1]

2303

1

T2

1

T7

40

T15

75

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	135	1			T2	2		T7	4		T15	3
all_values[0]	auto[0]	auto[1]	57	1			T7	1		T15	2		T16	4
all_values[0]	auto[1]	auto[0]	105	1			T15	2		T16	1		T17	5
all_values[0]	auto[1]	auto[1]	65	1			T15	1		T17	3		T42	1
all_values[1]	auto[0]	auto[0]	143	1			T2	2		T7	4		T15	4
all_values[1]	auto[0]	auto[1]	59	1			T7	1		T15	2		T16	1
all_values[1]	auto[1]	auto[0]	115	1			T16	1		T17	3		T42	4
all_values[1]	auto[1]	auto[1]	45	1			T15	2		T16	1		T17	1
all_values[2]	auto[0]	auto[0]	102	1			T2	1		T7	3		T15	3
all_values[2]	auto[0]	auto[1]	100	1			T2	1		T15	4		T19	1
all_values[2]	auto[1]	auto[0]	87	1			T17	6		T42	2		T59	5
all_values[2]	auto[1]	auto[1]	73	1			T7	2		T15	1		T16	2
all_values[3]	auto[0]	auto[0]	119	1			T2	2		T15	1		T19	2
all_values[3]	auto[0]	auto[1]	75	1			T15	2		T16	2		T17	4
all_values[3]	auto[1]	auto[0]	95	1			T7	1		T15	2		T16	1
all_values[3]	auto[1]	auto[1]	73	1			T7	4		T15	3		T16	1
all_values[4]	auto[0]	auto[0]	130	1			T2	2		T7	3		T15	2
all_values[4]	auto[0]	auto[1]	71	1			T7	1		T15	4		T16	1
all_values[4]	auto[1]	auto[0]	92	1			T7	1		T17	3		T42	3
all_values[4]	auto[1]	auto[1]	69	1			T15	2		T16	2		T17	2
all_values[5]	auto[0]	auto[0]	134	1			T2	2		T7	1		T15	2
all_values[5]	auto[0]	auto[1]	59	1			T15	3		T16	1		T17	3
all_values[5]	auto[1]	auto[0]	107	1			T7	1		T15	1		T16	3
all_values[5]	auto[1]	auto[1]	62	1			T7	3		T15	2		T16	3
all_values[6]	auto[0]	auto[0]	142	1			T2	2		T15	2		T19	2
all_values[6]	auto[0]	auto[1]	63	1			T7	1		T15	2		T17	4
all_values[6]	auto[1]	auto[0]	101	1			T7	2		T15	2		T16	5
all_values[6]	auto[1]	auto[1]	56	1			T7	2		T15	2		T17	1
all_values[7]	auto[0]	auto[0]	144	1			T2	2		T7	4		T15	3
all_values[7]	auto[0]	auto[1]	60	1			T15	1		T17	2		T42	2
all_values[7]	auto[1]	auto[0]	101	1			T7	1		T15	3		T16	4
all_values[7]	auto[1]	auto[1]	57	1			T15	1		T16	3		T42	4
all_values[8]	auto[0]	auto[0]	132	1			T2	2		T15	1		T19	2
all_values[8]	auto[0]	auto[1]	51	1			T17	1		T42	4		T43	2
all_values[8]	auto[1]	auto[0]	109	1			T7	3		T15	4		T16	7
all_values[8]	auto[1]	auto[1]	70	1			T7	2		T15	3		T16	1
all_values[9]	auto[0]	auto[0]	123	1			T2	2		T7	2		T15	3
all_values[9]	auto[0]	auto[1]	61	1			T7	2		T16	2		T17	2
all_values[9]	auto[1]	auto[0]	116	1			T7	1		T15	5		T16	4
all_values[9]	auto[1]	auto[1]	62	1			T16	1		T17	2		T42	2
all_values[10]	auto[0]	auto[0]	141	1			T2	2		T7	1		T15	1
all_values[10]	auto[0]	auto[1]	50	1			T7	3		T15	1		T16	2
all_values[10]	auto[1]	auto[0]	116	1			T15	5		T16	4		T17	1
all_values[10]	auto[1]	auto[1]	55	1			T7	1		T15	1		T16	2
all_values[11]	auto[0]	auto[0]	153	1			T2	2		T7	4		T15	2
all_values[11]	auto[0]	auto[1]	75	1			T15	3		T16	1		T17	2
all_values[11]	auto[1]	auto[0]	76	1			T15	2		T16	1		T17	1
all_values[11]	auto[1]	auto[1]	58	1			T7	1		T15	1		T17	1
all_values[12]	auto[0]	auto[0]	127	1			T2	2		T7	2		T19	2
all_values[12]	auto[0]	auto[1]	74	1			T7	2		T15	2		T17	2
all_values[12]	auto[1]	auto[0]	84	1			T7	1		T15	1		T16	6
all_values[12]	auto[1]	auto[1]	77	1			T15	5		T16	2		T17	1
all_values[13]	auto[0]	auto[0]	127	1			T2	2		T7	1		T19	2
all_values[13]	auto[0]	auto[1]	74	1			T7	4		T15	3		T16	1
all_values[13]	auto[1]	auto[0]	95	1			T15	2		T16	4		T17	4
all_values[13]	auto[1]	auto[1]	66	1			T15	3		T17	1		T42	2
all_values[14]	auto[0]	auto[0]	131	1			T2	2		T7	1		T15	1
all_values[14]	auto[0]	auto[1]	72	1			T7	3		T15	5		T16	1
all_values[14]	auto[1]	auto[0]	113	1			T15	1		T16	3		T42	1
all_values[14]	auto[1]	auto[1]	46	1			T7	1		T15	1		T16	3
all_values[15]	auto[0]	auto[0]	126	1			T2	2		T7	1		T15	3
all_values[15]	auto[0]	auto[1]	68	1			T15	2		T16	1		T42	3
all_values[15]	auto[1]	auto[0]	97	1			T7	2		T15	2		T16	2
all_values[15]	auto[1]	auto[1]	71	1			T7	2		T15	1		T16	2
all_values[16]	auto[0]	auto[0]	139	1			T2	2		T7	2		T19	2
all_values[16]	auto[0]	auto[1]	71	1			T7	3		T15	2		T16	2
all_values[16]	auto[1]	auto[0]	109	1			T15	3		T16	1		T17	4
all_values[16]	auto[1]	auto[1]	43	1			T15	3		T16	2		T42	2
all_values[17]	auto[0]	auto[0]	140	1			T2	2		T7	3		T15	1
all_values[17]	auto[0]	auto[1]	62	1			T7	1		T15	3		T16	1
all_values[17]	auto[1]	auto[0]	107	1			T7	1		T15	2		T16	2
all_values[17]	auto[1]	auto[1]	53	1			T15	2		T16	4		T17	2