Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
61.31	65.57	60.87	86.57	0.00	71.17	97.77	47.24

Total tests in report: 175

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
51.50	51.50	62.28	62.28	50.34	50.34	83.80	83.80	0.00	0.00	64.37	64.37	91.90	91.90	7.78	7.78	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3796741726
56.47	4.98	62.98	0.70	52.10	1.76	90.85	7.04	0.00	0.00	64.54	0.17	91.90	0.00	32.94	25.16	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.358497922
59.15	2.68	65.40	2.43	59.23	7.13	93.19	2.35	0.00	0.00	71.01	6.47	92.18	0.28	33.03	0.09	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.440082137
60.82	1.67	65.40	0.00	59.23	0.00	93.66	0.47	0.00	0.00	71.01	0.00	94.69	2.51	41.72	8.69	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4033449494
61.47	0.65	65.40	0.00	60.52	1.28	94.84	1.17	0.00	0.00	71.09	0.08	95.53	0.84	42.90	1.18	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3647933910
61.89	0.43	65.40	0.00	60.52	0.00	94.84	0.00	0.00	0.00	71.09	0.00	95.53	0.00	45.88	2.99	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3602902370
62.27	0.37	65.40	0.00	60.61	0.10	94.84	0.00	0.00	0.00	71.09	0.00	97.77	2.23	46.15	0.27	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4241931295
62.37	0.10	65.40	0.00	60.61	0.00	94.84	0.00	0.00	0.00	71.09	0.00	97.77	0.00	46.88	0.72	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3543822473
62.46	0.09	65.40	0.00	60.66	0.05	95.31	0.47	0.00	0.00	71.17	0.08	97.77	0.00	46.88	0.00	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1293180663
62.50	0.04	65.57	0.17	60.80	0.14	95.31	0.00	0.00	0.00	71.17	0.00	97.77	0.00	46.88	0.00	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.604106338
62.53	0.03	65.57	0.00	60.85	0.05	95.31	0.00	0.00	0.00	71.17	0.00	97.77	0.00	47.06	0.18	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2014583549
62.55	0.01	65.57	0.00	60.85	0.00	95.31	0.00	0.00	0.00	71.17	0.00	97.77	0.00	47.15	0.09	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1171009678
62.56	0.01	65.57	0.00	60.85	0.00	95.31	0.00	0.00	0.00	71.17	0.00	97.77	0.00	47.24	0.09	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2595771261
62.56	0.01	65.57	0.00	60.87	0.02	95.31	0.00	0.00	0.00	71.17	0.00	97.77	0.00	47.24	0.00	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.557361422

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3355272327
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4190491672
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3724373192
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1671640308
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3153709761
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2359846137
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2870496192
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1650634804
/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1954121310
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4011597716
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2832444857
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2588897939
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2273105325
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4274357888
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1173290838
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2225742121
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2592640277
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656283264
/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1978153909
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.357020181
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1811575075
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.3070729477
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4156540219
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2043888685
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3344033856
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2886149981
/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3875322109
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3780873173
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3984074705
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.577300309
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2146652353
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2224205192
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2579320477
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.243980154
/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4077949916
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4015660352
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.801364592
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4164821924
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2409251176
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3693030807
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.124557695
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1531969171
/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3134232831
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2308346003
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2363892947
/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1009223209
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3970822070
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2672181810
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2874989311
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4119003174
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3175882681
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3492831534
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1537513763
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.438301790
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.711000496
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.234154686
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.846131175
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.997071326
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2443833455
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4153103652
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1340911349
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2319351313
/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2925411326
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1540506547
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2289740318
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.161852253
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1690898932
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.4000292860
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.501368652
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2533330756
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1641990879
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3415488960
/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1863085778
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.794233841
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1145662123
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3915592236
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2746032057
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3623726371
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.210923811
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4197334936
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.887859001
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3695841321
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4033987506
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.939082803
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.1630400719
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.1055174087
/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2229481221
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.4067087238
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2897760827
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3529843494
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1360060473
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2481310825
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3473211366
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3194203840
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2121817086
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3003104167
/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1637926308
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3341387031
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3012669286
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3661587800
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2782608927
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2482822914
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4030609045
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2303354173
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.945060453
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1438306051
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3060214879
/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3390620083
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.599897811
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1938836150
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2028110075
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2588907167
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3553891677
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1673889450
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3003289259
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4267026999
/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.402866524
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.894255911
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4287538722
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3840187346
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2180710482
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1933959202
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2836420962
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.107864082
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.144898634
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.501948232
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2970178524
/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4100371915
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1220341964
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3994047709
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1102245287
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2803994916
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3936655750
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1800688663
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2483798643
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.180487277
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3550639226
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.187232114
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3202355129
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1933183863
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3206286359
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.889050451
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1579281234
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.81532558
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3060288982
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3904913850
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2382676327
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1008696068
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2101467639
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2824727985
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1525673724
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.602318948
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.564708164
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3734674123
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3764483748
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.327541326
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2125185573
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3944117317
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2303498825
/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.488178171
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4206661611

Total test records in report: 175

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.602318948	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:56 PM PDT 24	86375938 ps
T2	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.107864082	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:58 PM PDT 24	107549103 ps
T3	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2579320477	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:30 PM PDT 24	158753170 ps
T8	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1811575075	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:16 PM PDT 24	60492609 ps
T7	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2481310825	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	42701432 ps
T4	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.577300309	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:14 PM PDT 24	96775060 ps
T15	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.358497922	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:17 PM PDT 24	35974065 ps
T5	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3796741726	Aug 19 04:32:57 PM PDT 24	Aug 19 04:33:03 PM PDT 24	1357761470 ps
T18	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4164821924	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:14 PM PDT 24	220604595 ps
T19	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.557361422	Aug 19 04:32:47 PM PDT 24	Aug 19 04:32:50 PM PDT 24	262909291 ps
T14	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2836420962	Aug 19 04:32:58 PM PDT 24	Aug 19 04:32:59 PM PDT 24	93772202 ps
T16	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1340911349	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	77536250 ps
T6	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2273105325	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:58 PM PDT 24	73449162 ps
T31	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2146652353	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:16 PM PDT 24	76986539 ps
T9	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.440082137	Aug 19 04:32:53 PM PDT 24	Aug 19 04:32:54 PM PDT 24	92614090 ps
T32	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4241931295	Aug 19 04:33:02 PM PDT 24	Aug 19 04:33:03 PM PDT 24	74233345 ps
T26	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1863085778	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:17 PM PDT 24	356798466 ps
T33	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2308346003	Aug 19 04:33:24 PM PDT 24	Aug 19 04:33:25 PM PDT 24	104726325 ps
T17	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3602902370	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	55395569 ps
T42	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3840187346	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:55 PM PDT 24	44723245 ps
T34	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2832444857	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:59 PM PDT 24	125906785 ps
T27	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4033449494	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:09 PM PDT 24	808154884 ps
T43	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1173290838	Aug 19 04:32:45 PM PDT 24	Aug 19 04:32:46 PM PDT 24	37380650 ps
T29	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.939082803	Aug 19 04:32:58 PM PDT 24	Aug 19 04:33:01 PM PDT 24	407074913 ps
T58	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2874989311	Aug 19 04:33:21 PM PDT 24	Aug 19 04:33:21 PM PDT 24	55244871 ps
T20	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1690898932	Aug 19 04:33:29 PM PDT 24	Aug 19 04:33:32 PM PDT 24	222277620 ps
T59	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1171009678	Aug 19 04:33:26 PM PDT 24	Aug 19 04:33:27 PM PDT 24	48406842 ps
T21	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3647933910	Aug 19 04:33:00 PM PDT 24	Aug 19 04:33:03 PM PDT 24	225951934 ps
T22	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2409251176	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:13 PM PDT 24	139017519 ps
T23	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2225742121	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:57 PM PDT 24	153901230 ps
T24	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2482822914	Aug 19 04:33:01 PM PDT 24	Aug 19 04:33:05 PM PDT 24	163071123 ps
T30	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.945060453	Aug 19 04:32:55 PM PDT 24	Aug 19 04:33:00 PM PDT 24	795776920 ps
T54	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3994047709	Aug 19 04:33:27 PM PDT 24	Aug 19 04:33:28 PM PDT 24	91179866 ps
T25	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.887859001	Aug 19 04:33:00 PM PDT 24	Aug 19 04:33:03 PM PDT 24	96480087 ps
T28	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2043888685	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:14 PM PDT 24	80741264 ps
T35	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2121817086	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:59 PM PDT 24	119130974 ps
T50	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4206661611	Aug 19 04:33:25 PM PDT 24	Aug 19 04:33:29 PM PDT 24	1084177775 ps
T55	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2289740318	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:31 PM PDT 24	64361592 ps
T67	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3724373192	Aug 19 04:32:45 PM PDT 24	Aug 19 04:32:48 PM PDT 24	89844485 ps
T68	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3492831534	Aug 19 04:33:29 PM PDT 24	Aug 19 04:33:32 PM PDT 24	350427480 ps
T51	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3355272327	Aug 19 04:32:43 PM PDT 24	Aug 19 04:32:46 PM PDT 24	204808697 ps
T56	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.210923811	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:56 PM PDT 24	42234644 ps
T69	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2224205192	Aug 19 04:33:09 PM PDT 24	Aug 19 04:33:10 PM PDT 24	46115404 ps
T36	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3202355129	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:57 PM PDT 24	327328499 ps
T37	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2319351313	Aug 19 04:33:21 PM PDT 24	Aug 19 04:33:22 PM PDT 24	249543458 ps
T12	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1637926308	Aug 19 04:33:00 PM PDT 24	Aug 19 04:33:01 PM PDT 24	93387397 ps
T70	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4033987506	Aug 19 04:32:58 PM PDT 24	Aug 19 04:33:00 PM PDT 24	65571468 ps
T47	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3764483748	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:06 PM PDT 24	308066797 ps
T52	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2886149981	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:17 PM PDT 24	173514359 ps
T71	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3060288982	Aug 19 04:33:00 PM PDT 24	Aug 19 04:33:02 PM PDT 24	203664572 ps
T38	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3012669286	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:56 PM PDT 24	90124727 ps
T53	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4011597716	Aug 19 04:32:43 PM PDT 24	Aug 19 04:32:49 PM PDT 24	937198129 ps
T72	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3175882681	Aug 19 04:33:32 PM PDT 24	Aug 19 04:33:34 PM PDT 24	78602701 ps
T39	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2782608927	Aug 19 04:32:57 PM PDT 24	Aug 19 04:32:59 PM PDT 24	79936972 ps
T40	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3003104167	Aug 19 04:32:56 PM PDT 24	Aug 19 04:33:01 PM PDT 24	835961158 ps
T73	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2803994916	Aug 19 04:33:29 PM PDT 24	Aug 19 04:33:30 PM PDT 24	72132109 ps
T74	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1800688663	Aug 19 04:33:10 PM PDT 24	Aug 19 04:33:11 PM PDT 24	74432554 ps
T75	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1673889450	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	44612370 ps
T76	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3543822473	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:28 PM PDT 24	41651244 ps
T77	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3661587800	Aug 19 04:32:57 PM PDT 24	Aug 19 04:32:58 PM PDT 24	41332996 ps
T49	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.604106338	Aug 19 04:33:26 PM PDT 24	Aug 19 04:33:29 PM PDT 24	279092127 ps
T78	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2363892947	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:17 PM PDT 24	137150588 ps
T79	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4100371915	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	44235353 ps
T80	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2229481221	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	84355994 ps
T81	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.1630400719	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	51009522 ps
T82	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4156540219	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:15 PM PDT 24	186723748 ps
T83	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2028110075	Aug 19 04:33:19 PM PDT 24	Aug 19 04:33:20 PM PDT 24	49868861 ps
T84	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3153709761	Aug 19 04:32:39 PM PDT 24	Aug 19 04:32:40 PM PDT 24	49390345 ps
T85	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2443833455	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:16 PM PDT 24	163306892 ps
T41	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4267026999	Aug 19 04:32:57 PM PDT 24	Aug 19 04:33:04 PM PDT 24	900968252 ps
T86	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2382676327	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:00 PM PDT 24	70494299 ps
T87	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3936655750	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:31 PM PDT 24	58170607 ps
T88	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2588907167	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	51589667 ps
T13	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3915592236	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:56 PM PDT 24	125632410 ps
T89	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3390620083	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	84318827 ps
T90	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.711000496	Aug 19 04:33:25 PM PDT 24	Aug 19 04:33:26 PM PDT 24	56009344 ps
T91	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1641990879	Aug 19 04:33:34 PM PDT 24	Aug 19 04:33:36 PM PDT 24	289597067 ps
T92	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1525673724	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:05 PM PDT 24	122230557 ps
T10	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1293180663	Aug 19 04:32:41 PM PDT 24	Aug 19 04:32:42 PM PDT 24	239812098 ps
T93	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.599897811	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	62080228 ps
T48	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2014583549	Aug 19 04:33:26 PM PDT 24	Aug 19 04:33:28 PM PDT 24	366014092 ps
T94	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3060214879	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	42920931 ps
T95	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3194203840	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	35038354 ps
T96	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3529843494	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:19 PM PDT 24	53914281 ps
T97	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.438301790	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:14 PM PDT 24	79594543 ps
T57	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3341387031	Aug 19 04:32:57 PM PDT 24	Aug 19 04:32:58 PM PDT 24	84449406 ps
T98	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.180487277	Aug 19 04:32:57 PM PDT 24	Aug 19 04:33:04 PM PDT 24	137489266 ps
T99	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.894255911	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:01 PM PDT 24	79380530 ps
T100	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1579281234	Aug 19 04:32:58 PM PDT 24	Aug 19 04:32:59 PM PDT 24	71055076 ps
T101	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2303498825	Aug 19 04:33:31 PM PDT 24	Aug 19 04:33:32 PM PDT 24	120422213 ps
T102	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.1055174087	Aug 19 04:33:31 PM PDT 24	Aug 19 04:33:32 PM PDT 24	37045963 ps
T44	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1145662123	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:06 PM PDT 24	318935245 ps
T103	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1671640308	Aug 19 04:32:40 PM PDT 24	Aug 19 04:32:41 PM PDT 24	97026732 ps
T60	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.4000292860	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:35 PM PDT 24	558884462 ps
T104	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4153103652	Aug 19 04:33:32 PM PDT 24	Aug 19 04:33:33 PM PDT 24	57524974 ps
T105	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2746032057	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:05 PM PDT 24	75758679 ps
T64	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2824727985	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:06 PM PDT 24	1021811653 ps
T106	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.234154686	Aug 19 04:33:12 PM PDT 24	Aug 19 04:33:14 PM PDT 24	108047742 ps
T107	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1933959202	Aug 19 04:32:55 PM PDT 24	Aug 19 04:33:00 PM PDT 24	511906714 ps
T108	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3553891677	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	41027502 ps
T109	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.501948232	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:11 PM PDT 24	40701807 ps
T62	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3693030807	Aug 19 04:33:09 PM PDT 24	Aug 19 04:33:13 PM PDT 24	1447332923 ps
T110	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4077949916	Aug 19 04:33:10 PM PDT 24	Aug 19 04:33:14 PM PDT 24	636094800 ps
T111	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3904913850	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:01 PM PDT 24	144737374 ps
T45	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2180710482	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:01 PM PDT 24	149983122 ps
T112	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.4067087238	Aug 19 04:33:16 PM PDT 24	Aug 19 04:33:17 PM PDT 24	64463719 ps
T113	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3944117317	Aug 19 04:33:12 PM PDT 24	Aug 19 04:33:12 PM PDT 24	35871093 ps
T114	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.81532558	Aug 19 04:32:58 PM PDT 24	Aug 19 04:32:59 PM PDT 24	33690117 ps
T115	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1938836150	Aug 19 04:33:31 PM PDT 24	Aug 19 04:33:32 PM PDT 24	38941324 ps
T116	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3780873173	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:16 PM PDT 24	227426431 ps
T117	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.501368652	Aug 19 04:33:18 PM PDT 24	Aug 19 04:33:20 PM PDT 24	201362593 ps
T118	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.357020181	Aug 19 04:33:27 PM PDT 24	Aug 19 04:33:30 PM PDT 24	85402112 ps
T119	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.3070729477	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	35794294 ps
T120	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1531969171	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:29 PM PDT 24	52813006 ps
T121	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2970178524	Aug 19 04:33:27 PM PDT 24	Aug 19 04:33:28 PM PDT 24	40018779 ps
T61	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1009223209	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:33 PM PDT 24	864275083 ps
T122	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2533330756	Aug 19 04:33:31 PM PDT 24	Aug 19 04:33:32 PM PDT 24	33596068 ps
T46	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1540506547	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:31 PM PDT 24	78967492 ps
T123	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3550639226	Aug 19 04:32:53 PM PDT 24	Aug 19 04:32:54 PM PDT 24	53538218 ps
T124	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2870496192	Aug 19 04:32:45 PM PDT 24	Aug 19 04:32:48 PM PDT 24	257231664 ps
T125	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3695841321	Aug 19 04:32:57 PM PDT 24	Aug 19 04:32:59 PM PDT 24	58026122 ps
T126	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1933183863	Aug 19 04:33:00 PM PDT 24	Aug 19 04:33:04 PM PDT 24	193576832 ps
T11	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.402866524	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:57 PM PDT 24	142740608 ps
T127	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3206286359	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:58 PM PDT 24	308326963 ps
T128	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1008696068	Aug 19 04:32:54 PM PDT 24	Aug 19 04:32:55 PM PDT 24	35231736 ps
T129	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.488178171	Aug 19 04:33:07 PM PDT 24	Aug 19 04:33:10 PM PDT 24	92438773 ps
T130	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3734674123	Aug 19 04:32:56 PM PDT 24	Aug 19 04:32:58 PM PDT 24	184942926 ps
T131	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.794233841	Aug 19 04:33:01 PM PDT 24	Aug 19 04:33:04 PM PDT 24	204600866 ps
T63	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.144898634	Aug 19 04:32:59 PM PDT 24	Aug 19 04:33:04 PM PDT 24	675401123 ps
T132	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3970822070	Aug 19 04:33:16 PM PDT 24	Aug 19 04:33:18 PM PDT 24	155165123 ps
T133	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2483798643	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:14 PM PDT 24	40315194 ps
T134	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.889050451	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:05 PM PDT 24	137014398 ps
T135	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.187232114	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:04 PM PDT 24	65877112 ps
T136	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2303354173	Aug 19 04:32:57 PM PDT 24	Aug 19 04:33:00 PM PDT 24	85094175 ps
T137	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4119003174	Aug 19 04:33:12 PM PDT 24	Aug 19 04:33:14 PM PDT 24	132028883 ps
T138	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1360060473	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:14 PM PDT 24	67236029 ps
T139	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1954121310	Aug 19 04:32:44 PM PDT 24	Aug 19 04:32:46 PM PDT 24	131749546 ps
T140	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4015660352	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:13 PM PDT 24	119747320 ps
T141	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3875322109	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:13 PM PDT 24	114845451 ps
T142	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2101467639	Aug 19 04:33:01 PM PDT 24	Aug 19 04:33:03 PM PDT 24	78851953 ps
T143	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2672181810	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:13 PM PDT 24	65910098 ps
T144	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4197334936	Aug 19 04:32:55 PM PDT 24	Aug 19 04:32:56 PM PDT 24	72143342 ps
T145	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3473211366	Aug 19 04:33:31 PM PDT 24	Aug 19 04:33:32 PM PDT 24	36180507 ps
T146	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3134232831	Aug 19 04:33:27 PM PDT 24	Aug 19 04:33:28 PM PDT 24	44547380 ps
T147	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3415488960	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:18 PM PDT 24	300443423 ps
T148	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2925411326	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:32 PM PDT 24	95749257 ps
T149	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.564708164	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:03 PM PDT 24	61861331 ps
T150	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1220341964	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:15 PM PDT 24	107284938 ps
T151	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2125185573	Aug 19 04:33:13 PM PDT 24	Aug 19 04:33:14 PM PDT 24	67541644 ps
T152	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1102245287	Aug 19 04:33:27 PM PDT 24	Aug 19 04:33:28 PM PDT 24	53747561 ps
T153	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1438306051	Aug 19 04:33:34 PM PDT 24	Aug 19 04:33:35 PM PDT 24	38999809 ps
T154	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3003289259	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:07 PM PDT 24	431406370 ps
T155	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4030609045	Aug 19 04:32:58 PM PDT 24	Aug 19 04:33:00 PM PDT 24	208714767 ps
T156	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1537513763	Aug 19 04:33:28 PM PDT 24	Aug 19 04:33:30 PM PDT 24	78740686 ps
T157	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3984074705	Aug 19 04:33:12 PM PDT 24	Aug 19 04:33:13 PM PDT 24	73297180 ps
T66	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2595771261	Aug 19 04:33:12 PM PDT 24	Aug 19 04:33:17 PM PDT 24	965789290 ps
T158	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656283264	Aug 19 04:32:57 PM PDT 24	Aug 19 04:32:58 PM PDT 24	79726091 ps
T159	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3344033856	Aug 19 04:33:06 PM PDT 24	Aug 19 04:33:09 PM PDT 24	432867583 ps
T160	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2588897939	Aug 19 04:32:55 PM PDT 24	Aug 19 04:33:07 PM PDT 24	1717807975 ps
T161	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.846131175	Aug 19 04:33:24 PM PDT 24	Aug 19 04:33:27 PM PDT 24	85213987 ps
T162	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4287538722	Aug 19 04:33:02 PM PDT 24	Aug 19 04:33:02 PM PDT 24	54378312 ps
T163	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4190491672	Aug 19 04:32:43 PM PDT 24	Aug 19 04:32:50 PM PDT 24	891412694 ps
T164	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.161852253	Aug 19 04:33:30 PM PDT 24	Aug 19 04:33:32 PM PDT 24	210694434 ps
T165	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.327541326	Aug 19 04:33:23 PM PDT 24	Aug 19 04:33:25 PM PDT 24	225232822 ps
T166	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.801364592	Aug 19 04:33:15 PM PDT 24	Aug 19 04:33:17 PM PDT 24	94184792 ps
T167	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2359846137	Aug 19 04:32:41 PM PDT 24	Aug 19 04:32:43 PM PDT 24	49136280 ps
T168	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1650634804	Aug 19 04:32:49 PM PDT 24	Aug 19 04:32:50 PM PDT 24	155184306 ps
T169	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.124557695	Aug 19 04:33:11 PM PDT 24	Aug 19 04:33:13 PM PDT 24	142231026 ps
T65	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.997071326	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:19 PM PDT 24	699499527 ps
T170	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3623726371	Aug 19 04:33:03 PM PDT 24	Aug 19 04:33:05 PM PDT 24	110940425 ps
T171	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4274357888	Aug 19 04:32:54 PM PDT 24	Aug 19 04:32:55 PM PDT 24	85255553 ps
T172	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2592640277	Aug 19 04:32:43 PM PDT 24	Aug 19 04:32:46 PM PDT 24	144662377 ps
T173	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1978153909	Aug 19 04:32:45 PM PDT 24	Aug 19 04:32:48 PM PDT 24	394190095 ps
T174	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2897760827	Aug 19 04:33:14 PM PDT 24	Aug 19 04:33:15 PM PDT 24	29697515 ps
T175	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.243980154	Aug 19 04:33:09 PM PDT 24	Aug 19 04:33:12 PM PDT 24	211185978 ps

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3796741726
Short name	T5
Test name
Test status
Simulation time	1357761470 ps
CPU time	5.48 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	207136 kb
Host	smart-c65d2f6a-8d6f-4c8e-bb81-8f116fae9ffc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3796741726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3796741726
Directory	/workspace/6.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/35.usbdev_intr_test.358497922
Short name	T15
Test name
Test status
Simulation time	35974065 ps
CPU time	0.77 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	206824 kb
Host	smart-42ae7e57-6839-465a-a7b6-1cdd3d36e67d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=358497922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.358497922
Directory	/workspace/35.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.440082137
Short name	T9
Test name
Test status
Simulation time	92614090 ps
CPU time	0.9 seconds
Started	Aug 19 04:32:53 PM PDT 24
Finished	Aug 19 04:32:54 PM PDT 24
Peak memory	207020 kb
Host	smart-7490cace-86bd-414a-b502-4a59078d5cbf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=440082137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.440082137
Directory	/workspace/1.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4033449494
Short name	T27
Test name
Test status
Simulation time	808154884 ps
CPU time	5.34 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:09 PM PDT 24
Peak memory	207268 kb
Host	smart-94ae3dde-7949-4809-a8cf-3bd56b14c95f
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4033449494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4033449494
Directory	/workspace/8.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.3647933910
Short name	T21
Test name
Test status
Simulation time	225951934 ps
CPU time	2.72 seconds
Started	Aug 19 04:33:00 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	207152 kb
Host	smart-2813c329-f3b2-4321-b30d-b7ab7a171931
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3647933910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.3647933910
Directory	/workspace/7.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_intr_test.3602902370
Short name	T17
Test name
Test status
Simulation time	55395569 ps
CPU time	0.76 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206872 kb
Host	smart-1bf94cfe-a711-4266-840c-d8d6b59bfb3a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3602902370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.3602902370
Directory	/workspace/19.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4241931295
Short name	T32
Test name
Test status
Simulation time	74233345 ps
CPU time	1.06 seconds
Started	Aug 19 04:33:02 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	206880 kb
Host	smart-7609c9a3-f8a7-410f-800a-eca6771fb4f3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4241931295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4241931295
Directory	/workspace/7.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3543822473
Short name	T76
Test name
Test status
Simulation time	41651244 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	206860 kb
Host	smart-21388592-8781-4755-ae57-5804f07c6b1e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3543822473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3543822473
Directory	/workspace/13.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1293180663
Short name	T10
Test name
Test status
Simulation time	239812098 ps
CPU time	1.13 seconds
Started	Aug 19 04:32:41 PM PDT 24
Finished	Aug 19 04:32:42 PM PDT 24
Peak memory	206920 kb
Host	smart-7f3f92ea-6f81-4858-965c-13868a3c3ebf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1293180663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1293180663
Directory	/workspace/0.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.604106338
Short name	T49
Test name
Test status
Simulation time	279092127 ps
CPU time	3.06 seconds
Started	Aug 19 04:33:26 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	220972 kb
Host	smart-0ea599c9-87f9-4402-860d-51ac4567baf5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=604106338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.604106338
Directory	/workspace/17.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2014583549
Short name	T48
Test name
Test status
Simulation time	366014092 ps
CPU time	2.58 seconds
Started	Aug 19 04:33:26 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	207248 kb
Host	smart-850f4313-e4b6-4c80-aa93-819548f2fb6d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2014583549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2014583549
Directory	/workspace/17.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_intr_test.1171009678
Short name	T59
Test name
Test status
Simulation time	48406842 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:26 PM PDT 24
Finished	Aug 19 04:33:27 PM PDT 24
Peak memory	206928 kb
Host	smart-598b70f6-f6fc-481d-a2a0-ad7e85f779ac
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1171009678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1171009678
Directory	/workspace/11.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2595771261
Short name	T66
Test name
Test status
Simulation time	965789290 ps
CPU time	4.85 seconds
Started	Aug 19 04:33:12 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	207184 kb
Host	smart-9cf4a730-d45a-4aa6-b7eb-ffbbe6254f30
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2595771261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2595771261
Directory	/workspace/11.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_errors.557361422
Short name	T19
Test name
Test status
Simulation time	262909291 ps
CPU time	2.86 seconds
Started	Aug 19 04:32:47 PM PDT 24
Finished	Aug 19 04:32:50 PM PDT 24
Peak memory	220280 kb
Host	smart-c64f1181-2d27-45f0-8d53-7f8775e4e3cd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=557361422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.557361422
Directory	/workspace/1.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3355272327
Short name	T51
Test name
Test status
Simulation time	204808697 ps
CPU time	2.3 seconds
Started	Aug 19 04:32:43 PM PDT 24
Finished	Aug 19 04:32:46 PM PDT 24
Peak memory	207152 kb
Host	smart-89d2c48a-b3c6-4a9e-be82-519cd095fb26
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3355272327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3355272327
Directory	/workspace/0.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.4190491672
Short name	T163
Test name
Test status
Simulation time	891412694 ps
CPU time	6.96 seconds
Started	Aug 19 04:32:43 PM PDT 24
Finished	Aug 19 04:32:50 PM PDT 24
Peak memory	207204 kb
Host	smart-0e62852a-e20f-434c-98c9-73f87058a242
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4190491672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.4190491672
Directory	/workspace/0.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3724373192
Short name	T67
Test name
Test status
Simulation time	89844485 ps
CPU time	2.05 seconds
Started	Aug 19 04:32:45 PM PDT 24
Finished	Aug 19 04:32:48 PM PDT 24
Peak memory	215208 kb
Host	smart-669038b8-93df-46f3-aee3-59a706cd2c22
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724373192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.3724373192
Directory	/workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1671640308
Short name	T103
Test name
Test status
Simulation time	97026732 ps
CPU time	0.82 seconds
Started	Aug 19 04:32:40 PM PDT 24
Finished	Aug 19 04:32:41 PM PDT 24
Peak memory	206980 kb
Host	smart-d5aa3593-4ab3-43a5-b141-2ab9015fd960
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1671640308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1671640308
Directory	/workspace/0.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_intr_test.3153709761
Short name	T84
Test name
Test status
Simulation time	49390345 ps
CPU time	0.74 seconds
Started	Aug 19 04:32:39 PM PDT 24
Finished	Aug 19 04:32:40 PM PDT 24
Peak memory	206868 kb
Host	smart-e9c15c1e-8af3-4b49-bbfa-52147cf747bd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3153709761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3153709761
Directory	/workspace/0.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.2359846137
Short name	T167
Test name
Test status
Simulation time	49136280 ps
CPU time	1.39 seconds
Started	Aug 19 04:32:41 PM PDT 24
Finished	Aug 19 04:32:43 PM PDT 24
Peak memory	215376 kb
Host	smart-37c577db-d513-436b-be64-7da5baad3d6c
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2359846137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.2359846137
Directory	/workspace/0.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2870496192
Short name	T124
Test name
Test status
Simulation time	257231664 ps
CPU time	2.67 seconds
Started	Aug 19 04:32:45 PM PDT 24
Finished	Aug 19 04:32:48 PM PDT 24
Peak memory	207004 kb
Host	smart-1e3155ca-2aa6-4cfb-b8b9-91dd4567a0a2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2870496192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2870496192
Directory	/workspace/0.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1650634804
Short name	T168
Test name
Test status
Simulation time	155184306 ps
CPU time	1.67 seconds
Started	Aug 19 04:32:49 PM PDT 24
Finished	Aug 19 04:32:50 PM PDT 24
Peak memory	207288 kb
Host	smart-1d5ef01f-784f-4785-a8cd-7632228882aa
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1650634804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1650634804
Directory	/workspace/0.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_errors.1954121310
Short name	T139
Test name
Test status
Simulation time	131749546 ps
CPU time	1.61 seconds
Started	Aug 19 04:32:44 PM PDT 24
Finished	Aug 19 04:32:46 PM PDT 24
Peak memory	207192 kb
Host	smart-ad1983d7-47d0-4969-b786-d9ff8e4bf108
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1954121310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.1954121310
Directory	/workspace/0.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4011597716
Short name	T53
Test name
Test status
Simulation time	937198129 ps
CPU time	5.21 seconds
Started	Aug 19 04:32:43 PM PDT 24
Finished	Aug 19 04:32:49 PM PDT 24
Peak memory	207296 kb
Host	smart-1e5d935d-a3bb-4f8a-988a-06afddcb5320
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4011597716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4011597716
Directory	/workspace/0.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2832444857
Short name	T34
Test name
Test status
Simulation time	125906785 ps
CPU time	3.28 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	207168 kb
Host	smart-01356455-104a-455b-ab22-9be5086f68ea
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2832444857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2832444857
Directory	/workspace/1.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.2588897939
Short name	T160
Test name
Test status
Simulation time	1717807975 ps
CPU time	11.92 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:33:07 PM PDT 24
Peak memory	207200 kb
Host	smart-5b0f1a54-a582-4855-aa6a-d6ea735d370e
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2588897939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.2588897939
Directory	/workspace/1.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2273105325
Short name	T6
Test name
Test status
Simulation time	73449162 ps
CPU time	1.92 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	215468 kb
Host	smart-9a38acf6-5621-4c2e-9e5f-2ed9a465b7cc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273105325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde v_csr_mem_rw_with_rand_reset.2273105325
Directory	/workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.4274357888
Short name	T171
Test name
Test status
Simulation time	85255553 ps
CPU time	1.01 seconds
Started	Aug 19 04:32:54 PM PDT 24
Finished	Aug 19 04:32:55 PM PDT 24
Peak memory	206876 kb
Host	smart-c6b8b2b6-5841-4a9f-a6ce-7bcc23a157e0
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4274357888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.4274357888
Directory	/workspace/1.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1173290838
Short name	T43
Test name
Test status
Simulation time	37380650 ps
CPU time	0.73 seconds
Started	Aug 19 04:32:45 PM PDT 24
Finished	Aug 19 04:32:46 PM PDT 24
Peak memory	206908 kb
Host	smart-f35f986b-069a-45d4-aed9-fa10543bbafb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1173290838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1173290838
Directory	/workspace/1.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2225742121
Short name	T23
Test name
Test status
Simulation time	153901230 ps
CPU time	1.63 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:57 PM PDT 24
Peak memory	215424 kb
Host	smart-5787b0a5-cd10-48bc-8e74-fde85fdc93d6
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2225742121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2225742121
Directory	/workspace/1.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.2592640277
Short name	T172
Test name
Test status
Simulation time	144662377 ps
CPU time	2.27 seconds
Started	Aug 19 04:32:43 PM PDT 24
Finished	Aug 19 04:32:46 PM PDT 24
Peak memory	207068 kb
Host	smart-f91fd1a1-9b84-4eaf-a4d2-5c25a77e0d41
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2592640277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.2592640277
Directory	/workspace/1.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.656283264
Short name	T158
Test name
Test status
Simulation time	79726091 ps
CPU time	1.03 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	207056 kb
Host	smart-061c4eca-0dde-41b8-974b-89b27d619f0c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=656283264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.656283264
Directory	/workspace/1.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1978153909
Short name	T173
Test name
Test status
Simulation time	394190095 ps
CPU time	2.74 seconds
Started	Aug 19 04:32:45 PM PDT 24
Finished	Aug 19 04:32:48 PM PDT 24
Peak memory	207188 kb
Host	smart-4309756d-e74a-480f-b281-8babf6e224a0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1978153909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1978153909
Directory	/workspace/1.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.357020181
Short name	T118
Test name
Test status
Simulation time	85402112 ps
CPU time	2.48 seconds
Started	Aug 19 04:33:27 PM PDT 24
Finished	Aug 19 04:33:30 PM PDT 24
Peak memory	215480 kb
Host	smart-d26c1cb6-8dcf-4212-a9c4-20f24f338af4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357020181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbde v_csr_mem_rw_with_rand_reset.357020181
Directory	/workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1811575075
Short name	T8
Test name
Test status
Simulation time	60492609 ps
CPU time	0.97 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:16 PM PDT 24
Peak memory	207028 kb
Host	smart-68dd754c-dac0-4139-97c8-2ef98beea002
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1811575075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1811575075
Directory	/workspace/10.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_intr_test.3070729477
Short name	T119
Test name
Test status
Simulation time	35794294 ps
CPU time	0.76 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206920 kb
Host	smart-55017dc2-efd6-4632-9d35-ebaa6455b131
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3070729477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3070729477
Directory	/workspace/10.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4156540219
Short name	T82
Test name
Test status
Simulation time	186723748 ps
CPU time	1.14 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:15 PM PDT 24
Peak memory	207000 kb
Host	smart-209cae7a-b983-4362-8b34-87e2911636b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4156540219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4156540219
Directory	/workspace/10.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2043888685
Short name	T28
Test name
Test status
Simulation time	80741264 ps
CPU time	2.25 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	207264 kb
Host	smart-26db7d73-02df-447f-96a9-bea8a7ac40fb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2043888685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2043888685
Directory	/workspace/10.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3344033856
Short name	T159
Test name
Test status
Simulation time	432867583 ps
CPU time	2.75 seconds
Started	Aug 19 04:33:06 PM PDT 24
Finished	Aug 19 04:33:09 PM PDT 24
Peak memory	207228 kb
Host	smart-1f2ed174-d585-4118-89cf-a373ff43e803
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3344033856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3344033856
Directory	/workspace/10.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2886149981
Short name	T52
Test name
Test status
Simulation time	173514359 ps
CPU time	1.47 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	215564 kb
Host	smart-17f7f6ff-5b1a-401a-a89b-e78a48dfe073
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886149981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.2886149981
Directory	/workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3875322109
Short name	T141
Test name
Test status
Simulation time	114845451 ps
CPU time	1.15 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	206840 kb
Host	smart-3a9e0996-ccd4-4a7f-8f81-f40140816f3d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3875322109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3875322109
Directory	/workspace/11.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3780873173
Short name	T116
Test name
Test status
Simulation time	227426431 ps
CPU time	1.56 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:16 PM PDT 24
Peak memory	207244 kb
Host	smart-8b7794e6-503a-4e3c-a223-eb73b0775e38
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3780873173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3780873173
Directory	/workspace/11.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.3984074705
Short name	T157
Test name
Test status
Simulation time	73297180 ps
CPU time	1.68 seconds
Started	Aug 19 04:33:12 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	207144 kb
Host	smart-e9015374-57ac-47cc-be7c-4b40febe1a33
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3984074705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.3984074705
Directory	/workspace/11.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.577300309
Short name	T4
Test name
Test status
Simulation time	96775060 ps
CPU time	2.57 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	215548 kb
Host	smart-15796f36-fec2-468a-bad1-bea2256feed0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577300309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde v_csr_mem_rw_with_rand_reset.577300309
Directory	/workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2146652353
Short name	T31
Test name
Test status
Simulation time	76986539 ps
CPU time	1.05 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:16 PM PDT 24
Peak memory	206856 kb
Host	smart-17069399-90aa-45c9-a41f-092237d53c7c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2146652353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2146652353
Directory	/workspace/12.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_intr_test.2224205192
Short name	T69
Test name
Test status
Simulation time	46115404 ps
CPU time	0.73 seconds
Started	Aug 19 04:33:09 PM PDT 24
Finished	Aug 19 04:33:10 PM PDT 24
Peak memory	206908 kb
Host	smart-927b1001-4939-4b77-8bfa-2acd1a99093e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2224205192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2224205192
Directory	/workspace/12.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2579320477
Short name	T3
Test name
Test status
Simulation time	158753170 ps
CPU time	1.32 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:30 PM PDT 24
Peak memory	207220 kb
Host	smart-d374b3b1-1b39-4e3b-802a-f0dfd206308f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2579320477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2579320477
Directory	/workspace/12.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.243980154
Short name	T175
Test name
Test status
Simulation time	211185978 ps
CPU time	2.18 seconds
Started	Aug 19 04:33:09 PM PDT 24
Finished	Aug 19 04:33:12 PM PDT 24
Peak memory	207232 kb
Host	smart-7e011b71-881c-45ec-bdf3-0c97557e6dff
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=243980154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.243980154
Directory	/workspace/12.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.4077949916
Short name	T110
Test name
Test status
Simulation time	636094800 ps
CPU time	3.12 seconds
Started	Aug 19 04:33:10 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	207132 kb
Host	smart-22678344-d1f5-4e06-94fc-fc2b8f1354e1
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4077949916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.4077949916
Directory	/workspace/12.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4015660352
Short name	T140
Test name
Test status
Simulation time	119747320 ps
CPU time	1.47 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	215444 kb
Host	smart-a24719ac-79b8-4735-9c55-2fa15e35da55
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015660352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.4015660352
Directory	/workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.801364592
Short name	T166
Test name
Test status
Simulation time	94184792 ps
CPU time	0.89 seconds
Started	Aug 19 04:33:15 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	206912 kb
Host	smart-e0d07e54-2973-4855-93d8-a402e5c8ef8f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=801364592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.801364592
Directory	/workspace/13.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.4164821924
Short name	T18
Test name
Test status
Simulation time	220604595 ps
CPU time	1.25 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	207040 kb
Host	smart-a50cbd13-b7d3-44fe-b42f-89b13737bf18
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4164821924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.4164821924
Directory	/workspace/13.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2409251176
Short name	T22
Test name
Test status
Simulation time	139017519 ps
CPU time	1.79 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	207252 kb
Host	smart-6116a926-34ec-4bd7-8668-d140f4440003
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2409251176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2409251176
Directory	/workspace/13.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3693030807
Short name	T62
Test name
Test status
Simulation time	1447332923 ps
CPU time	3.29 seconds
Started	Aug 19 04:33:09 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	207160 kb
Host	smart-283243b8-40a7-4856-bce8-273ab87991ab
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3693030807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3693030807
Directory	/workspace/13.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.124557695
Short name	T169
Test name
Test status
Simulation time	142231026 ps
CPU time	1.8 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	215504 kb
Host	smart-4142f5be-c61d-410d-95b6-94c108ec7066
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124557695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde v_csr_mem_rw_with_rand_reset.124557695
Directory	/workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1531969171
Short name	T120
Test name
Test status
Simulation time	52813006 ps
CPU time	0.97 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206924 kb
Host	smart-ab0e897c-78af-42c8-951d-b5dc3cceab18
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1531969171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1531969171
Directory	/workspace/14.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_intr_test.3134232831
Short name	T146
Test name
Test status
Simulation time	44547380 ps
CPU time	0.78 seconds
Started	Aug 19 04:33:27 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	206880 kb
Host	smart-0506ceff-da78-490b-9f7d-37334dc72580
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3134232831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3134232831
Directory	/workspace/14.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2308346003
Short name	T33
Test name
Test status
Simulation time	104726325 ps
CPU time	1.16 seconds
Started	Aug 19 04:33:24 PM PDT 24
Finished	Aug 19 04:33:25 PM PDT 24
Peak memory	207200 kb
Host	smart-66496d02-6db9-4cb1-ba28-570f7e70318e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2308346003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2308346003
Directory	/workspace/14.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2363892947
Short name	T78
Test name
Test status
Simulation time	137150588 ps
CPU time	3.22 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	215360 kb
Host	smart-516bac79-63a6-48f1-bfc1-09f24f42e83b
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2363892947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2363892947
Directory	/workspace/14.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1009223209
Short name	T61
Test name
Test status
Simulation time	864275083 ps
CPU time	4.8 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:33 PM PDT 24
Peak memory	207200 kb
Host	smart-effff772-a81a-4c77-abb4-e664761d8c6c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1009223209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1009223209
Directory	/workspace/14.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3970822070
Short name	T132
Test name
Test status
Simulation time	155165123 ps
CPU time	1.87 seconds
Started	Aug 19 04:33:16 PM PDT 24
Finished	Aug 19 04:33:18 PM PDT 24
Peak memory	215548 kb
Host	smart-bf64e930-0148-44cb-a254-1d70fcdb40bd
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970822070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd ev_csr_mem_rw_with_rand_reset.3970822070
Directory	/workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.2672181810
Short name	T143
Test name
Test status
Simulation time	65910098 ps
CPU time	1.04 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:13 PM PDT 24
Peak memory	206860 kb
Host	smart-e4f8d10c-7fb4-445b-86af-e1b5f1b8b2b3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2672181810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.2672181810
Directory	/workspace/15.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2874989311
Short name	T58
Test name
Test status
Simulation time	55244871 ps
CPU time	0.76 seconds
Started	Aug 19 04:33:21 PM PDT 24
Finished	Aug 19 04:33:21 PM PDT 24
Peak memory	206840 kb
Host	smart-7680f84a-cc1e-4483-9f10-57c832cea7ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2874989311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2874989311
Directory	/workspace/15.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.4119003174
Short name	T137
Test name
Test status
Simulation time	132028883 ps
CPU time	1.21 seconds
Started	Aug 19 04:33:12 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	207208 kb
Host	smart-cf1f6370-df64-4f61-bd5b-7c87ac668bf8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4119003174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.4119003174
Directory	/workspace/15.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3175882681
Short name	T72
Test name
Test status
Simulation time	78602701 ps
CPU time	1.83 seconds
Started	Aug 19 04:33:32 PM PDT 24
Finished	Aug 19 04:33:34 PM PDT 24
Peak memory	207220 kb
Host	smart-3d1e5501-6167-4fdb-9ebf-edc64f425886
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3175882681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3175882681
Directory	/workspace/15.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3492831534
Short name	T68
Test name
Test status
Simulation time	350427480 ps
CPU time	2.53 seconds
Started	Aug 19 04:33:29 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	207204 kb
Host	smart-55612dbd-fbf2-4ea6-91ce-5a7707da48fc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3492831534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3492831534
Directory	/workspace/15.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1537513763
Short name	T156
Test name
Test status
Simulation time	78740686 ps
CPU time	1.38 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:30 PM PDT 24
Peak memory	215476 kb
Host	smart-fdbd8977-1fc4-437d-9b82-8fd5978e0a5b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537513763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.1537513763
Directory	/workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.438301790
Short name	T97
Test name
Test status
Simulation time	79594543 ps
CPU time	1.02 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	206780 kb
Host	smart-c6f5cc1e-c985-4a11-8ece-217fc9f4b77c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=438301790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.438301790
Directory	/workspace/16.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_intr_test.711000496
Short name	T90
Test name
Test status
Simulation time	56009344 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:25 PM PDT 24
Finished	Aug 19 04:33:26 PM PDT 24
Peak memory	206868 kb
Host	smart-69f804b8-4447-4b40-9f83-c9cbfefdc846
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=711000496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.711000496
Directory	/workspace/16.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.234154686
Short name	T106
Test name
Test status
Simulation time	108047742 ps
CPU time	1.2 seconds
Started	Aug 19 04:33:12 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	207256 kb
Host	smart-cae1f025-8385-463b-be28-b7f274438f44
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=234154686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.234154686
Directory	/workspace/16.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.846131175
Short name	T161
Test name
Test status
Simulation time	85213987 ps
CPU time	2.21 seconds
Started	Aug 19 04:33:24 PM PDT 24
Finished	Aug 19 04:33:27 PM PDT 24
Peak memory	223652 kb
Host	smart-14028816-48ae-4bd4-80c0-713de37d2a8c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=846131175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.846131175
Directory	/workspace/16.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.997071326
Short name	T65
Test name
Test status
Simulation time	699499527 ps
CPU time	5.1 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	207184 kb
Host	smart-c0fee8dd-0040-430b-98c1-2b97bc785495
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=997071326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.997071326
Directory	/workspace/16.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2443833455
Short name	T85
Test name
Test status
Simulation time	163306892 ps
CPU time	2.57 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:16 PM PDT 24
Peak memory	215504 kb
Host	smart-e0e81ba4-c36e-43f7-ab4d-4f3f0f4bda06
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443833455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.2443833455
Directory	/workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.4153103652
Short name	T104
Test name
Test status
Simulation time	57524974 ps
CPU time	0.93 seconds
Started	Aug 19 04:33:32 PM PDT 24
Finished	Aug 19 04:33:33 PM PDT 24
Peak memory	206972 kb
Host	smart-85677b99-b82b-40f2-830b-cb8bb8f9551e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4153103652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.4153103652
Directory	/workspace/17.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1340911349
Short name	T16
Test name
Test status
Simulation time	77536250 ps
CPU time	0.84 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206920 kb
Host	smart-6a083011-db4e-4233-961d-ba87b563a5ca
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1340911349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1340911349
Directory	/workspace/17.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2319351313
Short name	T37
Test name
Test status
Simulation time	249543458 ps
CPU time	1.38 seconds
Started	Aug 19 04:33:21 PM PDT 24
Finished	Aug 19 04:33:22 PM PDT 24
Peak memory	206988 kb
Host	smart-111221bd-6ef1-4992-aed8-fe24a1b08f63
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2319351313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2319351313
Directory	/workspace/17.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2925411326
Short name	T148
Test name
Test status
Simulation time	95749257 ps
CPU time	1.75 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	215380 kb
Host	smart-2dc73a23-78f4-48e3-bc8d-9874027b818e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925411326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.2925411326
Directory	/workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1540506547
Short name	T46
Test name
Test status
Simulation time	78967492 ps
CPU time	1.2 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:31 PM PDT 24
Peak memory	206912 kb
Host	smart-f05524e2-d012-498a-a44b-79d74a8ea82c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1540506547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1540506547
Directory	/workspace/18.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2289740318
Short name	T55
Test name
Test status
Simulation time	64361592 ps
CPU time	0.82 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:31 PM PDT 24
Peak memory	206916 kb
Host	smart-b9584147-17d0-4901-803e-5a111d7754cd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2289740318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2289740318
Directory	/workspace/18.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.161852253
Short name	T164
Test name
Test status
Simulation time	210694434 ps
CPU time	1.6 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	207184 kb
Host	smart-8bec9070-ee3a-4765-b9e2-770c98d45162
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=161852253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.161852253
Directory	/workspace/18.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1690898932
Short name	T20
Test name
Test status
Simulation time	222277620 ps
CPU time	2.73 seconds
Started	Aug 19 04:33:29 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	207140 kb
Host	smart-45968490-404c-49d2-850b-9370515c3aa7
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1690898932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1690898932
Directory	/workspace/18.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.4000292860
Short name	T60
Test name
Test status
Simulation time	558884462 ps
CPU time	4.32 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:35 PM PDT 24
Peak memory	207168 kb
Host	smart-d35260ff-9645-4acc-ac6a-251c8e57a9dd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4000292860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.4000292860
Directory	/workspace/18.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.501368652
Short name	T117
Test name
Test status
Simulation time	201362593 ps
CPU time	1.71 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:20 PM PDT 24
Peak memory	215412 kb
Host	smart-3d68b26f-4aba-4c91-80a9-c3184932af0a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501368652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde v_csr_mem_rw_with_rand_reset.501368652
Directory	/workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.2533330756
Short name	T122
Test name
Test status
Simulation time	33596068 ps
CPU time	0.84 seconds
Started	Aug 19 04:33:31 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	206912 kb
Host	smart-857da698-0fae-4232-801b-22262ff8b63f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2533330756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.2533330756
Directory	/workspace/19.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1641990879
Short name	T91
Test name
Test status
Simulation time	289597067 ps
CPU time	1.69 seconds
Started	Aug 19 04:33:34 PM PDT 24
Finished	Aug 19 04:33:36 PM PDT 24
Peak memory	207228 kb
Host	smart-af4979f9-2c47-4a78-bfea-7dc2e33f2d20
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1641990879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1641990879
Directory	/workspace/19.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3415488960
Short name	T147
Test name
Test status
Simulation time	300443423 ps
CPU time	3.34 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:18 PM PDT 24
Peak memory	221032 kb
Host	smart-5848c053-3ae7-4153-ae45-15323e7a8fdd
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3415488960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3415488960
Directory	/workspace/19.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.1863085778
Short name	T26
Test name
Test status
Simulation time	356798466 ps
CPU time	2.46 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	207248 kb
Host	smart-c80ea69b-edb5-428a-bac2-db64f3cb62f3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1863085778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.1863085778
Directory	/workspace/19.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.794233841
Short name	T131
Test name
Test status
Simulation time	204600866 ps
CPU time	2.25 seconds
Started	Aug 19 04:33:01 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	207112 kb
Host	smart-7c7b904a-f526-449a-95da-b9c5ad102dfc
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=794233841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.794233841
Directory	/workspace/2.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1145662123
Short name	T44
Test name
Test status
Simulation time	318935245 ps
CPU time	6.9 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:06 PM PDT 24
Peak memory	207052 kb
Host	smart-96b48171-a3db-4769-8b9f-a962e0bc1dc1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1145662123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1145662123
Directory	/workspace/2.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3915592236
Short name	T13
Test name
Test status
Simulation time	125632410 ps
CPU time	0.8 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:56 PM PDT 24
Peak memory	206912 kb
Host	smart-3bb6fde0-6e4d-443e-b181-b832d3e63ac5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3915592236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3915592236
Directory	/workspace/2.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2746032057
Short name	T105
Test name
Test status
Simulation time	75758679 ps
CPU time	1.9 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:05 PM PDT 24
Peak memory	215412 kb
Host	smart-d6f93457-9596-474f-8850-2ae89e7a45b0
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746032057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.2746032057
Directory	/workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3623726371
Short name	T170
Test name
Test status
Simulation time	110940425 ps
CPU time	1.08 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:05 PM PDT 24
Peak memory	206976 kb
Host	smart-a4041246-6b8f-4f0c-b516-84e53583873a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3623726371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3623726371
Directory	/workspace/2.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_intr_test.210923811
Short name	T56
Test name
Test status
Simulation time	42234644 ps
CPU time	0.77 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:56 PM PDT 24
Peak memory	206880 kb
Host	smart-ac24fd6c-eda3-4346-9c45-1bd7665774cc
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=210923811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.210923811
Directory	/workspace/2.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.4197334936
Short name	T144
Test name
Test status
Simulation time	72143342 ps
CPU time	1.4 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:56 PM PDT 24
Peak memory	215388 kb
Host	smart-1ae05c74-5585-4226-8257-4742e31427cc
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4197334936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.4197334936
Directory	/workspace/2.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.887859001
Short name	T25
Test name
Test status
Simulation time	96480087 ps
CPU time	2.37 seconds
Started	Aug 19 04:33:00 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	207056 kb
Host	smart-1a424b47-4982-4458-8107-6998514848b2
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=887859001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.887859001
Directory	/workspace/2.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3695841321
Short name	T125
Test name
Test status
Simulation time	58026122 ps
CPU time	1.06 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	207172 kb
Host	smart-7178783a-6ee0-4dae-96b2-fba80d763980
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3695841321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3695841321
Directory	/workspace/2.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.4033987506
Short name	T70
Test name
Test status
Simulation time	65571468 ps
CPU time	1.58 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	207064 kb
Host	smart-1344357a-d309-430d-ae9e-ca09f080feee
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4033987506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.4033987506
Directory	/workspace/2.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.939082803
Short name	T29
Test name
Test status
Simulation time	407074913 ps
CPU time	2.88 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	207264 kb
Host	smart-47af2c1d-99ce-4efe-a68b-eabdfe5004f9
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=939082803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.939082803
Directory	/workspace/2.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/20.usbdev_intr_test.1630400719
Short name	T81
Test name
Test status
Simulation time	51009522 ps
CPU time	0.74 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206920 kb
Host	smart-f4fd5475-4577-42f2-a1e7-baf091465af5
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1630400719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1630400719
Directory	/workspace/20.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/21.usbdev_intr_test.1055174087
Short name	T102
Test name
Test status
Simulation time	37045963 ps
CPU time	0.72 seconds
Started	Aug 19 04:33:31 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	206924 kb
Host	smart-5ccbfbeb-1959-4647-84f0-187c25b09db7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1055174087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1055174087
Directory	/workspace/21.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/22.usbdev_intr_test.2229481221
Short name	T80
Test name
Test status
Simulation time	84355994 ps
CPU time	0.73 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206920 kb
Host	smart-f5242c6d-25d2-43a9-ae20-56de1773b8b2
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2229481221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2229481221
Directory	/workspace/22.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/23.usbdev_intr_test.4067087238
Short name	T112
Test name
Test status
Simulation time	64463719 ps
CPU time	0.77 seconds
Started	Aug 19 04:33:16 PM PDT 24
Finished	Aug 19 04:33:17 PM PDT 24
Peak memory	206880 kb
Host	smart-99f1c8b7-63b6-47b3-a7cd-d59f05cb68f9
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4067087238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.4067087238
Directory	/workspace/23.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/24.usbdev_intr_test.2897760827
Short name	T174
Test name
Test status
Simulation time	29697515 ps
CPU time	0.71 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:15 PM PDT 24
Peak memory	206892 kb
Host	smart-616af90a-455d-42c7-a3db-77c1a9f0c867
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2897760827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2897760827
Directory	/workspace/24.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/25.usbdev_intr_test.3529843494
Short name	T96
Test name
Test status
Simulation time	53914281 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206872 kb
Host	smart-b9efb85e-b109-457b-928d-d1b17f84450c
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3529843494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.3529843494
Directory	/workspace/25.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/26.usbdev_intr_test.1360060473
Short name	T138
Test name
Test status
Simulation time	67236029 ps
CPU time	0.76 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	206780 kb
Host	smart-aa6e644f-f7b5-4e9f-aed3-4c4fcbf3b6e6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1360060473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1360060473
Directory	/workspace/26.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/27.usbdev_intr_test.2481310825
Short name	T7
Test name
Test status
Simulation time	42701432 ps
CPU time	0.69 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206828 kb
Host	smart-8d719f97-8513-410d-99db-4c0375392aa0
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2481310825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2481310825
Directory	/workspace/27.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/28.usbdev_intr_test.3473211366
Short name	T145
Test name
Test status
Simulation time	36180507 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:31 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	206924 kb
Host	smart-9e80f3f5-8e3d-407c-acc4-1f7b44794a46
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3473211366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3473211366
Directory	/workspace/28.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/29.usbdev_intr_test.3194203840
Short name	T95
Test name
Test status
Simulation time	35038354 ps
CPU time	0.69 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206840 kb
Host	smart-0e670a7f-73ac-4685-b262-29d87a60b383
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3194203840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3194203840
Directory	/workspace/29.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.2121817086
Short name	T35
Test name
Test status
Simulation time	119130974 ps
CPU time	3.28 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	207152 kb
Host	smart-f6525368-35f8-47a9-b099-a092e2d09526
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2121817086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.2121817086
Directory	/workspace/3.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3003104167
Short name	T40
Test name
Test status
Simulation time	835961158 ps
CPU time	5.1 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	207200 kb
Host	smart-35db9a21-f7a9-41aa-9baf-9603c62440cf
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3003104167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3003104167
Directory	/workspace/3.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.1637926308
Short name	T12
Test name
Test status
Simulation time	93387397 ps
CPU time	0.99 seconds
Started	Aug 19 04:33:00 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	207004 kb
Host	smart-92e07bf8-a82e-404f-8e61-c9c92b4dff8e
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1637926308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.1637926308
Directory	/workspace/3.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3341387031
Short name	T57
Test name
Test status
Simulation time	84449406 ps
CPU time	1.18 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	216968 kb
Host	smart-3ca52b87-abe9-40f8-b28f-f0b1a997d276
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341387031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.3341387031
Directory	/workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.3012669286
Short name	T38
Test name
Test status
Simulation time	90124727 ps
CPU time	1.01 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:56 PM PDT 24
Peak memory	206868 kb
Host	smart-18e9821a-a630-489a-b12d-58edfc68ecd9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3012669286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.3012669286
Directory	/workspace/3.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_intr_test.3661587800
Short name	T77
Test name
Test status
Simulation time	41332996 ps
CPU time	0.72 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	206904 kb
Host	smart-61490e6f-242d-43ae-889a-78cde577a8d6
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3661587800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3661587800
Directory	/workspace/3.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.2782608927
Short name	T39
Test name
Test status
Simulation time	79936972 ps
CPU time	2.21 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	215288 kb
Host	smart-f91350b3-aa94-4bb2-bd45-8ad25b7c2ddd
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2782608927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.2782608927
Directory	/workspace/3.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2482822914
Short name	T24
Test name
Test status
Simulation time	163071123 ps
CPU time	3.87 seconds
Started	Aug 19 04:33:01 PM PDT 24
Finished	Aug 19 04:33:05 PM PDT 24
Peak memory	207072 kb
Host	smart-0ea74d22-62d3-4c18-8adf-ff202692dac0
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2482822914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2482822914
Directory	/workspace/3.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.4030609045
Short name	T155
Test name
Test status
Simulation time	208714767 ps
CPU time	1.31 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	207192 kb
Host	smart-1aa98087-5d2e-4453-9c98-6dea1ece8059
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4030609045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.4030609045
Directory	/workspace/3.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2303354173
Short name	T136
Test name
Test status
Simulation time	85094175 ps
CPU time	2.31 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	220648 kb
Host	smart-7ff0eef6-8fa1-4a0f-89e5-10a6db41f697
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2303354173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2303354173
Directory	/workspace/3.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.945060453
Short name	T30
Test name
Test status
Simulation time	795776920 ps
CPU time	4.63 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	207300 kb
Host	smart-5bb42698-7a05-4f30-911f-5e0e0afc7abb
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=945060453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.945060453
Directory	/workspace/3.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/30.usbdev_intr_test.1438306051
Short name	T153
Test name
Test status
Simulation time	38999809 ps
CPU time	0.76 seconds
Started	Aug 19 04:33:34 PM PDT 24
Finished	Aug 19 04:33:35 PM PDT 24
Peak memory	206836 kb
Host	smart-5bb75d16-e8a7-41fa-82c5-8995f659f20e
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1438306051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.1438306051
Directory	/workspace/30.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/31.usbdev_intr_test.3060214879
Short name	T94
Test name
Test status
Simulation time	42920931 ps
CPU time	0.78 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206372 kb
Host	smart-fed85b72-8e07-4827-ab1e-0c305a29728b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3060214879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.3060214879
Directory	/workspace/31.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/32.usbdev_intr_test.3390620083
Short name	T89
Test name
Test status
Simulation time	84318827 ps
CPU time	0.84 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206924 kb
Host	smart-494322c7-437d-4589-b600-33d07bb87655
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3390620083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3390620083
Directory	/workspace/32.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/33.usbdev_intr_test.599897811
Short name	T93
Test name
Test status
Simulation time	62080228 ps
CPU time	0.8 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206824 kb
Host	smart-34b49273-f51c-476d-9ff1-ba840ffe232b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=599897811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.599897811
Directory	/workspace/33.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/34.usbdev_intr_test.1938836150
Short name	T115
Test name
Test status
Simulation time	38941324 ps
CPU time	0.71 seconds
Started	Aug 19 04:33:31 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	206840 kb
Host	smart-e2f1e3ca-f1c2-4d62-a585-3d308c9d547f
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1938836150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1938836150
Directory	/workspace/34.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2028110075
Short name	T83
Test name
Test status
Simulation time	49868861 ps
CPU time	0.88 seconds
Started	Aug 19 04:33:19 PM PDT 24
Finished	Aug 19 04:33:20 PM PDT 24
Peak memory	206828 kb
Host	smart-e245363b-d345-49e3-b8e0-9acd180b3dfb
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2028110075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2028110075
Directory	/workspace/36.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/37.usbdev_intr_test.2588907167
Short name	T88
Test name
Test status
Simulation time	51589667 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206832 kb
Host	smart-cb7ec816-8b77-4b4b-9cd7-b5ca66478220
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2588907167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.2588907167
Directory	/workspace/37.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/38.usbdev_intr_test.3553891677
Short name	T108
Test name
Test status
Simulation time	41027502 ps
CPU time	0.75 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206860 kb
Host	smart-43ba7463-ac5b-4115-92e1-abc4692156af
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3553891677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3553891677
Directory	/workspace/38.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1673889450
Short name	T75
Test name
Test status
Simulation time	44612370 ps
CPU time	0.71 seconds
Started	Aug 19 04:33:18 PM PDT 24
Finished	Aug 19 04:33:19 PM PDT 24
Peak memory	206472 kb
Host	smart-ff01b0ac-3189-45ef-ad63-776baa5a9c4b
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1673889450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1673889450
Directory	/workspace/39.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3003289259
Short name	T154
Test name
Test status
Simulation time	431406370 ps
CPU time	3.64 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:07 PM PDT 24
Peak memory	207164 kb
Host	smart-9436b5f0-ecdc-49c0-93e3-22888091bf0b
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3003289259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3003289259
Directory	/workspace/4.usbdev_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.4267026999
Short name	T41
Test name
Test status
Simulation time	900968252 ps
CPU time	7.18 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	207116 kb
Host	smart-0e7c274d-76f5-47d8-b079-5e875be590f7
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4267026999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.4267026999
Directory	/workspace/4.usbdev_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.402866524
Short name	T11
Test name
Test status
Simulation time	142740608 ps
CPU time	0.86 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:57 PM PDT 24
Peak memory	206960 kb
Host	smart-9e25a79c-6d37-47d7-814f-74f45b583669
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=402866524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.402866524
Directory	/workspace/4.usbdev_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.894255911
Short name	T99
Test name
Test status
Simulation time	79380530 ps
CPU time	1.77 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	215392 kb
Host	smart-073a9784-aced-4312-916f-3bef73d4bb4b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894255911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev _csr_mem_rw_with_rand_reset.894255911
Directory	/workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.4287538722
Short name	T162
Test name
Test status
Simulation time	54378312 ps
CPU time	0.79 seconds
Started	Aug 19 04:33:02 PM PDT 24
Finished	Aug 19 04:33:02 PM PDT 24
Peak memory	206876 kb
Host	smart-36a5f68f-9fcf-4f84-8679-dfbb0415fc5e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=4287538722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.4287538722
Directory	/workspace/4.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3840187346
Short name	T42
Test name
Test status
Simulation time	44723245 ps
CPU time	0.71 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:55 PM PDT 24
Peak memory	206876 kb
Host	smart-5aadf63c-49d6-4250-9a33-49feed01c776
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3840187346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3840187346
Directory	/workspace/4.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2180710482
Short name	T45
Test name
Test status
Simulation time	149983122 ps
CPU time	2.3 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	215428 kb
Host	smart-a3c42627-5622-45f9-abc4-70029d039784
User	root
Command	/workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=2180710482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2180710482
Directory	/workspace/4.usbdev_mem_partial_access/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1933959202
Short name	T107
Test name
Test status
Simulation time	511906714 ps
CPU time	4.36 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	207124 kb
Host	smart-e59224b7-2b83-44ab-a46e-767cc050f72c
User	root
Command	/workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1933959202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1933959202
Directory	/workspace/4.usbdev_mem_walk/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2836420962
Short name	T14
Test name
Test status
Simulation time	93772202 ps
CPU time	1.07 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	207120 kb
Host	smart-53dbc826-bb86-43e4-a3ab-6ced20721391
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2836420962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2836420962
Directory	/workspace/4.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.107864082
Short name	T2
Test name
Test status
Simulation time	107549103 ps
CPU time	1.59 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	207264 kb
Host	smart-9337e5e3-47d1-45e3-ad5a-f4ab16168072
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=107864082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.107864082
Directory	/workspace/4.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.144898634
Short name	T63
Test name
Test status
Simulation time	675401123 ps
CPU time	4.54 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	207120 kb
Host	smart-f3eadd6b-4953-4ac8-8b27-434fcca48a57
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=144898634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.144898634
Directory	/workspace/4.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/40.usbdev_intr_test.501948232
Short name	T109
Test name
Test status
Simulation time	40701807 ps
CPU time	0.74 seconds
Started	Aug 19 04:33:11 PM PDT 24
Finished	Aug 19 04:33:11 PM PDT 24
Peak memory	206804 kb
Host	smart-b6bb0cad-9c5c-4134-a621-fcca9a15078a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=501948232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.501948232
Directory	/workspace/40.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/41.usbdev_intr_test.2970178524
Short name	T121
Test name
Test status
Simulation time	40018779 ps
CPU time	0.71 seconds
Started	Aug 19 04:33:27 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	206960 kb
Host	smart-aeaac64c-2c37-41eb-9e82-5c4258d073d3
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2970178524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2970178524
Directory	/workspace/41.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/42.usbdev_intr_test.4100371915
Short name	T79
Test name
Test status
Simulation time	44235353 ps
CPU time	0.7 seconds
Started	Aug 19 04:33:28 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	206840 kb
Host	smart-dc61d9cf-63ab-49f4-9f05-4961f50eab96
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4100371915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.4100371915
Directory	/workspace/42.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/43.usbdev_intr_test.1220341964
Short name	T150
Test name
Test status
Simulation time	107284938 ps
CPU time	0.83 seconds
Started	Aug 19 04:33:14 PM PDT 24
Finished	Aug 19 04:33:15 PM PDT 24
Peak memory	206852 kb
Host	smart-037cf3ca-cf39-4184-ad51-fdf3856ed085
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1220341964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1220341964
Directory	/workspace/43.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/44.usbdev_intr_test.3994047709
Short name	T54
Test name
Test status
Simulation time	91179866 ps
CPU time	0.84 seconds
Started	Aug 19 04:33:27 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	206840 kb
Host	smart-054ddc2e-252c-48f8-bf40-74f4c71d372d
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3994047709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3994047709
Directory	/workspace/44.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/45.usbdev_intr_test.1102245287
Short name	T152
Test name
Test status
Simulation time	53747561 ps
CPU time	0.74 seconds
Started	Aug 19 04:33:27 PM PDT 24
Finished	Aug 19 04:33:28 PM PDT 24
Peak memory	206840 kb
Host	smart-14ba1c62-7f43-4902-82db-bc29dba8aacf
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1102245287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.1102245287
Directory	/workspace/45.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/46.usbdev_intr_test.2803994916
Short name	T73
Test name
Test status
Simulation time	72132109 ps
CPU time	0.81 seconds
Started	Aug 19 04:33:29 PM PDT 24
Finished	Aug 19 04:33:30 PM PDT 24
Peak memory	206844 kb
Host	smart-145d39d7-f246-467f-a87c-3e39f8b4cbdd
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2803994916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2803994916
Directory	/workspace/46.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/47.usbdev_intr_test.3936655750
Short name	T87
Test name
Test status
Simulation time	58170607 ps
CPU time	0.73 seconds
Started	Aug 19 04:33:30 PM PDT 24
Finished	Aug 19 04:33:31 PM PDT 24
Peak memory	206840 kb
Host	smart-13a2b3a1-e8b4-47fd-bdcd-f54ad6401502
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3936655750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.3936655750
Directory	/workspace/47.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/48.usbdev_intr_test.1800688663
Short name	T74
Test name
Test status
Simulation time	74432554 ps
CPU time	0.79 seconds
Started	Aug 19 04:33:10 PM PDT 24
Finished	Aug 19 04:33:11 PM PDT 24
Peak memory	206904 kb
Host	smart-cd5d554b-5c67-482f-ad90-3ab932593ade
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1800688663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1800688663
Directory	/workspace/48.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/49.usbdev_intr_test.2483798643
Short name	T133
Test name
Test status
Simulation time	40315194 ps
CPU time	0.74 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	206888 kb
Host	smart-1a968707-ce06-4942-8db7-f664fc2a5685
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2483798643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2483798643
Directory	/workspace/49.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.180487277
Short name	T98
Test name
Test status
Simulation time	137489266 ps
CPU time	1.83 seconds
Started	Aug 19 04:32:57 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	215548 kb
Host	smart-3e8226e7-69b7-4f7b-8e5b-7ffc008c9db1
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180487277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev _csr_mem_rw_with_rand_reset.180487277
Directory	/workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.3550639226
Short name	T123
Test name
Test status
Simulation time	53538218 ps
CPU time	0.83 seconds
Started	Aug 19 04:32:53 PM PDT 24
Finished	Aug 19 04:32:54 PM PDT 24
Peak memory	206992 kb
Host	smart-a1d211de-9794-447f-8d33-c30eba36279c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3550639226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.3550639226
Directory	/workspace/5.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_intr_test.187232114
Short name	T135
Test name
Test status
Simulation time	65877112 ps
CPU time	0.77 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	206844 kb
Host	smart-98cb5438-55a5-43c5-8da8-aa402ec35522
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=187232114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.187232114
Directory	/workspace/5.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3202355129
Short name	T36
Test name
Test status
Simulation time	327328499 ps
CPU time	2.17 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:57 PM PDT 24
Peak memory	207248 kb
Host	smart-3f540c31-1154-4f3f-8313-a6161b288150
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3202355129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3202355129
Directory	/workspace/5.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1933183863
Short name	T126
Test name
Test status
Simulation time	193576832 ps
CPU time	3.2 seconds
Started	Aug 19 04:33:00 PM PDT 24
Finished	Aug 19 04:33:04 PM PDT 24
Peak memory	207144 kb
Host	smart-87fb8276-4dde-499e-8181-d8e1c7fe7249
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1933183863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1933183863
Directory	/workspace/5.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3206286359
Short name	T127
Test name
Test status
Simulation time	308326963 ps
CPU time	2.51 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	207212 kb
Host	smart-87f8f476-a5c7-4985-bc63-3a943f3f8319
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3206286359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3206286359
Directory	/workspace/5.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.889050451
Short name	T134
Test name
Test status
Simulation time	137014398 ps
CPU time	1.32 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:05 PM PDT 24
Peak memory	215184 kb
Host	smart-f1594880-f24e-407c-a0dd-fead2008edd6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889050451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev _csr_mem_rw_with_rand_reset.889050451
Directory	/workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1579281234
Short name	T100
Test name
Test status
Simulation time	71055076 ps
CPU time	0.92 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	206812 kb
Host	smart-cc59c445-9107-48be-a27e-8bd7f78b103c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1579281234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1579281234
Directory	/workspace/6.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_intr_test.81532558
Short name	T114
Test name
Test status
Simulation time	33690117 ps
CPU time	0.75 seconds
Started	Aug 19 04:32:58 PM PDT 24
Finished	Aug 19 04:32:59 PM PDT 24
Peak memory	206844 kb
Host	smart-d9df90e9-868b-4e05-a2b6-b200dce3d1e7
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=81532558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.81532558
Directory	/workspace/6.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3060288982
Short name	T71
Test name
Test status
Simulation time	203664572 ps
CPU time	1.72 seconds
Started	Aug 19 04:33:00 PM PDT 24
Finished	Aug 19 04:33:02 PM PDT 24
Peak memory	207192 kb
Host	smart-c7790476-5cf0-493d-bb70-0cffeef65972
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3060288982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3060288982
Directory	/workspace/6.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3904913850
Short name	T111
Test name
Test status
Simulation time	144737374 ps
CPU time	1.87 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:01 PM PDT 24
Peak memory	215476 kb
Host	smart-89e65dcb-30a5-4345-a2a2-838acf29b571
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3904913850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3904913850
Directory	/workspace/6.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2382676327
Short name	T86
Test name
Test status
Simulation time	70494299 ps
CPU time	1.48 seconds
Started	Aug 19 04:32:59 PM PDT 24
Finished	Aug 19 04:33:00 PM PDT 24
Peak memory	215536 kb
Host	smart-22d7757a-1b40-4200-be9f-9fe065f02823
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382676327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.2382676327
Directory	/workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_intr_test.1008696068
Short name	T128
Test name
Test status
Simulation time	35231736 ps
CPU time	0.67 seconds
Started	Aug 19 04:32:54 PM PDT 24
Finished	Aug 19 04:32:55 PM PDT 24
Peak memory	206912 kb
Host	smart-c6346ada-5f91-4610-a4bf-1ab8ee3e8b7a
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1008696068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.1008696068
Directory	/workspace/7.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2101467639
Short name	T142
Test name
Test status
Simulation time	78851953 ps
CPU time	1.03 seconds
Started	Aug 19 04:33:01 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	206964 kb
Host	smart-707dde7e-3d52-4a88-aca5-0e0344c26ac4
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2101467639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2101467639
Directory	/workspace/7.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2824727985
Short name	T64
Test name
Test status
Simulation time	1021811653 ps
CPU time	3.14 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:06 PM PDT 24
Peak memory	207268 kb
Host	smart-ab80f422-0929-4629-8d79-7c79c94edd60
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2824727985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2824727985
Directory	/workspace/7.usbdev_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.1525673724
Short name	T92
Test name
Test status
Simulation time	122230557 ps
CPU time	1.69 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:05 PM PDT 24
Peak memory	215552 kb
Host	smart-56dc2916-d33e-4b42-8f8a-dd18158913e6
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525673724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.1525673724
Directory	/workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.602318948
Short name	T1
Test name
Test status
Simulation time	86375938 ps
CPU time	1.02 seconds
Started	Aug 19 04:32:55 PM PDT 24
Finished	Aug 19 04:32:56 PM PDT 24
Peak memory	206980 kb
Host	smart-c91b8177-56eb-45c1-aa61-e106dcd62726
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=602318948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.602318948
Directory	/workspace/8.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_intr_test.564708164
Short name	T149
Test name
Test status
Simulation time	61861331 ps
CPU time	0.83 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:03 PM PDT 24
Peak memory	206920 kb
Host	smart-f653b386-5d39-4a7e-a489-e6113c34a053
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=564708164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.564708164
Directory	/workspace/8.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3734674123
Short name	T130
Test name
Test status
Simulation time	184942926 ps
CPU time	1.95 seconds
Started	Aug 19 04:32:56 PM PDT 24
Finished	Aug 19 04:32:58 PM PDT 24
Peak memory	207224 kb
Host	smart-b524e249-7a11-4bb9-9449-08646125cd2f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3734674123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3734674123
Directory	/workspace/8.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.3764483748
Short name	T47
Test name
Test status
Simulation time	308066797 ps
CPU time	2.91 seconds
Started	Aug 19 04:33:03 PM PDT 24
Finished	Aug 19 04:33:06 PM PDT 24
Peak memory	207276 kb
Host	smart-ff0ac448-e8f4-42ad-a393-6dd782d9d012
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3764483748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.3764483748
Directory	/workspace/8.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.327541326
Short name	T165
Test name
Test status
Simulation time	225232822 ps
CPU time	1.95 seconds
Started	Aug 19 04:33:23 PM PDT 24
Finished	Aug 19 04:33:25 PM PDT 24
Peak memory	215440 kb
Host	smart-7426732c-5ec2-4e8c-81aa-0c3ae8b5c735
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327541326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev _csr_mem_rw_with_rand_reset.327541326
Directory	/workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.2125185573
Short name	T151
Test name
Test status
Simulation time	67541644 ps
CPU time	0.84 seconds
Started	Aug 19 04:33:13 PM PDT 24
Finished	Aug 19 04:33:14 PM PDT 24
Peak memory	206820 kb
Host	smart-0f6a0be3-dc2c-4be8-92ea-07297dee9856
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2125185573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.2125185573
Directory	/workspace/9.usbdev_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_intr_test.3944117317
Short name	T113
Test name
Test status
Simulation time	35871093 ps
CPU time	0.74 seconds
Started	Aug 19 04:33:12 PM PDT 24
Finished	Aug 19 04:33:12 PM PDT 24
Peak memory	206792 kb
Host	smart-2898474c-cfff-4400-a90b-63ebfb355982
User	root
Command	/workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3944117317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3944117317
Directory	/workspace/9.usbdev_intr_test/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2303498825
Short name	T101
Test name
Test status
Simulation time	120422213 ps
CPU time	1.19 seconds
Started	Aug 19 04:33:31 PM PDT 24
Finished	Aug 19 04:33:32 PM PDT 24
Peak memory	207304 kb
Host	smart-85645308-bd38-4f30-a438-50a57ce1ef75
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2303498825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2303498825
Directory	/workspace/9.usbdev_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_errors.488178171
Short name	T129
Test name
Test status
Simulation time	92438773 ps
CPU time	2.39 seconds
Started	Aug 19 04:33:07 PM PDT 24
Finished	Aug 19 04:33:10 PM PDT 24
Peak memory	215488 kb
Host	smart-74fd0f10-7338-481d-bf7b-29a243537d65
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=488178171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.488178171
Directory	/workspace/9.usbdev_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4206661611
Short name	T50
Test name
Test status
Simulation time	1084177775 ps
CPU time	3.7 seconds
Started	Aug 19 04:33:25 PM PDT 24
Finished	Aug 19 04:33:29 PM PDT 24
Peak memory	207304 kb
Host	smart-7a5af26f-5b9c-44a8-9be3-2ec806dd75f0
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4206661611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4206661611
Directory	/workspace/9.usbdev_tl_intg_err/latest