Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
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Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 18 0 0.00
Crosses 96 96 0 0.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_dir 2 2 0 0.00 100 1 1 2
cp_endp 12 12 0 0.00 100 1 1 0
cp_pid 4 4 0 0.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_X_dir_X_endp 96 96 0 0.00 100 1 1 0


Summary for Variable cp_dir

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 2 0 0.00


Automatically Generated Bins for cp_dir

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[0] - auto[1]] -- -- 2



Summary for Variable cp_endp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 12 0 0.00


User Defined Bins for cp_endp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
endpoints[0x0] 0 1 1
endpoints[0x1] 0 1 1
endpoints[0x2] 0 1 1
endpoints[0x3] 0 1 1
endpoints[0x4] 0 1 1
endpoints[0x5] 0 1 1
endpoints[0x6] 0 1 1
endpoints[0x7] 0 1 1
endpoints[0x8] 0 1 1
endpoints[0x9] 0 1 1
endpoints[0xa] 0 1 1
endpoints[0xb] 0 1 1



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 4 0 0.00


User Defined Bins for cp_pid

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
nak 0 1 1
ack 0 1 1
data1 0 1 1
data0 0 1 1



Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 96 96 0 0.00 96


Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Uncovered bins
cp_pidcp_dircp_endpCOUNTAT LEASTNUMBERSTATUS
* * * -- -- 96

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