Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
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Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
0.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv



Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 11 11 0 0.00
Crosses 54 54 0 0.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_avout 3 3 0 0.00 100 1 1 0
cp_avsetup 3 3 0 0.00 100 1 1 0
cp_pid 2 2 0 0.00 100 1 1 0
cp_rx 3 3 0 0.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_fifo_X_pid 54 54 0 0.00 100 1 1 0


Summary for Variable cp_avout

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_avout

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
full 0 1 1
solo 0 1 1
empty 0 1 1



Summary for Variable cp_avsetup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_avsetup

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
full 0 1 1
solo 0 1 1
empty 0 1 1



Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 2 0 0.00


User Defined Bins for cp_pid

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
out 0 1 1
setup 0 1 1



Summary for Variable cp_rx

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 3 0 0.00


User Defined Bins for cp_rx

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
full 0 1 1
solo 0 1 1
empty 0 1 1



Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 54 54 0 0.00 54


Automatically Generated Cross Bins for cr_fifo_X_pid

Uncovered bins
cp_avsetupcp_avoutcp_rxcp_pidCOUNTAT LEASTNUMBERSTATUS
* * * * -- -- 54

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%