Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362	1			T2	2		T7	5		T15	8
all_pins[1]	362	1			T2	2		T7	5		T15	8
all_pins[2]	362	1			T2	2		T7	5		T15	8
all_pins[3]	362	1			T2	2		T7	5		T15	8
all_pins[4]	362	1			T2	2		T7	5		T15	8
all_pins[5]	362	1			T2	2		T7	5		T15	8
all_pins[6]	362	1			T2	2		T7	5		T15	8
all_pins[7]	362	1			T2	2		T7	5		T15	8
all_pins[8]	362	1			T2	2		T7	5		T15	8
all_pins[9]	362	1			T2	2		T7	5		T15	8
all_pins[10]	362	1			T2	2		T7	5		T15	8
all_pins[11]	362	1			T2	2		T7	5		T15	8
all_pins[12]	362	1			T2	2		T7	5		T15	8
all_pins[13]	362	1			T2	2		T7	5		T15	8
all_pins[14]	362	1			T2	2		T7	5		T15	8
all_pins[15]	362	1			T2	2		T7	5		T15	8
all_pins[16]	362	1			T2	2		T7	5		T15	8
all_pins[17]	362	1			T2	2		T7	5		T15	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10483	1			T2	64		T7	142		T15	222
values[0x1]	1101	1			T7	18		T15	34		T16	29
transitions[0x0=>0x1]	830	1			T7	13		T15	25		T16	21
transitions[0x1=>0x0]	830	1			T7	13		T15	25		T16	21

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	297	1			T2	2		T7	5		T15	7
all_pins[0]	values[0x1]	65	1			T15	1		T17	3		T42	1
all_pins[0]	transitions[0x0=>0x1]	51	1			T15	1		T17	3		T42	1
all_pins[0]	transitions[0x1=>0x0]	31	1			T15	2		T16	1		T17	1
all_pins[1]	values[0x0]	317	1			T2	2		T7	5		T15	6
all_pins[1]	values[0x1]	45	1			T15	2		T16	1		T17	1
all_pins[1]	transitions[0x0=>0x1]	28	1			T15	1		T17	1		T42	1
all_pins[1]	transitions[0x1=>0x0]	56	1			T7	2		T16	1		T17	1
all_pins[2]	values[0x0]	289	1			T2	2		T7	3		T15	7
all_pins[2]	values[0x1]	73	1			T7	2		T15	1		T16	2
all_pins[2]	transitions[0x0=>0x1]	48	1			T15	1		T16	1		T17	1
all_pins[2]	transitions[0x1=>0x0]	48	1			T7	2		T15	3		T17	3
all_pins[3]	values[0x0]	289	1			T2	2		T7	1		T15	5
all_pins[3]	values[0x1]	73	1			T7	4		T15	3		T16	1
all_pins[3]	transitions[0x0=>0x1]	52	1			T7	4		T15	2		T16	1
all_pins[3]	transitions[0x1=>0x0]	48	1			T15	1		T16	2		T42	3
all_pins[4]	values[0x0]	293	1			T2	2		T7	5		T15	6
all_pins[4]	values[0x1]	69	1			T15	2		T16	2		T17	2
all_pins[4]	transitions[0x0=>0x1]	55	1			T15	1		T17	1		T42	3
all_pins[4]	transitions[0x1=>0x0]	48	1			T7	3		T15	1		T16	1
all_pins[5]	values[0x0]	300	1			T2	2		T7	2		T15	6
all_pins[5]	values[0x1]	62	1			T7	3		T15	2		T16	3
all_pins[5]	transitions[0x0=>0x1]	48	1			T7	1		T15	2		T16	3
all_pins[5]	transitions[0x1=>0x0]	42	1			T15	2		T42	3		T43	1
all_pins[6]	values[0x0]	306	1			T2	2		T7	3		T15	6
all_pins[6]	values[0x1]	56	1			T7	2		T15	2		T17	1
all_pins[6]	transitions[0x0=>0x1]	45	1			T7	2		T15	1		T17	1
all_pins[6]	transitions[0x1=>0x0]	46	1			T16	3		T42	2		T43	2
all_pins[7]	values[0x0]	305	1			T2	2		T7	5		T15	7
all_pins[7]	values[0x1]	57	1			T15	1		T16	3		T42	4
all_pins[7]	transitions[0x0=>0x1]	44	1			T15	1		T16	3		T42	4
all_pins[7]	transitions[0x1=>0x0]	57	1			T7	2		T15	3		T16	1
all_pins[8]	values[0x0]	292	1			T2	2		T7	3		T15	5
all_pins[8]	values[0x1]	70	1			T7	2		T15	3		T16	1
all_pins[8]	transitions[0x0=>0x1]	49	1			T7	2		T15	3		T16	1
all_pins[8]	transitions[0x1=>0x0]	41	1			T16	1		T42	1		T43	2
all_pins[9]	values[0x0]	300	1			T2	2		T7	5		T15	8
all_pins[9]	values[0x1]	62	1			T16	1		T17	2		T42	2
all_pins[9]	transitions[0x0=>0x1]	50	1			T16	1		T17	2		T42	1
all_pins[9]	transitions[0x1=>0x0]	43	1			T7	1		T15	1		T16	2
all_pins[10]	values[0x0]	307	1			T2	2		T7	4		T15	7
all_pins[10]	values[0x1]	55	1			T7	1		T15	1		T16	2
all_pins[10]	transitions[0x0=>0x1]	39	1			T16	2		T17	1		T42	1
all_pins[10]	transitions[0x1=>0x0]	42	1			T17	1		T42	1		T59	2
all_pins[11]	values[0x0]	304	1			T2	2		T7	4		T15	7
all_pins[11]	values[0x1]	58	1			T7	1		T15	1		T17	1
all_pins[11]	transitions[0x0=>0x1]	43	1			T7	1		T15	1		T17	1
all_pins[11]	transitions[0x1=>0x0]	62	1			T15	5		T16	2		T17	1
all_pins[12]	values[0x0]	285	1			T2	2		T7	5		T15	3
all_pins[12]	values[0x1]	77	1			T15	5		T16	2		T17	1
all_pins[12]	transitions[0x0=>0x1]	50	1			T15	3		T16	2		T17	1
all_pins[12]	transitions[0x1=>0x0]	39	1			T15	1		T17	1		T42	1
all_pins[13]	values[0x0]	296	1			T2	2		T7	5		T15	5
all_pins[13]	values[0x1]	66	1			T15	3		T17	1		T42	2
all_pins[13]	transitions[0x0=>0x1]	54	1			T15	3		T17	1		T42	2
all_pins[13]	transitions[0x1=>0x0]	34	1			T7	1		T15	1		T16	3
all_pins[14]	values[0x0]	316	1			T2	2		T7	4		T15	7
all_pins[14]	values[0x1]	46	1			T7	1		T15	1		T16	3
all_pins[14]	transitions[0x0=>0x1]	26	1			T7	1		T15	1		T16	2
all_pins[14]	transitions[0x1=>0x0]	51	1			T7	2		T15	1		T16	1
all_pins[15]	values[0x0]	291	1			T2	2		T7	3		T15	7
all_pins[15]	values[0x1]	71	1			T7	2		T15	1		T16	2
all_pins[15]	transitions[0x0=>0x1]	60	1			T7	2		T17	4		T42	1
all_pins[15]	transitions[0x1=>0x0]	32	1			T15	2		T42	2		T59	2
all_pins[16]	values[0x0]	319	1			T2	2		T7	5		T15	5
all_pins[16]	values[0x1]	43	1			T15	3		T16	2		T42	2
all_pins[16]	transitions[0x0=>0x1]	35	1			T15	2		T16	1		T42	2
all_pins[16]	transitions[0x1=>0x0]	45	1			T15	1		T16	3		T17	2
all_pins[17]	values[0x0]	309	1			T2	2		T7	5		T15	6
all_pins[17]	values[0x1]	53	1			T15	2		T16	4		T17	2
all_pins[17]	transitions[0x0=>0x1]	53	1			T15	2		T16	4		T17	2