Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T7	4		T15	7		T16	7
all_values[1]	272	1			T7	4		T15	7		T16	7
all_values[2]	272	1			T7	4		T15	7		T16	7
all_values[3]	272	1			T7	4		T15	7		T16	7
all_values[4]	272	1			T7	4		T15	7		T16	7
all_values[5]	272	1			T7	4		T15	7		T16	7
all_values[6]	272	1			T7	4		T15	7		T16	7
all_values[7]	272	1			T7	4		T15	7		T16	7
all_values[8]	272	1			T7	4		T15	7		T16	7
all_values[9]	272	1			T7	4		T15	7		T16	7
all_values[10]	272	1			T7	4		T15	7		T16	7
all_values[11]	272	1			T7	4		T15	7		T16	7
all_values[12]	272	1			T7	4		T15	7		T16	7
all_values[13]	272	1			T7	4		T15	7		T16	7
all_values[14]	272	1			T7	4		T15	7		T16	7
all_values[15]	272	1			T7	4		T15	7		T16	7
all_values[16]	272	1			T7	4		T15	7		T16	7
all_values[17]	272	1			T7	4		T15	7		T16	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6474

1

T7

101

T15

171

T16

164

auto[1]

2230

1

T7

27

T15

53

T16

60

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5973

1

T7

88

T15

145

T16

157

auto[1]

2731

1

T7

40

T15

79

T16

67

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5194

1

T7

87

T15

122

T16

122

auto[1]

3510

1

T7

41

T15

102

T16

102

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	74	1			T7	3		T15	3		T16	3
all_values[0]	auto[0]	auto[1]	auto[0]	76	1			T15	1		T17	4		T42	1
all_values[0]	auto[1]	auto[0]	auto[1]	63	1			T7	1		T15	2		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	59	1			T15	1		T16	1		T17	3
all_values[1]	auto[0]	auto[0]	auto[0]	98	1			T7	3		T15	2		T16	3
all_values[1]	auto[0]	auto[1]	auto[0]	70	1			T15	1		T16	2		T17	2
all_values[1]	auto[1]	auto[0]	auto[1]	69	1			T7	1		T15	3		T16	1
all_values[1]	auto[1]	auto[1]	auto[1]	35	1			T15	1		T16	1		T42	1
all_values[2]	auto[0]	auto[0]	auto[0]	39	1			T7	2		T15	2		T16	3
all_values[2]	auto[0]	auto[0]	auto[1]	46	1			T15	3		T43	1		T58	2
all_values[2]	auto[0]	auto[1]	auto[0]	40	1			T17	6		T42	1		T59	2
all_values[2]	auto[0]	auto[1]	auto[1]	38	1			T7	1		T15	1		T16	2
all_values[2]	auto[1]	auto[0]	auto[1]	60	1			T15	1		T16	2		T17	1
all_values[2]	auto[1]	auto[1]	auto[1]	49	1			T7	1		T58	1		T54	2
all_values[3]	auto[0]	auto[0]	auto[0]	51	1			T15	2		T16	3		T43	3
all_values[3]	auto[0]	auto[0]	auto[1]	27	1			T17	2		T42	1		T59	1
all_values[3]	auto[0]	auto[1]	auto[0]	40	1			T42	1		T58	1		T59	1
all_values[3]	auto[0]	auto[1]	auto[1]	39	1			T7	2		T15	3		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	64	1			T15	1		T16	2		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	51	1			T7	2		T15	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	51	1			T7	2		T15	1		T16	2
all_values[4]	auto[0]	auto[0]	auto[1]	29	1			T15	1		T16	1		T17	1
all_values[4]	auto[0]	auto[1]	auto[0]	46	1			T7	1		T17	1		T42	2
all_values[4]	auto[0]	auto[1]	auto[1]	30	1			T15	1		T17	1		T42	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1			T7	1		T15	2		T16	3
all_values[4]	auto[1]	auto[1]	auto[1]	51	1			T15	2		T16	1		T17	4
all_values[5]	auto[0]	auto[0]	auto[0]	61	1			T7	1		T17	1		T42	1
all_values[5]	auto[0]	auto[0]	auto[1]	29	1			T15	2		T16	1		T17	1
all_values[5]	auto[0]	auto[1]	auto[0]	54	1			T15	1		T16	1		T42	1
all_values[5]	auto[0]	auto[1]	auto[1]	22	1			T7	1		T16	2		T59	2
all_values[5]	auto[1]	auto[0]	auto[1]	51	1			T15	2		T16	3		T17	3
all_values[5]	auto[1]	auto[1]	auto[1]	55	1			T7	2		T15	2		T17	2
all_values[6]	auto[0]	auto[0]	auto[0]	59	1			T16	2		T58	3		T55	5
all_values[6]	auto[0]	auto[0]	auto[1]	24	1			T15	1		T17	1		T59	1
all_values[6]	auto[0]	auto[1]	auto[0]	54	1			T7	1		T15	2		T16	4
all_values[6]	auto[0]	auto[1]	auto[1]	24	1			T7	2		T15	1		T42	2
all_values[6]	auto[1]	auto[0]	auto[1]	62	1			T7	1		T15	2		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	49	1			T15	1		T17	2		T42	2
all_values[7]	auto[0]	auto[0]	auto[0]	86	1			T7	3		T15	4		T16	1
all_values[7]	auto[0]	auto[1]	auto[0]	69	1			T7	1		T15	1		T16	3
all_values[7]	auto[1]	auto[0]	auto[1]	67	1			T15	1		T17	1		T58	2
all_values[7]	auto[1]	auto[1]	auto[1]	50	1			T15	1		T16	3		T17	1
all_values[8]	auto[0]	auto[0]	auto[0]	69	1			T15	1		T16	1		T17	1
all_values[8]	auto[0]	auto[1]	auto[0]	82	1			T7	2		T15	3		T16	5
all_values[8]	auto[1]	auto[0]	auto[1]	58	1			T17	1		T42	5		T43	1
all_values[8]	auto[1]	auto[1]	auto[1]	63	1			T7	2		T15	3		T16	1
all_values[9]	auto[0]	auto[0]	auto[0]	56	1			T7	1		T15	4		T16	1
all_values[9]	auto[0]	auto[0]	auto[1]	24	1			T7	1		T16	1		T17	2
all_values[9]	auto[0]	auto[1]	auto[0]	60	1			T7	1		T15	2		T16	1
all_values[9]	auto[0]	auto[1]	auto[1]	30	1			T16	1		T17	1		T43	1
all_values[9]	auto[1]	auto[0]	auto[1]	58	1			T7	1		T15	1		T16	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1			T16	1		T17	1		T42	2
all_values[10]	auto[0]	auto[0]	auto[0]	61	1			T15	2		T16	1		T17	3
all_values[10]	auto[0]	auto[0]	auto[1]	22	1			T7	3		T42	1		T58	1
all_values[10]	auto[0]	auto[1]	auto[0]	59	1			T15	3		T16	1		T17	1
all_values[10]	auto[0]	auto[1]	auto[1]	22	1			T16	1		T17	1		T42	1
all_values[10]	auto[1]	auto[0]	auto[1]	57	1			T15	1		T16	1		T17	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1			T7	1		T15	1		T16	3
all_values[11]	auto[0]	auto[0]	auto[0]	68	1			T7	3		T15	1		T16	5
all_values[11]	auto[0]	auto[0]	auto[1]	37	1			T15	1		T17	1		T42	2
all_values[11]	auto[0]	auto[1]	auto[0]	41	1			T15	2		T17	1		T58	1
all_values[11]	auto[0]	auto[1]	auto[1]	18	1			T42	1		T59	1		T55	1
all_values[11]	auto[1]	auto[0]	auto[1]	67	1			T15	3		T16	2		T17	2
all_values[11]	auto[1]	auto[1]	auto[1]	41	1			T7	1		T17	1		T42	1
all_values[12]	auto[0]	auto[0]	auto[0]	50	1			T7	1		T16	1		T17	1
all_values[12]	auto[0]	auto[0]	auto[1]	26	1			T7	1		T17	1		T42	1
all_values[12]	auto[0]	auto[1]	auto[0]	35	1			T7	1		T16	3		T17	2
all_values[12]	auto[0]	auto[1]	auto[1]	39	1			T15	3		T16	1		T43	1
all_values[12]	auto[1]	auto[0]	auto[1]	74	1			T7	1		T15	1		T42	4
all_values[12]	auto[1]	auto[1]	auto[1]	48	1			T15	3		T16	2		T17	3
all_values[13]	auto[0]	auto[0]	auto[0]	54	1			T16	2		T17	2		T59	3
all_values[13]	auto[0]	auto[0]	auto[1]	35	1			T7	3		T17	1		T42	1
all_values[13]	auto[0]	auto[1]	auto[0]	49	1			T16	3		T17	2		T42	2
all_values[13]	auto[0]	auto[1]	auto[1]	21	1			T15	1		T17	1		T58	1
all_values[13]	auto[1]	auto[0]	auto[1]	65	1			T7	1		T15	5		T16	1
all_values[13]	auto[1]	auto[1]	auto[1]	48	1			T15	1		T16	1		T42	3
all_values[14]	auto[0]	auto[0]	auto[0]	66	1			T15	1		T17	2		T42	1
all_values[14]	auto[0]	auto[0]	auto[1]	24	1			T7	1		T15	2		T17	2
all_values[14]	auto[0]	auto[1]	auto[0]	59	1			T16	2		T43	2		T58	1
all_values[14]	auto[0]	auto[1]	auto[1]	25	1			T15	1		T17	1		T59	1
all_values[14]	auto[1]	auto[0]	auto[1]	63	1			T7	2		T15	3		T16	2
all_values[14]	auto[1]	auto[1]	auto[1]	35	1			T7	1		T16	3		T17	1
all_values[15]	auto[0]	auto[0]	auto[0]	48	1			T7	1		T15	1		T16	2
all_values[15]	auto[0]	auto[0]	auto[1]	31	1			T15	1		T16	1		T42	1
all_values[15]	auto[0]	auto[1]	auto[0]	53	1			T7	1		T15	3		T16	1
all_values[15]	auto[0]	auto[1]	auto[1]	29	1			T7	1		T16	1		T17	2
all_values[15]	auto[1]	auto[0]	auto[1]	57	1			T15	2		T16	1		T17	1
all_values[15]	auto[1]	auto[1]	auto[1]	54	1			T7	1		T16	1		T17	2
all_values[16]	auto[0]	auto[0]	auto[0]	69	1			T7	1		T16	1		T17	5
all_values[16]	auto[0]	auto[0]	auto[1]	32	1			T7	1		T15	1		T16	2
all_values[16]	auto[0]	auto[1]	auto[0]	61	1			T15	2		T17	1		T42	3
all_values[16]	auto[0]	auto[1]	auto[1]	18	1			T15	1		T42	2		T59	1
all_values[16]	auto[1]	auto[0]	auto[1]	55	1			T7	2		T15	2		T16	2
all_values[16]	auto[1]	auto[1]	auto[1]	37	1			T15	1		T16	2		T17	1
all_values[17]	auto[0]	auto[0]	auto[0]	87	1			T7	2		T15	1		T16	1
all_values[17]	auto[0]	auto[1]	auto[0]	70	1			T7	1		T15	1		T16	1
all_values[17]	auto[1]	auto[0]	auto[1]	78	1			T7	1		T15	4		T16	2
all_values[17]	auto[1]	auto[1]	auto[1]	37	1			T15	1		T16	3		T17	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal