Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	10065093	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

10669502

1

T1

5

T2

10

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	20099921	1			T1	8		T2	8		T3	3
values[0x0]	316974	1			T1	5		T2	7		T3	3
values[0x1]	317700	1			T1	4		T2	4		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8004056	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

12730539

1

T1

10

T2

13

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	62990	1			T44	1		T40	12		T111	84
valid_sources[0x01]	63572	1			T44	1		T31	1		T35	1
valid_sources[0x02]	62562	1			T42	2		T43	1		T44	7
valid_sources[0x03]	66273	1			T44	6		T40	29		T58	2
valid_sources[0x04]	64331	1			T40	54		T111	74		T22	12
valid_sources[0x05]	136652	1			T45	2		T31	1		T40	32
valid_sources[0x06]	62968	1			T44	2		T31	1		T40	2
valid_sources[0x07]	63265	1			T44	1		T40	4		T53	1
valid_sources[0x08]	90964	1			T2	1		T44	3		T31	2
valid_sources[0x09]	72693	1			T2	1		T43	1		T44	5
valid_sources[0x0a]	64991	1			T44	2		T40	45		T321	2
valid_sources[0x0b]	163978	1			T44	1		T54	1		T55	1
valid_sources[0x0c]	203204	1			T44	9		T40	36		T55	1
valid_sources[0x0d]	63996	1			T44	4		T31	2		T40	61
valid_sources[0x0e]	71399	1			T43	1		T44	3		T31	1
valid_sources[0x0f]	142821	1			T31	1		T66	1		T35	1
valid_sources[0x10]	65772	1			T44	4		T40	79		T111	39
valid_sources[0x11]	99063	1			T44	2		T31	1		T33	3
valid_sources[0x12]	64124	1			T2	1		T3	1		T44	5
valid_sources[0x13]	74942	1			T44	1		T66	1		T40	22
valid_sources[0x14]	63070	1			T44	6		T31	2		T40	38
valid_sources[0x15]	68162	1			T44	1		T40	17		T54	1
valid_sources[0x16]	64193	1			T44	10		T58	5		T111	68
valid_sources[0x17]	65364	1			T44	4		T31	1		T40	29
valid_sources[0x18]	64084	1			T44	10		T31	1		T40	9
valid_sources[0x19]	101874	1			T43	3		T44	7		T35	1
valid_sources[0x1a]	64140	1			T44	11		T31	1		T40	3
valid_sources[0x1b]	65410	1			T44	4		T40	19		T111	57
valid_sources[0x1c]	62652	1			T44	2		T40	36		T77	2
valid_sources[0x1d]	62459	1			T44	7		T45	1		T40	27
valid_sources[0x1e]	62872	1			T44	4		T31	1		T52	4
valid_sources[0x1f]	64224	1			T44	10		T40	18		T55	1
valid_sources[0x20]	63720	1			T44	5		T31	1		T40	22
valid_sources[0x21]	88258	1			T44	1		T40	22		T75	2
valid_sources[0x22]	63689	1			T44	2		T46	1		T40	16
valid_sources[0x23]	66883	1			T41	1		T44	5		T45	1
valid_sources[0x24]	65924	1			T44	9		T31	1		T32	1
valid_sources[0x25]	65100	1			T1	1		T44	1		T31	4
valid_sources[0x26]	64054	1			T2	1		T43	3		T44	12
valid_sources[0x27]	77701	1			T44	3		T31	2		T40	34
valid_sources[0x28]	64320	1			T44	3		T31	2		T40	8
valid_sources[0x29]	64517	1			T44	6		T31	2		T66	2
valid_sources[0x2a]	63511	1			T44	3		T31	1		T40	10
valid_sources[0x2b]	139609	1			T31	1		T32	1		T40	28
valid_sources[0x2c]	79740	1			T44	6		T46	1		T40	8
valid_sources[0x2d]	65023	1			T44	5		T31	1		T40	30
valid_sources[0x2e]	66572	1			T44	1		T66	1		T40	26
valid_sources[0x2f]	65109	1			T44	4		T31	2		T52	3
valid_sources[0x30]	92463	1			T44	4		T40	18		T77	1
valid_sources[0x31]	65146	1			T2	2		T44	3		T40	35
valid_sources[0x32]	111835	1			T3	2		T44	1		T31	3
valid_sources[0x33]	63279	1			T44	9		T45	2		T31	1
valid_sources[0x34]	79853	1			T44	1		T40	32		T55	1
valid_sources[0x35]	64331	1			T44	5		T31	1		T33	6
valid_sources[0x36]	420296	1			T43	1		T44	4		T31	1
valid_sources[0x37]	63737	1			T2	1		T31	1		T90	28
valid_sources[0x38]	64202	1			T44	4		T31	1		T40	34
valid_sources[0x39]	64618	1			T92	1		T26	5		T111	74
valid_sources[0x3a]	64463	1			T43	1		T44	7		T66	1
valid_sources[0x3b]	89986	1			T44	11		T40	4		T111	58
valid_sources[0x3c]	154497	1			T44	7		T31	2		T40	69
valid_sources[0x3d]	85938	1			T1	1		T44	1		T40	50
valid_sources[0x3e]	111375	1			T44	7		T31	2		T40	4
valid_sources[0x3f]	100849	1			T44	7		T31	1		T40	30
valid_sources[0x40]	94215	1			T44	4		T45	1		T31	3
valid_sources[0x41]	63823	1			T44	1		T31	2		T40	45
valid_sources[0x42]	64339	1			T40	24		T77	1		T55	2
valid_sources[0x43]	82126	1			T2	1		T43	1		T44	4
valid_sources[0x44]	65545	1			T3	1		T44	1		T31	1
valid_sources[0x45]	64668	1			T44	5		T31	1		T39	12
valid_sources[0x46]	64799	1			T2	1		T44	4		T31	1
valid_sources[0x47]	64280	1			T44	3		T66	1		T40	4
valid_sources[0x48]	63186	1			T43	8		T40	23		T94	1
valid_sources[0x49]	240832	1			T44	8		T31	1		T40	26
valid_sources[0x4a]	92247	1			T29	12		T44	3		T40	14
valid_sources[0x4b]	64667	1			T44	12		T40	7		T54	1
valid_sources[0x4c]	63904	1			T1	1		T44	4		T45	1
valid_sources[0x4d]	62632	1			T44	2		T31	1		T33	2
valid_sources[0x4e]	119833	1			T44	3		T45	4		T31	1
valid_sources[0x4f]	85731	1			T44	1		T31	4		T40	26
valid_sources[0x50]	64407	1			T44	3		T40	24		T111	70
valid_sources[0x51]	63552	1			T41	1		T44	3		T31	3
valid_sources[0x52]	70351	1			T1	1		T2	1		T44	2
valid_sources[0x53]	64345	1			T44	13		T31	1		T40	49
valid_sources[0x54]	64994	1			T44	6		T45	1		T31	1
valid_sources[0x55]	99774	1			T42	2		T44	4		T31	1
valid_sources[0x56]	63948	1			T44	6		T31	2		T40	34
valid_sources[0x57]	79004	1			T44	12		T31	1		T40	8
valid_sources[0x58]	78620	1			T44	2		T40	47		T92	1
valid_sources[0x59]	77254	1			T44	1		T31	3		T40	33
valid_sources[0x5a]	183919	1			T40	29		T55	1		T505	2
valid_sources[0x5b]	64983	1			T44	3		T52	2		T40	26
valid_sources[0x5c]	63291	1			T44	11		T40	20		T77	1
valid_sources[0x5d]	64885	1			T44	10		T46	1		T40	7
valid_sources[0x5e]	63033	1			T44	1		T31	1		T40	3
valid_sources[0x5f]	64190	1			T44	4		T40	40		T111	47
valid_sources[0x60]	64781	1			T44	1		T45	1		T31	1
valid_sources[0x61]	64271	1			T2	1		T41	1		T44	3
valid_sources[0x62]	68143	1			T44	1		T31	3		T40	33
valid_sources[0x63]	65350	1			T44	2		T92	1		T111	63
valid_sources[0x64]	63067	1			T3	1		T44	4		T31	2
valid_sources[0x65]	75154	1			T44	6		T45	2		T33	3
valid_sources[0x66]	165639	1			T44	8		T31	2		T40	24
valid_sources[0x67]	91113	1			T43	1		T44	2		T31	1
valid_sources[0x68]	64087	1			T43	7		T44	1		T31	1
valid_sources[0x69]	63930	1			T44	2		T31	2		T93	3
valid_sources[0x6a]	64996	1			T44	9		T45	2		T40	61
valid_sources[0x6b]	62471	1			T44	3		T40	6		T89	2
valid_sources[0x6c]	63817	1			T44	4		T46	2		T111	54
valid_sources[0x6d]	79623	1			T44	2		T31	1		T40	3
valid_sources[0x6e]	89145	1			T44	7		T31	2		T40	5
valid_sources[0x6f]	74179	1			T44	4		T31	1		T40	13
valid_sources[0x70]	64163	1			T1	2		T44	3		T45	1
valid_sources[0x71]	98246	1			T44	4		T40	16		T111	79
valid_sources[0x72]	118562	1			T31	1		T89	4		T320	2
valid_sources[0x73]	65218	1			T1	2		T44	9		T35	1
valid_sources[0x74]	65084	1			T31	1		T40	2		T53	1
valid_sources[0x75]	139029	1			T43	4		T44	9		T31	2
valid_sources[0x76]	65266	1			T44	7		T31	3		T40	91
valid_sources[0x77]	64178	1			T44	4		T45	1		T31	1
valid_sources[0x78]	65038	1			T44	3		T31	1		T40	37
valid_sources[0x79]	73585	1			T31	1		T38	58		T40	37
valid_sources[0x7a]	64299	1			T30	159		T44	3		T31	2
valid_sources[0x7b]	63667	1			T2	1		T44	4		T45	3
valid_sources[0x7c]	63903	1			T43	2		T44	2		T40	75
valid_sources[0x7d]	63506	1			T44	7		T31	1		T40	19
valid_sources[0x7e]	96107	1			T44	2		T31	3		T40	21
valid_sources[0x7f]	77992	1			T44	4		T31	1		T40	19
valid_sources[0x80]	66402	1			T44	2		T46	5		T40	32

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

10156270

1

T2

4

T29

2

T41

1

values[0x0]

all_enables

biggest_size

265316

1

T1

4

T2

4

T3

3

values[0x1]

all_enables

biggest_size

247916

1

T1

1

T2

2

T3

3