Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

10078949

1

T1

12

T2

9

T3

6

full_word

10670463

1

T1

5

T2

10

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	20749102	1			T1	17		T2	19		T3	12
auto[TlIntgErrCmd]	108	1			T224	7		T243	2		T249	7
auto[TlIntgErrData]	98	1			T224	5		T243	2		T249	7
auto[TlIntgErrBoth]	104	1			T224	8		T243	6		T249	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20101735

1

T1

8

T2

8

T3

3

auto[1]

647677

1

T1

9

T2

11

T3

9

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	9945154	1			T1	8		T2	4		T3	3
auto[TlIntgErrNone]	partial	auto[1]	133508	1			T1	4		T2	5		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	10156440	1			T2	4		T29	2		T41	1
auto[TlIntgErrNone]	full_word	auto[1]	514000	1			T1	5		T2	6		T3	6
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T224	4		T243	1		T249	2
auto[TlIntgErrCmd]	partial	auto[1]	55	1			T224	2		T243	1		T249	5
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T494	1		T501	1		T499	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T224	1		T295	1		T494	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T224	2		T497	1		T498	2
auto[TlIntgErrData]	partial	auto[1]	44	1			T224	3		T243	1		T249	6
auto[TlIntgErrData]	full_word	auto[0]	1	1			T502	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T243	1		T249	1		T499	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1			T224	2		T243	4		T498	2
auto[TlIntgErrBoth]	partial	auto[1]	58	1			T224	6		T243	2		T249	6
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T503	2		T496	1		T504	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T295	1		T494	2		T500	1