Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	579465855	10803	0	0
ep_in_enable_rd_A	579465855	3114	0	0
ep_out_enable_rd_A	579465855	2975	0	0
in_iso_rd_A	579465855	3087	0	0
intr_enable_rd_A	579465855	4037	0	0
out_iso_rd_A	579465855	2771	0	0
phy_config_rd_A	579465855	1764	0	0
phy_pins_drive_rd_A	579465855	2130	0	0
rxenable_setup_rd_A	579465855	2555	0	0
set_nak_out_rd_A	579465855	3082	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	10803	0	0
T223	7423	227	0	0
T224	60826	7	0	0
T225	4494	13	0	0
T242	3659	377	0	0
T243	34807	3	0	0
T249	28132	4	0	0
T250	4741	906	0	0
T254	4724	472	0	0
T259	9713	17	0	0
T266	3761	10	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	3114	0	0
T225	4494	50	0	0
T230	5274	7	0	0
T264	3124	46	0	0
T277	5163	23	0	0
T281	9461	82	0	0
T282	75286	266	0	0
T286	6016	42	0	0
T287	5379	8	0	0
T293	2552	2	0	0
T294	10936	75	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	2975	0	0
T225	4494	54	0	0
T230	5274	7	0	0
T264	3124	40	0	0
T277	5163	49	0	0
T281	9461	64	0	0
T282	75286	271	0	0
T286	6016	9	0	0
T287	5379	30	0	0
T293	2552	27	0	0
T294	10936	61	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	3087	0	0
T225	4494	14	0	0
T230	5274	6	0	0
T264	3124	60	0	0
T277	5163	49	0	0
T281	9461	104	0	0
T282	75286	295	0	0
T286	6016	17	0	0
T287	5379	49	0	0
T293	2552	30	0	0
T294	10936	102	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	4037	0	0
T225	4494	5	0	0
T230	5274	2	0	0
T277	5163	46	0	0
T281	9461	93	0	0
T282	75286	265	0	0
T286	6016	6	0	0
T287	5379	53	0	0
T293	2552	37	0	0
T294	10936	11	0	0
T295	33546	155	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	2771	0	0
T225	4494	47	0	0
T230	5274	2	0	0
T264	3124	26	0	0
T277	5163	34	0	0
T281	9461	86	0	0
T282	75286	326	0	0
T286	6016	13	0	0
T294	10936	57	0	0
T295	33546	158	0	0
T296	64240	115	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	1764	0	0
T225	4494	5	0	0
T230	5274	8	0	0
T264	3124	6	0	0
T277	5163	19	0	0
T281	9461	86	0	0
T282	75286	256	0	0
T286	6016	31	0	0
T287	5379	1	0	0
T293	2552	1	0	0
T294	10936	48	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	2130	0	0
T225	4494	5	0	0
T230	5274	1	0	0
T264	3124	41	0	0
T277	5163	49	0	0
T281	9461	73	0	0
T282	75286	292	0	0
T286	6016	12	0	0
T287	5379	20	0	0
T293	2552	20	0	0
T294	10936	47	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	2555	0	0
T225	4494	5	0	0
T230	5274	3	0	0
T264	3124	3	0	0
T277	5163	47	0	0
T281	9461	96	0	0
T282	75286	234	0	0
T286	6016	9	0	0
T287	5379	17	0	0
T293	2552	20	0	0
T294	10936	20	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579465855	3082	0	0
T225	4494	42	0	0
T230	5274	4	0	0
T264	3124	9	0	0
T277	5163	24	0	0
T281	9461	75	0	0
T282	75286	247	0	0
T286	6016	28	0	0
T287	5379	43	0	0
T294	10936	99	0	0
T295	33546	123	0	0