Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.35 100.00 69.42 100.00 100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_avsetupfifo 95.45 100.00 81.82 100.00 100.00
tb.dut.usbdev_avoutfifo 97.73 100.00 90.91 100.00 100.00
tb.dut.usbdev_rxfifo 97.92 100.00 91.67 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo 100.00 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo 100.00 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
95.45 100.00
tb.dut.usbdev_avsetupfifo

SCORELINE
97.73 100.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T3 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T3 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
97.92 100.00
tb.dut.usbdev_rxfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T1 T2 T30 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T1 T2 T30 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300


43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;
Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T30 T43 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T30 T43 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T30 T43 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T30 T31 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T30 T31 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T2 T30 T31 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 
Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00


68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T2 T30 T31 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T2 T30 T31 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T30,T31
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T30,T31 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T30,T31 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT2,T30,T31 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T30,T31
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT31,T89,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T30,T31 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT2,T30,T31 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT31,T46,T90
110Not Covered
111CoveredT2,T30,T31 

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T30,T31 

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT2,T30,T31 

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT31,T89,T18
10CoveredT2,T30,T31
11CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT2,T30,T31
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
95.45 81.82
tb.dut.usbdev_avsetupfifo

SCORECOND
97.73 90.91
tb.dut.usbdev_avoutfifo

TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT44,T66,T58
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT66,T23,T67
110Not Covered
111CoveredT1,T2,T3 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T30
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
97.92 91.67
tb.dut.usbdev_rxfifo

SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT2,T30,T43
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T30 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T30 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T30
110Not Covered
111CoveredT2,T30,T43 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T30
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
95.45 100.00
tb.dut.usbdev_avsetupfifo

SCOREBRANCH
97.73 100.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00 



130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>

Branches:
-1-StatusTests
1 Covered T2,T30,T31
0 Covered T1,T2,T3 



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T30,T31 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T2,T30,T31
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.92 100.00
tb.dut.usbdev_rxfifo

SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00 



138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T30 



69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T30
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 560901816 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 461264882 0 0
gen_passthru_fifo.paramCheckPass 22368 22368 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 560901816 0 0
T1 46584 733 0 0
T2 98670 618 0 0
T3 74448 1400 0 0
T29 96030 48 0 0
T30 330990 11649 0 0
T31 264534 17924 0 0
T32 6443 0 0 0
T33 9829 1140 0 0
T34 10095 0 0 0
T35 6682 0 0 0
T36 10551 0 0 0
T41 18260 28 0 0
T42 84051 959 0 0
T43 277656 33597 0 0
T44 99816 9235 0 0
T45 303708 23115 0 0
T46 0 55 0 0
T53 0 577 0 0
T54 0 579 0 0
T55 0 573 0 0
T66 7685 0 0 0
T89 0 240 0 0
T90 0 80 0 0
T91 0 587 0 0
T92 0 30 0 0
T93 0 557 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 93168 92388 0 0
T2 107640 106728 0 0
T3 81216 80112 0 0
T29 104760 103656 0 0
T30 361080 360336 0 0
T41 19920 18852 0 0
T42 91692 90780 0 0
T43 277656 276792 0 0
T44 99816 99048 0 0
T45 303708 302820 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 93168 92388 0 0
T2 107640 106728 0 0
T3 81216 80112 0 0
T29 104760 103656 0 0
T30 361080 360336 0 0
T41 19920 18852 0 0
T42 91692 90780 0 0
T43 277656 276792 0 0
T44 99816 99048 0 0
T45 303708 302820 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 93168 92388 0 0
T2 107640 106728 0 0
T3 81216 80112 0 0
T29 104760 103656 0 0
T30 361080 360336 0 0
T41 19920 18852 0 0
T42 91692 90780 0 0
T43 277656 276792 0 0
T44 99816 99048 0 0
T45 303708 302820 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 461264882 0 0
T1 15528 665 0 0
T2 44850 542 0 0
T3 33840 1352 0 0
T29 43650 0 0 0
T30 150450 11013 0 0
T31 176356 17375 0 0
T32 6443 0 0 0
T33 9829 1126 0 0
T34 10095 0 0 0
T35 6682 0 0 0
T36 10551 0 0 0
T41 8300 0 0 0
T42 38205 915 0 0
T43 138828 33325 0 0
T44 49908 5163 0 0
T45 151854 22935 0 0
T46 0 33 0 0
T53 0 577 0 0
T54 0 579 0 0
T55 0 573 0 0
T58 0 5843 0 0
T66 7685 0 0 0
T81 0 3078 0 0
T89 0 155 0 0
T90 0 48 0 0
T91 0 587 0 0
T92 0 18 0 0
T93 0 557 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 22368 22368 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T29 6 6 0 0
T30 6 6 0 0
T41 6 6 0 0
T42 6 6 0 0
T43 6 6 0 0
T44 6 6 0 0
T45 6 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%