Unified Coverage Report :: Module :: usbdev_counter

Module : usbdev_counter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
59.28	81.58	36.67			59.60

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_counter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_ctr_out	54.65	78.95	25.00			60.00
tb.dut.u_ctr_in	54.65	78.95	25.00			60.00
tb.dut.u_ctr_errors	65.57	84.21	50.00			62.50
tb.dut.u_ctr_nodata_in	66.96	84.21	50.00			66.67

---

Module Instance : tb.dut.u_ctr_out

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.65	78.95	25.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_errors

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	84.21	50.00			62.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
65.57	84.21	50.00			62.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ctr_nodata_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.96	84.21	50.00			66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.96	84.21	50.00			66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.83	97.53	92.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
54.65	78.95

tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
65.57	84.21

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         2/2                if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58                          assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
59                        end else begin : gen_single
60                          logic unused_ep;
61         unreachable      assign unused_ep = ^ep_i;  // Endpoint number not required
62         1/1              assign ep_enabled = endpoints[0];
           Tests:       T1 T2 T3 
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=3,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
54.65	78.95

tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Line Coverage for Module self-instances :

SCORE	LINE
66.96	84.21

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         2/2                if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Cond Coverage for Module self-instances :

SCORE	COND
54.65	25.00

tb.dut.u_ctr_out

SCORE	COND
54.65	25.00

tb.dut.u_ctr_in

SCORE	COND
66.96	50.00

tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	5	2	40.00
Logical	5	2	40.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

---

Cond Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
65.57	50.00

tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	3	1	33.33
Logical	3	1	33.33
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=12,NEvents=4,Width=8,EpW=4 + NEndpoints=12,NEvents=3,Width=8,EpW=4 + NEndpoints=12,NEvents=1,Width=8,EpW=4 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
54.65	60.00

tb.dut.u_ctr_out

SCORE	BRANCH
54.65	60.00

tb.dut.u_ctr_in

SCORE	BRANCH
66.96	66.67

tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		11	7	63.64
TERNARY	58	2	1	50.00
IF	45	5	4	80.00
IF	70	4	2	50.00

58             assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==>
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

---

Branch Coverage for Module : usbdev_counter ( parameter NEndpoints=1,NEvents=4,Width=8,EpW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
65.57	62.50

tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		9	5	55.56
IF	45	5	3	60.00
IF	70	4	2	50.00

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==>
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Not Covered
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_ctr_out

	Total	Covered	Percent
Conditions	4	1	25.00
Logical	4	1	25.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_out

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	58	1	1	100.00
IF	45	5	3	60.00
IF	70	4	2	50.00

58             assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
                                                             -1-  
                                                             ==>  
                                                             ==> (Excluded)  

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==>
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
TOTAL		19	15	78.95
ALWAYS	45	7	5	71.43
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_ctr_in

	Total	Covered	Percent
Conditions	4	1	25.00
Logical	4	1	25.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_in

	Line No.	Total	Covered	Percent
Branches		10	6	60.00
TERNARY	58	1	1	100.00
IF	45	5	3	60.00
IF	70	4	2	50.00

58             assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
                                                             -1-  
                                                             ==>  
                                                             ==> (Excluded)  

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==>
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	61	0	0
CONT_ASSIGN	62	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         2/2                if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
51         1/2     ==>        if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58                          assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
59                        end else begin : gen_single
60                          logic unused_ep;
61         unreachable      assign unused_ep = ^ep_i;  // Endpoint number not required
62         1/1              assign ep_enabled = endpoints[0];
           Tests:       T1 T2 T3 
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_ctr_errors

	Total	Covered	Percent
Conditions	2	1	50.00
Logical	2	1	50.00
Non-Logical	0	0
Event	0	0

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_errors

	Line No.	Total	Covered	Percent
Branches		8	5	62.50
IF	45	4	3	75.00
IF	70	4	2	50.00

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	-	Excluded		VC_COV_UNR
0	-	1	Not Covered
0	-	0	Covered	T1,T2,T3

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3

Line Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
TOTAL		19	16	84.21
ALWAYS	45	7	6	85.71
CONT_ASSIGN	58	1	1	100.00
ALWAYS	70	8	6	75.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	86	1	1	100.00

44                        always_ff @(posedge clk_i or negedge rst_ni) begin
45         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
46         1/1                endpoints  <= NEndpoints'(0);
           Tests:       T1 T2 T3 
47         1/1                ev_enables <= NEvents'(0);
           Tests:       T1 T2 T3 
48                          end else begin
49                            // Software writes to set the current enables.
50         1/2     ==>        if (endp_qe_i) endpoints  <= endpoints_i;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
51         2/2                if (ev_qe_i)   ev_enables <= ev_i;
           Tests:       T1 T2 T3  | T1 T2 T3 
                   ==>  MISSING_ELSE
52                          end
53                        end
54                      
55                        // Respond to events on this endpoint?
56                        logic ep_enabled;
57                        if (NEndpoints > 1) begin : gen_multi
58         1/1              assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
           Tests:       T1 T2 T3 
59                        end else begin : gen_single
60                          logic unused_ep;
61                          assign unused_ep = ^ep_i;  // Endpoint number not required
62                          assign ep_enabled = endpoints[0];
63                        end
64                      
65                        // Saturating event counter.
66                        logic [Width-1:0] count;
67                        logic [NEvents-1:0] event_q;
68                      
69                        always_ff @(posedge clk_i or negedge rst_ni) begin
70         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
71         1/1                count   <= Width'(0);
           Tests:       T1 T2 T3 
72         1/1                event_q <= NEvents'(0);
           Tests:       T1 T2 T3 
73         1/1              end else if (reset_i) begin
           Tests:       T1 T2 T3 
74         0/1     ==>        count   <= Width'(0);
75                            // Do not modify 'event_q' here because the event inputs may still be asserted.
76                          end else begin
77                            // Positive-edge triggered, saturating count of events.
78         1/2     ==>        if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
           Tests:       T1 T2 T3 
                        MISSING_ELSE
79                            // Retain previous state of event input signals.
80         1/1                event_q <= event_i;
           Tests:       T1 T2 T3 
81                          end
82                        end
83                      
84         1/1            assign ev_o = ev_enables;
           Tests:       T1 T2 T3 
85         1/1            assign endpoints_o = endpoints;
           Tests:       T1 T2 T3 
86         1/1            assign count_o = count;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_ctr_nodata_in

	Total	Covered	Percent
Conditions	4	2	50.00
Logical	4	2	50.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((ep_i < 4'(NEndpoints)) ? endpoints[ep_i] : 1'b0)
             -----------1-----------

-1-	Status	Tests	Exclude Annotation
0	Excluded		VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       78
 EXPRESSION (((|((ev_enables & event_i) & (~event_q)))) & ep_enabled)
             ---------------------1--------------------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T4,T5,T6
1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_ctr_nodata_in

	Line No.	Total	Covered	Percent
Branches		9	6	66.67
TERNARY	58	1	1	100.00
IF	45	4	3	75.00
IF	70	4	2	50.00

58             assign ep_enabled = (ep_i < EpW'(NEndpoints)) ? endpoints[ep_i] : 1'b0;
                                                             -1-  
                                                             ==>  
                                                             ==> (Excluded)  

Branches:

-1-	Status	Tests	Exclude Annotation
1	Covered	T1,T2,T3
0	Excluded		VC_COV_UNR

45             if (!rst_ni) begin
               -1-  
46               endpoints  <= NEndpoints'(0);
                 ==>
47               ev_enables <= NEvents'(0);
48             end else begin
49               // Software writes to set the current enables.
50               if (endp_qe_i) endpoints  <= endpoints_i;
                 -2-  
                 ==>
                 MISSING_ELSE
                 ==>
51               if (ev_qe_i)   ev_enables <= ev_i;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	Status	Tests	Exclude Annotation
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	-	Covered	T1,T2,T3
0	-	1	Covered	T1,T2,T3
0	-	0	Excluded		VC_COV_UNR

70             if (!rst_ni) begin
               -1-  
71               count   <= Width'(0);
                 ==>
72               event_q <= NEvents'(0);
73             end else if (reset_i) begin
                        -2-  
74               count   <= Width'(0);
                 ==>
75               // Do not modify 'event_q' here because the event inputs may still be asserted.
76             end else begin
77               // Positive-edge triggered, saturating count of events.
78               if (|(ev_enables & event_i & ~event_q) & ep_enabled) count <= count + ~&count;
                 -3-  
                 ==>
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Covered	T1,T2,T3