Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	90040	1			T1	4		T2	7		T3	3
all_values[1]	90040	1			T1	4		T2	7		T3	3
all_values[2]	90040	1			T1	4		T2	7		T3	3
all_values[3]	90040	1			T1	4		T2	7		T3	3
all_values[4]	90040	1			T1	4		T2	7		T3	3
all_values[5]	90040	1			T1	4		T2	7		T3	3
all_values[6]	90040	1			T1	4		T2	7		T3	3
all_values[7]	90040	1			T1	4		T2	7		T3	3
all_values[8]	90040	1			T1	4		T2	7		T3	3
all_values[9]	90040	1			T1	4		T2	7		T3	3
all_values[10]	90040	1			T1	4		T2	7		T3	3
all_values[11]	90040	1			T1	4		T2	7		T3	3
all_values[12]	90040	1			T1	4		T2	7		T3	3
all_values[13]	90040	1			T1	4		T2	7		T3	3
all_values[14]	90040	1			T1	4		T2	7		T3	3
all_values[15]	90040	1			T1	4		T2	7		T3	3
all_values[16]	90040	1			T1	4		T2	7		T3	3
all_values[17]	90040	1			T1	4		T2	7		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2871361

1

T1

128

T2

219

T3

94

auto[1]

9919

1

T2

5

T3

2

T28

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410468

1

T1

110

T2

210

T3

85

auto[1]

470812

1

T1

18

T2

14

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	62539	1			T1	3		T2	7		T3	3
all_values[0]	auto[0]	auto[1]	24150	1			T1	1		T28	2		T32	1
all_values[0]	auto[1]	auto[0]	3243	1			T49	3		T50	3		T51	3
all_values[0]	auto[1]	auto[1]	108	1			T362	1		T363	1		T364	1
all_values[1]	auto[0]	auto[0]	85527	1			T1	4		T2	7		T3	3
all_values[1]	auto[0]	auto[1]	3056	1			T29	2		T30	2		T36	1
all_values[1]	auto[1]	auto[0]	559	1			T31	2		T35	2		T7	1
all_values[1]	auto[1]	auto[1]	898	1			T31	12		T35	1		T7	1
all_values[2]	auto[0]	auto[0]	4248	1			T1	1		T2	6		T3	1
all_values[2]	auto[0]	auto[1]	85545	1			T1	3		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	137	1			T40	1		T66	1		T67	1
all_values[2]	auto[1]	auto[1]	110	1			T40	1		T66	1		T67	1
all_values[3]	auto[0]	auto[0]	88102	1			T1	4		T2	7		T3	3
all_values[3]	auto[0]	auto[1]	283	1			T19	1		T68	1		T69	1
all_values[3]	auto[1]	auto[0]	1582	1			T19	1484		T258	2		T259	1
all_values[3]	auto[1]	auto[1]	73	1			T19	1		T258	2		T259	4
all_values[4]	auto[0]	auto[0]	4226	1			T1	1		T2	6		T3	1
all_values[4]	auto[0]	auto[1]	85655	1			T1	3		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	102	1			T48	1		T258	1		T259	6
all_values[4]	auto[1]	auto[1]	57	1			T48	1		T262	1		T258	1
all_values[5]	auto[0]	auto[0]	89502	1			T1	4		T2	7		T3	3
all_values[5]	auto[0]	auto[1]	343	1			T7	1		T22	1		T8	1
all_values[5]	auto[1]	auto[0]	129	1			T262	1		T258	1		T259	3
all_values[5]	auto[1]	auto[1]	66	1			T262	2		T258	1		T259	2
all_values[6]	auto[0]	auto[0]	89587	1			T1	4		T2	7		T3	3
all_values[6]	auto[0]	auto[1]	218	1			T7	1		T9	1		T97	1
all_values[6]	auto[1]	auto[0]	120	1			T262	1		T259	2		T327	3
all_values[6]	auto[1]	auto[1]	115	1			T70	1		T71	1		T72	1
all_values[7]	auto[0]	auto[0]	35582	1			T3	3		T40	2		T42	2
all_values[7]	auto[0]	auto[1]	54288	1			T1	4		T2	7		T28	5
all_values[7]	auto[1]	auto[0]	111	1			T52	1		T53	1		T54	1
all_values[7]	auto[1]	auto[1]	59	1			T52	1		T53	1		T54	1
all_values[8]	auto[0]	auto[0]	89299	1			T1	4		T2	7		T3	3
all_values[8]	auto[0]	auto[1]	53	1			T262	1		T259	1		T260	1
all_values[8]	auto[1]	auto[0]	592	1			T58	10		T56	10		T59	10
all_values[8]	auto[1]	auto[1]	96	1			T56	1		T59	1		T61	1
all_values[9]	auto[0]	auto[0]	89795	1			T1	4		T2	2		T3	3
all_values[9]	auto[0]	auto[1]	59	1			T262	1		T260	3		T352	6
all_values[9]	auto[1]	auto[0]	112	1			T2	3		T64	3		T65	3
all_values[9]	auto[1]	auto[1]	74	1			T2	2		T64	2		T65	2
all_values[10]	auto[0]	auto[0]	89475	1			T1	4		T2	7		T3	3
all_values[10]	auto[0]	auto[1]	397	1			T30	1		T33	1		T37	2
all_values[10]	auto[1]	auto[0]	93	1			T262	2		T258	1		T352	4
all_values[10]	auto[1]	auto[1]	75	1			T262	3		T258	3		T259	1
all_values[11]	auto[0]	auto[0]	89039	1			T1	4		T2	7		T3	2
all_values[11]	auto[0]	auto[1]	735	1			T3	1		T32	4		T38	4
all_values[11]	auto[1]	auto[0]	157	1			T75	1		T76	1		T77	1
all_values[11]	auto[1]	auto[1]	109	1			T75	1		T76	1		T77	1
all_values[12]	auto[0]	auto[0]	89619	1			T1	4		T2	7		T3	3
all_values[12]	auto[0]	auto[1]	252	1			T79	1		T82	1		T83	1
all_values[12]	auto[1]	auto[0]	91	1			T78	2		T80	2		T81	2
all_values[12]	auto[1]	auto[1]	78	1			T78	1		T80	1		T81	1
all_values[13]	auto[0]	auto[0]	89703	1			T1	4		T2	7		T3	1
all_values[13]	auto[0]	auto[1]	66	1			T79	1		T82	1		T83	1
all_values[13]	auto[1]	auto[0]	159	1			T3	1		T84	1		T85	1
all_values[13]	auto[1]	auto[1]	112	1			T3	1		T84	1		T85	1
all_values[14]	auto[0]	auto[0]	18195	1			T1	4		T2	7		T3	3
all_values[14]	auto[0]	auto[1]	71687	1			T40	1		T7	2		T19	1486
all_values[14]	auto[1]	auto[0]	88	1			T258	4		T259	1		T260	2
all_values[14]	auto[1]	auto[1]	70	1			T260	3		T352	2		T327	4
all_values[15]	auto[0]	auto[0]	4260	1			T1	1		T2	6		T3	1
all_values[15]	auto[0]	auto[1]	85591	1			T1	3		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	117	1			T262	3		T259	3		T260	2
all_values[15]	auto[1]	auto[1]	72	1			T258	1		T259	2		T260	5
all_values[16]	auto[0]	auto[0]	89085	1			T1	4		T2	7		T3	3
all_values[16]	auto[0]	auto[1]	774	1			T30	1		T24	1		T74	1
all_values[16]	auto[1]	auto[0]	105	1			T32	4		T38	4		T73	4
all_values[16]	auto[1]	auto[1]	76	1			T32	4		T38	4		T73	4
all_values[17]	auto[0]	auto[0]	34515	1			T2	5		T42	2		T63	2
all_values[17]	auto[0]	auto[1]	55351	1			T1	4		T2	2		T3	3
all_values[17]	auto[1]	auto[0]	113	1			T28	1		T62	1		T262	3
all_values[17]	auto[1]	auto[1]	61	1			T28	1		T62	1		T258	1