Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1927	1			T28	1		T68	1		T107	6
range_16_to_126	149194	1			T1	1		T3	1		T29	5
fifteen	413	1			T68	1		T107	7		T115	3
range_2_to_14	18231	1			T42	2		T86	2		T36	2
seven	440	1			T228	1		T107	9		T115	5
one	867	1			T68	1		T333	1		T107	5
zero	731	1			T75	1		T160	5		T84	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

12222

1

T1

1

T3

1

T30

1

three

14311

1

T30

2

T86

1

T31

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	45	1			T165	11		T189	1		T515	17
range_127	three	46	1			T68	1		T115	1		T165	11
range_16_to_126	seven	10902	1			T1	1		T3	1		T30	1
range_16_to_126	three	12819	1			T30	2		T31	2		T35	2
fifteen	seven	39	1			T107	1		T116	1		T189	1
fifteen	three	27	1			T116	1		T516	1		T517	2
range_2_to_14	seven	1045	1			T107	4		T518	2		T115	5
range_2_to_14	three	1327	1			T86	1		T8	2		T107	4
seven	seven	31	1			T107	1		T425	2		T519	1
seven	three	13	1			T425	1		T426	1		T520	1
one	seven	105	1			T107	1		T292	1		T189	1
one	three	42	1			T223	2		T446	1		T342	4
zero	seven	86	1			T425	1		T224	2		T521	1
zero	three	50	1			T189	1		T436	1		T425	1