Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105566

1

T1

1

T3

1

T28

1

auto[1]

45286

1

T29

2

T30

9

T31

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	28518	1			T30	3		T37	2		T17	2
max_len_m1	840	1			T30	1		T32	1		T19	3
max_len_m2	851	1			T31	2		T19	2		T4	1
max_len_m3	835	1			T30	1		T19	1		T73	1
five	1231	1			T19	3		T4	3		T5	4
four	1164	1			T31	2		T19	1		T73	1
three	783	1			T38	1		T19	2		T74	1
one	824	1			T19	2		T4	2		T68	1
zero	12032	1			T3	1		T29	3		T30	6

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23129	1			T30	2		T37	1		T17	1
max_len	auto[1]	5389	1			T30	1		T37	1		T17	1
max_len_m1	auto[0]	560	1			T30	1		T32	1		T19	3
max_len_m1	auto[1]	280	1			T5	1		T6	2		T275	2
max_len_m2	auto[0]	581	1			T31	1		T19	2		T4	1
max_len_m2	auto[1]	270	1			T31	1		T5	1		T157	1
max_len_m3	auto[0]	563	1			T30	1		T19	1		T73	1
max_len_m3	auto[1]	272	1			T4	2		T6	1		T169	2
five	auto[0]	650	1			T19	3		T4	3		T5	2
five	auto[1]	581	1			T5	2		T6	1		T68	1
four	auto[0]	585	1			T31	1		T19	1		T73	1
four	auto[1]	579	1			T31	1		T50	1		T157	1
three	auto[0]	397	1			T38	1		T19	2		T74	1
three	auto[1]	386	1			T158	1		T280	12		T287	5
one	auto[0]	387	1			T19	2		T4	2		T68	1
one	auto[1]	437	1			T280	12		T191	1		T287	8
zero	auto[0]	545	1			T3	1		T29	1		T19	1
zero	auto[1]	11487	1			T29	2		T30	6		T33	4