Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68209

1

T1

1

T28

1

T29

3

auto[1]

76887

1

T29

4

T30

15

T31

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	10999	1			T30	3		T31	3		T21	1
endpoints[0x1]	11398	1			T30	5		T31	3		T36	1
endpoints[0x2]	9544	1			T30	2		T31	3		T4	21
endpoints[0x3]	13223	1			T30	2		T31	3		T35	3
endpoints[0x4]	12034	1			T30	3		T31	3		T33	7
endpoints[0x5]	11403	1			T30	4		T31	3		T18	1
endpoints[0x6]	12288	1			T30	1		T31	3		T23	24
endpoints[0x7]	11531	1			T1	1		T30	1		T31	3
endpoints[0x8]	12522	1			T31	3		T37	3		T88	1
endpoints[0x9]	13358	1			T30	2		T31	3		T32	11
endpoints[0xa]	14519	1			T28	1		T29	7		T31	3
endpoints[0xb]	12277	1			T30	1		T31	3		T4	21

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	175	1			T30	3		T111	7		T114	5
ack	37843	1			T29	2		T30	3		T31	12
data1	49946	1			T29	1		T30	9		T32	5
data0	57077	1			T1	1		T28	1		T29	4

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	15	1			T30	1		T111	1		T338	1
nak	auto[1]	endpoints[0x1]	22	1			T30	1		T338	1		T339	1
nak	auto[1]	endpoints[0x2]	10	1			T114	2		T340	1		T341	1
nak	auto[1]	endpoints[0x3]	16	1			T341	2		T342	2		T343	1
nak	auto[1]	endpoints[0x4]	10	1			T111	2		T114	1		T344	2
nak	auto[1]	endpoints[0x5]	19	1			T30	1		T345	1		T344	1
nak	auto[1]	endpoints[0x6]	16	1			T111	2		T346	1		T338	1
nak	auto[1]	endpoints[0x7]	11	1			T347	1		T344	1		T339	1
nak	auto[1]	endpoints[0x8]	15	1			T344	1		T339	1		T348	2
nak	auto[1]	endpoints[0x9]	16	1			T341	3		T342	1		T349	1
nak	auto[1]	endpoints[0xa]	12	1			T344	2		T339	1		T349	2
nak	auto[1]	endpoints[0xb]	13	1			T111	2		T114	2		T340	1
ack	auto[1]	endpoints[0x0]	3110	1			T31	1		T9	1		T157	16
ack	auto[1]	endpoints[0x1]	3179	1			T30	1		T31	1		T6	49
ack	auto[1]	endpoints[0x2]	2879	1			T30	1		T31	1		T4	7
ack	auto[1]	endpoints[0x3]	3224	1			T31	1		T35	1		T20	1
ack	auto[1]	endpoints[0x4]	3115	1			T30	1		T31	1		T33	3
ack	auto[1]	endpoints[0x5]	3000	1			T31	1		T158	1		T79	7
ack	auto[1]	endpoints[0x6]	3313	1			T31	1		T23	9		T5	32
ack	auto[1]	endpoints[0x7]	3052	1			T31	1		T158	1		T79	7
ack	auto[1]	endpoints[0x8]	3352	1			T31	1		T157	16		T168	16
ack	auto[1]	endpoints[0x9]	3341	1			T31	1		T4	7		T49	1
ack	auto[1]	endpoints[0xa]	3088	1			T29	2		T31	1		T17	1
ack	auto[1]	endpoints[0xb]	3190	1			T31	1		T4	7		T159	1
data1	auto[0]	endpoints[0x0]	1922	1			T30	1		T157	8		T160	3
data1	auto[0]	endpoints[0x1]	2029	1			T30	1		T6	17		T55	4
data1	auto[0]	endpoints[0x2]	1472	1			T4	1		T51	1		T95	2
data1	auto[0]	endpoints[0x3]	2864	1			T30	2		T4	3		T111	1
data1	auto[0]	endpoints[0x4]	2434	1			T38	5		T4	3		T163	1
data1	auto[0]	endpoints[0x5]	2272	1			T73	5		T111	1		T79	3
data1	auto[0]	endpoints[0x6]	2385	1			T30	1		T5	16		T79	5
data1	auto[0]	endpoints[0x7]	2173	1			T30	1		T24	1		T111	1
data1	auto[0]	endpoints[0x8]	2405	1			T157	5		T96	8		T168	4
data1	auto[0]	endpoints[0x9]	2897	1			T32	5		T4	3		T49	1
data1	auto[0]	endpoints[0xa]	3729	1			T29	1		T50	1		T280	23
data1	auto[0]	endpoints[0xb]	2455	1			T4	3		T159	1		T68	2
data1	auto[1]	endpoints[0x0]	1685	1			T157	8		T160	5		T68	4
data1	auto[1]	endpoints[0x1]	1800	1			T30	2		T6	32		T95	1
data1	auto[1]	endpoints[0x2]	1573	1			T4	6		T51	1		T95	2
data1	auto[1]	endpoints[0x3]	1802	1			T4	3		T107	3		T190	7
data1	auto[1]	endpoints[0x4]	1715	1			T33	1		T4	3		T163	1
data1	auto[1]	endpoints[0x5]	1630	1			T79	5		T280	21		T198	7
data1	auto[1]	endpoints[0x6]	1867	1			T23	8		T5	16		T79	4
data1	auto[1]	endpoints[0x7]	1708	1			T79	5		T169	4		T280	17
data1	auto[1]	endpoints[0x8]	1849	1			T157	11		T168	11		T79	3
data1	auto[1]	endpoints[0x9]	1837	1			T30	1		T4	3		T49	1
data1	auto[1]	endpoints[0xa]	1671	1			T50	1		T280	23		T162	3
data1	auto[1]	endpoints[0xb]	1772	1			T4	3		T159	1		T68	5
data0	auto[0]	endpoints[0x0]	2767	1			T31	1		T21	1		T9	1
data0	auto[0]	endpoints[0x1]	2864	1			T31	1		T36	1		T74	1
data0	auto[0]	endpoints[0x2]	2253	1			T31	1		T4	6		T89	1
data0	auto[0]	endpoints[0x3]	3774	1			T31	1		T35	1		T20	1
data0	auto[0]	endpoints[0x4]	3276	1			T30	1		T31	1		T38	6
data0	auto[0]	endpoints[0x5]	3035	1			T30	2		T31	1		T18	1
data0	auto[0]	endpoints[0x6]	3185	1			T31	1		T5	16		T350	1
data0	auto[0]	endpoints[0x7]	3154	1			T1	1		T31	1		T24	1
data0	auto[0]	endpoints[0x8]	3294	1			T31	1		T37	1		T88	1
data0	auto[0]	endpoints[0x9]	3683	1			T31	1		T32	6		T4	4
data0	auto[0]	endpoints[0xa]	4522	1			T28	1		T29	2		T31	1
data0	auto[0]	endpoints[0xb]	3360	1			T31	1		T4	4		T159	1
data0	auto[1]	endpoints[0x0]	1493	1			T30	1		T31	1		T9	1
data0	auto[1]	endpoints[0x1]	1500	1			T31	1		T6	17		T351	1
data0	auto[1]	endpoints[0x2]	1353	1			T30	1		T31	1		T4	1
data0	auto[1]	endpoints[0x3]	1539	1			T31	1		T35	1		T20	1
data0	auto[1]	endpoints[0x4]	1479	1			T30	1		T31	1		T33	3
data0	auto[1]	endpoints[0x5]	1444	1			T30	1		T31	1		T158	1
data0	auto[1]	endpoints[0x6]	1517	1			T31	1		T23	7		T5	16
data0	auto[1]	endpoints[0x7]	1430	1			T31	1		T111	1		T158	1
data0	auto[1]	endpoints[0x8]	1601	1			T31	1		T37	1		T157	5
data0	auto[1]	endpoints[0x9]	1580	1			T30	1		T31	1		T4	4
data0	auto[1]	endpoints[0xa]	1491	1			T29	2		T31	1		T17	1
data0	auto[1]	endpoints[0xb]	1483	1			T30	1		T31	1		T4	4