Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7484 1 T42 2 T68 4 T333 2
auto[1] 53214 1 T29 2 T30 9 T42 2


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 52970 1 T29 2 T30 9 T42 1
auto[1] 7728 1 T42 3 T36 1 T68 41


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55080 1 T29 2 T30 9 T42 3
auto[1] 5618 1 T42 1 T86 5 T34 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4137 1 T42 1 T86 1 T68 11
pkt_types[PidTypeInToken] 56561 1 T29 2 T30 9 T42 3


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1230 1 T68 3 T107 17 T115 37
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 625 1 T333 1 T107 20 T115 29
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 95 1 T68 1 T164 1 T365 4
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 10 1 T388 1 T387 1 T406 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1259 1 T68 3 T333 2 T107 10
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 793 1 T86 1 T107 53 T115 6
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 112 1 T42 1 T68 4 T164 2
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 13 1 T379 1 T502 1 T479 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3606 1 T333 1 T107 59 T115 102
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 1803 1 T42 1 T228 2 T107 83
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 58 1 T42 1 T526 1 T450 2
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 57 1 T447 1 T497 1 T388 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 41392 1 T29 2 T30 9 T31 12
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2262 1 T86 4 T34 1 T333 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7328 1 T42 1 T36 1 T68 36
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 55 1 T450 1 T398 1 T442 1

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