Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	90040	1			T1	4		T2	7		T3	3
all_pins[1]	90040	1			T1	4		T2	7		T3	3
all_pins[2]	90040	1			T1	4		T2	7		T3	3
all_pins[3]	90040	1			T1	4		T2	7		T3	3
all_pins[4]	90040	1			T1	4		T2	7		T3	3
all_pins[5]	90040	1			T1	4		T2	7		T3	3
all_pins[6]	90040	1			T1	4		T2	7		T3	3
all_pins[7]	90040	1			T1	4		T2	7		T3	3
all_pins[8]	90040	1			T1	4		T2	7		T3	3
all_pins[9]	90040	1			T1	4		T2	7		T3	3
all_pins[10]	90040	1			T1	4		T2	7		T3	3
all_pins[11]	90040	1			T1	4		T2	7		T3	3
all_pins[12]	90040	1			T1	4		T2	7		T3	3
all_pins[13]	90040	1			T1	4		T2	7		T3	3
all_pins[14]	90040	1			T1	4		T2	7		T3	3
all_pins[15]	90040	1			T1	4		T2	7		T3	3
all_pins[16]	90040	1			T1	4		T2	7		T3	3
all_pins[17]	90040	1			T1	4		T2	7		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2878971	1			T1	128		T2	222		T3	95
values[0x1]	2309	1			T2	2		T3	1		T28	1
transitions[0x0=>0x1]	2041	1			T2	2		T3	1		T28	1
transitions[0x1=>0x0]	2041	1			T2	2		T3	1		T28	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	89932	1			T1	4		T2	7		T3	3
all_pins[0]	values[0x1]	108	1			T362	1		T363	1		T364	1
all_pins[0]	transitions[0x0=>0x1]	93	1			T362	1		T363	1		T364	1
all_pins[0]	transitions[0x1=>0x0]	883	1			T31	12		T35	1		T7	1
all_pins[1]	values[0x0]	89142	1			T1	4		T2	7		T3	3
all_pins[1]	values[0x1]	898	1			T31	12		T35	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	890	1			T31	12		T35	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	102	1			T40	1		T66	1		T67	1
all_pins[2]	values[0x0]	89930	1			T1	4		T2	7		T3	3
all_pins[2]	values[0x1]	110	1			T40	1		T66	1		T67	1
all_pins[2]	transitions[0x0=>0x1]	85	1			T40	1		T66	1		T67	1
all_pins[2]	transitions[0x1=>0x0]	48	1			T19	1		T258	2		T259	1
all_pins[3]	values[0x0]	89967	1			T1	4		T2	7		T3	3
all_pins[3]	values[0x1]	73	1			T19	1		T258	2		T259	4
all_pins[3]	transitions[0x0=>0x1]	56	1			T19	1		T258	2		T259	4
all_pins[3]	transitions[0x1=>0x0]	40	1			T48	1		T262	1		T258	1
all_pins[4]	values[0x0]	89983	1			T1	4		T2	7		T3	3
all_pins[4]	values[0x1]	57	1			T48	1		T262	1		T258	1
all_pins[4]	transitions[0x0=>0x1]	40	1			T48	1		T262	1		T353	1
all_pins[4]	transitions[0x1=>0x0]	49	1			T262	2		T259	2		T352	1
all_pins[5]	values[0x0]	89974	1			T1	4		T2	7		T3	3
all_pins[5]	values[0x1]	66	1			T262	2		T258	1		T259	2
all_pins[5]	transitions[0x0=>0x1]	52	1			T259	2		T260	2		T352	2
all_pins[5]	transitions[0x1=>0x0]	101	1			T70	1		T71	1		T72	1
all_pins[6]	values[0x0]	89925	1			T1	4		T2	7		T3	3
all_pins[6]	values[0x1]	115	1			T70	1		T71	1		T72	1
all_pins[6]	transitions[0x0=>0x1]	103	1			T70	1		T71	1		T72	1
all_pins[6]	transitions[0x1=>0x0]	47	1			T52	1		T53	1		T54	1
all_pins[7]	values[0x0]	89981	1			T1	4		T2	7		T3	3
all_pins[7]	values[0x1]	59	1			T52	1		T53	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	44	1			T52	1		T53	1		T54	1
all_pins[7]	transitions[0x1=>0x0]	81	1			T56	1		T59	1		T61	1
all_pins[8]	values[0x0]	89944	1			T1	4		T2	7		T3	3
all_pins[8]	values[0x1]	96	1			T56	1		T59	1		T61	1
all_pins[8]	transitions[0x0=>0x1]	80	1			T56	1		T59	1		T61	1
all_pins[8]	transitions[0x1=>0x0]	58	1			T2	2		T64	2		T65	2
all_pins[9]	values[0x0]	89966	1			T1	4		T2	5		T3	3
all_pins[9]	values[0x1]	74	1			T2	2		T64	2		T65	2
all_pins[9]	transitions[0x0=>0x1]	54	1			T2	2		T64	2		T65	2
all_pins[9]	transitions[0x1=>0x0]	55	1			T262	1		T258	2		T259	1
all_pins[10]	values[0x0]	89965	1			T1	4		T2	7		T3	3
all_pins[10]	values[0x1]	75	1			T262	3		T258	3		T259	1
all_pins[10]	transitions[0x0=>0x1]	57	1			T258	1		T259	1		T352	1
all_pins[10]	transitions[0x1=>0x0]	91	1			T75	1		T76	1		T77	1
all_pins[11]	values[0x0]	89931	1			T1	4		T2	7		T3	3
all_pins[11]	values[0x1]	109	1			T75	1		T76	1		T77	1
all_pins[11]	transitions[0x0=>0x1]	96	1			T75	1		T76	1		T77	1
all_pins[11]	transitions[0x1=>0x0]	65	1			T78	1		T80	1		T81	1
all_pins[12]	values[0x0]	89962	1			T1	4		T2	7		T3	3
all_pins[12]	values[0x1]	78	1			T78	1		T80	1		T81	1
all_pins[12]	transitions[0x0=>0x1]	66	1			T78	1		T80	1		T81	1
all_pins[12]	transitions[0x1=>0x0]	100	1			T3	1		T84	1		T85	1
all_pins[13]	values[0x0]	89928	1			T1	4		T2	7		T3	2
all_pins[13]	values[0x1]	112	1			T3	1		T84	1		T85	1
all_pins[13]	transitions[0x0=>0x1]	99	1			T3	1		T84	1		T85	1
all_pins[13]	transitions[0x1=>0x0]	57	1			T260	1		T352	2		T327	3
all_pins[14]	values[0x0]	89970	1			T1	4		T2	7		T3	3
all_pins[14]	values[0x1]	70	1			T260	3		T352	2		T327	4
all_pins[14]	transitions[0x0=>0x1]	49	1			T352	2		T327	3		T357	3
all_pins[14]	transitions[0x1=>0x0]	51	1			T258	1		T259	2		T260	2
all_pins[15]	values[0x0]	89968	1			T1	4		T2	7		T3	3
all_pins[15]	values[0x1]	72	1			T258	1		T259	2		T260	5
all_pins[15]	transitions[0x0=>0x1]	53	1			T258	1		T259	2		T260	2
all_pins[15]	transitions[0x1=>0x0]	57	1			T32	4		T38	4		T73	4
all_pins[16]	values[0x0]	89964	1			T1	4		T2	7		T3	3
all_pins[16]	values[0x1]	76	1			T32	4		T38	4		T73	4
all_pins[16]	transitions[0x0=>0x1]	63	1			T32	4		T38	4		T73	4
all_pins[16]	transitions[0x1=>0x0]	48	1			T28	1		T62	1		T258	1
all_pins[17]	values[0x0]	89979	1			T1	4		T2	7		T3	3
all_pins[17]	values[0x1]	61	1			T28	1		T62	1		T258	1
all_pins[17]	transitions[0x0=>0x1]	61	1			T28	1		T62	1		T258	1