Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4251	1			T4	8		T228	1		T107	102
invalid_ep[0xd]	4120	1			T4	9		T228	2		T79	2
invalid_ep[0xe]	4215	1			T4	8		T228	1		T79	2
invalid_ep[0xf]	4239	1			T42	2		T4	8		T79	2
endpoints[0x0]	11744	1			T30	2		T42	1		T31	2
endpoints[0x1]	12080	1			T30	3		T42	1		T31	2
endpoints[0x2]	10548	1			T30	1		T86	3		T31	2
endpoints[0x3]	14311	1			T30	2		T86	1		T31	2
endpoints[0x4]	13219	1			T30	2		T42	1		T31	2
endpoints[0x5]	12322	1			T30	3		T42	1		T86	3
endpoints[0x6]	13065	1			T30	1		T42	2		T31	2
endpoints[0x7]	12222	1			T1	1		T3	1		T30	1
endpoints[0x8]	13129	1			T42	2		T31	2		T37	2
endpoints[0x9]	13395	1			T30	2		T42	1		T31	2
endpoints[0xa]	15750	1			T28	1		T29	5		T42	1
endpoints[0xb]	12753	1			T30	1		T86	12		T31	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	21810	1			T1	1		T28	1		T42	2
pkt_types[PidTypeOutToken]	73058	1			T3	1		T29	3		T30	9
pkt_types[PidTypeInToken]	60311	1			T29	2		T30	9		T42	3

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	926	1			T107	16		T115	20		T116	28
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	895	1			T107	29		T115	10		T116	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	939	1			T107	24		T115	23		T116	34
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	959	1			T42	1		T107	32		T115	20
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1434	1			T55	1		T229	1		T160	5
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1568	1			T6	23		T95	1		T68	3
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1497	1			T4	6		T89	1		T51	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1539	1			T107	30		T161	3		T115	14
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1472	1			T163	1		T79	3		T107	23
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1347	1			T79	5		T107	28		T115	22
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1605	1			T79	4		T107	21		T115	16
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1547	1			T1	1		T167	1		T228	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1557	1			T42	1		T157	8		T168	7
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1486	1			T49	1		T79	1		T107	26
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1499	1			T28	1		T50	1		T333	2
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1540	1			T86	1		T159	1		T68	4
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1437	1			T4	8		T107	30		T115	13
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1378	1			T4	9		T228	1		T79	2
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1384	1			T4	8		T79	2		T107	17
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1435	1			T4	8		T79	2		T107	30
pkt_types[PidTypeOutToken]	endpoints[0x0]	4639	1			T30	1		T31	1		T21	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	4792	1			T30	1		T31	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	3644	1			T86	1		T31	1		T4	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	6542	1			T30	2		T86	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5664	1			T30	1		T31	1		T38	11
pkt_types[PidTypeOutToken]	endpoints[0x5]	5474	1			T30	2		T42	1		T86	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	5539	1			T30	1		T42	2		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	5074	1			T3	1		T30	1		T42	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5628	1			T31	1		T37	1		T88	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6487	1			T42	1		T31	1		T32	11
pkt_types[PidTypeOutToken]	endpoints[0xa]	8326	1			T29	3		T31	1		T17	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	5615	1			T86	5		T31	1		T4	7
pkt_types[PidTypeInToken]	invalid_ep[0xc]	951	1			T228	1		T107	20		T115	18
pkt_types[PidTypeInToken]	invalid_ep[0xd]	917	1			T228	1		T107	22		T115	17
pkt_types[PidTypeInToken]	invalid_ep[0xe]	963	1			T107	27		T115	26		T116	27
pkt_types[PidTypeInToken]	invalid_ep[0xf]	919	1			T107	25		T115	20		T116	22
pkt_types[PidTypeInToken]	endpoints[0x0]	4672	1			T30	1		T42	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x1]	4653	1			T30	2		T31	1		T36	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4353	1			T30	1		T31	1		T4	8
pkt_types[PidTypeInToken]	endpoints[0x3]	5155	1			T31	1		T35	1		T20	1
pkt_types[PidTypeInToken]	endpoints[0x4]	4963	1			T30	1		T42	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4487	1			T30	1		T86	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4840	1			T31	1		T23	15		T5	33
pkt_types[PidTypeInToken]	endpoints[0x7]	4607	1			T31	1		T111	1		T158	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4871	1			T31	1		T37	1		T157	17
pkt_types[PidTypeInToken]	endpoints[0x9]	4448	1			T30	2		T31	1		T4	8
pkt_types[PidTypeInToken]	endpoints[0xa]	4916	1			T29	2		T42	1		T31	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4596	1			T30	1		T86	3		T31	1