Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T262	4		T258	4		T259	7
all_values[1]	284	1			T262	4		T258	4		T259	7
all_values[2]	284	1			T262	4		T258	4		T259	7
all_values[3]	284	1			T262	4		T258	4		T259	7
all_values[4]	284	1			T262	4		T258	4		T259	7
all_values[5]	284	1			T262	4		T258	4		T259	7
all_values[6]	284	1			T262	4		T258	4		T259	7
all_values[7]	284	1			T262	4		T258	4		T259	7
all_values[8]	284	1			T262	4		T258	4		T259	7
all_values[9]	284	1			T262	4		T258	4		T259	7
all_values[10]	284	1			T262	4		T258	4		T259	7
all_values[11]	284	1			T262	4		T258	4		T259	7
all_values[12]	284	1			T262	4		T258	4		T259	7
all_values[13]	284	1			T262	4		T258	4		T259	7
all_values[14]	284	1			T262	4		T258	4		T259	7
all_values[15]	284	1			T262	4		T258	4		T259	7
all_values[16]	284	1			T262	4		T258	4		T259	7
all_values[17]	284	1			T262	4		T258	4		T259	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6742

1

T262

103

T258

87

T259

157

auto[1]

2346

1

T262

25

T258

41

T259

67

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6250

1

T262

83

T258

89

T259

163

auto[1]

2838

1

T262

45

T258

39

T259

61

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5352

1

T262

70

T258

78

T259

135

auto[1]

3736

1

T262

58

T258

50

T259

89

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	86	1			T262	2		T258	2		T259	2
all_values[0]	auto[0]	auto[1]	auto[0]	89	1			T262	1		T258	1		T259	1
all_values[0]	auto[1]	auto[0]	auto[1]	62	1			T258	1		T260	3		T352	1
all_values[0]	auto[1]	auto[1]	auto[1]	47	1			T262	1		T259	4		T260	1
all_values[1]	auto[0]	auto[0]	auto[0]	85	1			T262	1		T259	1		T260	1
all_values[1]	auto[0]	auto[1]	auto[0]	88	1			T262	1		T258	4		T259	4
all_values[1]	auto[1]	auto[0]	auto[1]	63	1			T262	1		T260	3		T352	2
all_values[1]	auto[1]	auto[1]	auto[1]	48	1			T262	1		T259	2		T260	2
all_values[2]	auto[0]	auto[0]	auto[0]	50	1			T259	1		T260	3		T352	2
all_values[2]	auto[0]	auto[0]	auto[1]	42	1			T262	1		T258	1		T260	1
all_values[2]	auto[0]	auto[1]	auto[0]	33	1			T327	2		T353	2		T354	1
all_values[2]	auto[0]	auto[1]	auto[1]	30	1			T262	1		T258	2		T259	1
all_values[2]	auto[1]	auto[0]	auto[1]	72	1			T262	1		T259	1		T260	2
all_values[2]	auto[1]	auto[1]	auto[1]	57	1			T262	1		T258	1		T259	4
all_values[3]	auto[0]	auto[0]	auto[0]	67	1			T262	3		T258	1		T260	2
all_values[3]	auto[0]	auto[0]	auto[1]	24	1			T354	1		T355	3		T356	1
all_values[3]	auto[0]	auto[1]	auto[0]	51	1			T258	1		T260	1		T352	1
all_values[3]	auto[0]	auto[1]	auto[1]	24	1			T258	1		T259	1		T352	1
all_values[3]	auto[1]	auto[0]	auto[1]	60	1			T262	1		T258	1		T259	2
all_values[3]	auto[1]	auto[1]	auto[1]	58	1			T259	4		T260	1		T352	5
all_values[4]	auto[0]	auto[0]	auto[0]	58	1			T262	1		T260	1		T352	1
all_values[4]	auto[0]	auto[0]	auto[1]	34	1			T262	1		T258	1		T357	1
all_values[4]	auto[0]	auto[1]	auto[0]	51	1			T258	1		T259	5		T260	1
all_values[4]	auto[0]	auto[1]	auto[1]	22	1			T260	1		T352	1		T353	2
all_values[4]	auto[1]	auto[0]	auto[1]	66	1			T259	2		T260	4		T327	1
all_values[4]	auto[1]	auto[1]	auto[1]	53	1			T262	2		T258	2		T352	2
all_values[5]	auto[0]	auto[0]	auto[0]	55	1			T259	2		T260	2		T352	1
all_values[5]	auto[0]	auto[0]	auto[1]	18	1			T262	1		T258	1		T357	1
all_values[5]	auto[0]	auto[1]	auto[0]	61	1			T259	1		T352	1		T327	1
all_values[5]	auto[0]	auto[1]	auto[1]	30	1			T262	1		T259	1		T260	1
all_values[5]	auto[1]	auto[0]	auto[1]	70	1			T262	2		T260	4		T352	2
all_values[5]	auto[1]	auto[1]	auto[1]	50	1			T258	3		T259	3		T352	3
all_values[6]	auto[0]	auto[0]	auto[0]	57	1			T259	1		T260	3		T352	1
all_values[6]	auto[0]	auto[0]	auto[1]	23	1			T258	1		T259	2		T352	1
all_values[6]	auto[0]	auto[1]	auto[0]	62	1			T259	2		T260	1		T327	1
all_values[6]	auto[0]	auto[1]	auto[1]	24	1			T262	1		T352	1		T357	2
all_values[6]	auto[1]	auto[0]	auto[1]	51	1			T262	3		T260	1		T352	1
all_values[6]	auto[1]	auto[1]	auto[1]	67	1			T258	3		T259	2		T260	2
all_values[7]	auto[0]	auto[0]	auto[0]	88	1			T262	2		T258	2		T259	3
all_values[7]	auto[0]	auto[1]	auto[0]	81	1			T262	1		T260	2		T352	3
all_values[7]	auto[1]	auto[0]	auto[1]	63	1			T258	2		T260	1		T352	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T262	1		T259	4		T260	2
all_values[8]	auto[0]	auto[0]	auto[0]	98	1			T262	1		T258	1		T259	1
all_values[8]	auto[0]	auto[1]	auto[0]	67	1			T262	1		T258	3		T259	3
all_values[8]	auto[1]	auto[0]	auto[1]	58	1			T262	2		T259	1		T352	2
all_values[8]	auto[1]	auto[1]	auto[1]	61	1			T259	2		T260	2		T352	1
all_values[9]	auto[0]	auto[0]	auto[0]	73	1			T259	6		T260	2		T327	2
all_values[9]	auto[0]	auto[0]	auto[1]	26	1			T260	1		T352	3		T327	2
all_values[9]	auto[0]	auto[1]	auto[0]	45	1			T258	2		T260	1		T358	1
all_values[9]	auto[0]	auto[1]	auto[1]	25	1			T262	1		T359	1		T360	1
all_values[9]	auto[1]	auto[0]	auto[1]	67	1			T262	3		T258	1		T259	1
all_values[9]	auto[1]	auto[1]	auto[1]	48	1			T258	1		T260	1		T352	1
all_values[10]	auto[0]	auto[0]	auto[0]	60	1			T259	2		T327	3		T357	3
all_values[10]	auto[0]	auto[0]	auto[1]	28	1			T259	1		T260	3		T327	1
all_values[10]	auto[0]	auto[1]	auto[0]	45	1			T262	1		T352	2		T327	1
all_values[10]	auto[0]	auto[1]	auto[1]	26	1			T262	1		T258	2		T355	1
all_values[10]	auto[1]	auto[0]	auto[1]	70	1			T262	1		T258	1		T259	2
all_values[10]	auto[1]	auto[1]	auto[1]	55	1			T262	1		T258	1		T259	2
all_values[11]	auto[0]	auto[0]	auto[0]	68	1			T260	2		T352	1		T327	2
all_values[11]	auto[0]	auto[0]	auto[1]	27	1			T262	1		T258	1		T259	1
all_values[11]	auto[0]	auto[1]	auto[0]	50	1			T259	2		T352	1		T327	4
all_values[11]	auto[0]	auto[1]	auto[1]	23	1			T262	1		T258	1		T259	1
all_values[11]	auto[1]	auto[0]	auto[1]	73	1			T262	2		T258	2		T259	2
all_values[11]	auto[1]	auto[1]	auto[1]	43	1			T259	1		T260	3		T352	2
all_values[12]	auto[0]	auto[0]	auto[0]	71	1			T262	1		T258	3		T259	6
all_values[12]	auto[0]	auto[0]	auto[1]	26	1			T352	1		T327	1		T357	1
all_values[12]	auto[0]	auto[1]	auto[0]	34	1			T258	1		T260	2		T352	2
all_values[12]	auto[0]	auto[1]	auto[1]	32	1			T262	1		T260	1		T352	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1			T262	2		T259	1		T260	1
all_values[12]	auto[1]	auto[1]	auto[1]	51	1			T352	2		T327	2		T354	1
all_values[13]	auto[0]	auto[0]	auto[0]	57	1			T262	2		T258	1		T260	2
all_values[13]	auto[0]	auto[0]	auto[1]	25	1			T260	1		T327	1		T357	1
all_values[13]	auto[0]	auto[1]	auto[0]	62	1			T262	1		T259	5		T352	3
all_values[13]	auto[0]	auto[1]	auto[1]	28	1			T258	2		T259	1		T260	2
all_values[13]	auto[1]	auto[0]	auto[1]	57	1			T260	2		T352	1		T357	1
all_values[13]	auto[1]	auto[1]	auto[1]	55	1			T262	1		T258	1		T259	1
all_values[14]	auto[0]	auto[0]	auto[0]	63	1			T258	1		T259	4		T260	1
all_values[14]	auto[0]	auto[0]	auto[1]	27	1			T262	1		T352	2		T361	1
all_values[14]	auto[0]	auto[1]	auto[0]	42	1			T258	3		T259	1		T260	1
all_values[14]	auto[0]	auto[1]	auto[1]	31	1			T260	2		T352	1		T327	1
all_values[14]	auto[1]	auto[0]	auto[1]	69	1			T262	3		T259	2		T260	3
all_values[14]	auto[1]	auto[1]	auto[1]	52	1			T352	1		T327	3		T357	1
all_values[15]	auto[0]	auto[0]	auto[0]	61	1			T262	2		T258	3		T259	3
all_values[15]	auto[0]	auto[0]	auto[1]	23	1			T259	1		T352	1		T327	1
all_values[15]	auto[0]	auto[1]	auto[0]	50	1			T262	1		T259	1		T260	1
all_values[15]	auto[0]	auto[1]	auto[1]	36	1			T259	1		T260	2		T352	1
all_values[15]	auto[1]	auto[0]	auto[1]	51	1			T262	1		T259	1		T260	2
all_values[15]	auto[1]	auto[1]	auto[1]	63	1			T258	1		T260	2		T352	1
all_values[16]	auto[0]	auto[0]	auto[0]	61	1			T262	1		T259	2		T260	1
all_values[16]	auto[0]	auto[0]	auto[1]	31	1			T258	1		T259	1		T353	1
all_values[16]	auto[0]	auto[1]	auto[0]	44	1			T262	1		T258	1		T259	1
all_values[16]	auto[0]	auto[1]	auto[1]	26	1			T259	1		T260	1		T327	1
all_values[16]	auto[1]	auto[0]	auto[1]	72	1			T262	1		T258	2		T259	1
all_values[16]	auto[1]	auto[1]	auto[1]	50	1			T262	1		T259	1		T260	2
all_values[17]	auto[0]	auto[0]	auto[0]	84	1			T262	2		T259	2		T260	1
all_values[17]	auto[0]	auto[1]	auto[0]	77	1			T262	1		T258	2		T259	3
all_values[17]	auto[1]	auto[0]	auto[1]	76	1			T262	1		T258	1		T259	1
all_values[17]	auto[1]	auto[1]	auto[1]	47	1			T258	1		T259	1		T260	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal