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74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
76 1/1 err_q <= '0;
Tests: T1 T2 T3
77 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
78 1/1 err_q <= 1'b1;
Tests: T246 T247 T248
79 end
MISSING_ELSE
80 end
81
82 // integrity error output is permanent and should be used for alert generation
83 // register errors are transactional
84 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
85
86 // outgoing integrity generation
87 tlul_pkg::tl_d2h_t tl_o_pre;
88 tlul_rsp_intg_gen #(
89 .EnableRspIntgGen(1),
90 .EnableDataIntgGen(1)
91 ) u_rsp_intg_gen (
92 .tl_i(tl_o_pre),
93 .tl_o(tl_o)
94 );
95
96 tlul_pkg::tl_h2d_t tl_socket_h2d [2];
97 tlul_pkg::tl_d2h_t tl_socket_d2h [2];
98
99 logic [0:0] reg_steer;
100
101 // socket_1n connection
102 1/1 assign tl_reg_h2d = tl_socket_h2d[1];
Tests: T1 T2 T3
103 1/1 assign tl_socket_d2h[1] = tl_reg_d2h;
Tests: T1 T2 T3
104
105 1/1 assign tl_win_o = tl_socket_h2d[0];
Tests: T1 T2 T3
106 1/1 assign tl_socket_d2h[0] = tl_win_i;
Tests: T1 T2 T3
107
108 // Create Socket_1n
109 tlul_socket_1n #(
110 .N (2),
111 .HReqPass (1'b1),
112 .HRspPass (1'b1),
113 .DReqPass ({2{1'b1}}),
114 .DRspPass ({2{1'b1}}),
115 .HReqDepth (4'h0),
116 .HRspDepth (4'h0),
117 .DReqDepth ({2{4'h0}}),
118 .DRspDepth ({2{4'h0}}),
119 .ExplicitErrs (1'b0)
120 ) u_socket (
121 .clk_i (clk_i),
122 .rst_ni (rst_ni),
123 .tl_h_i (tl_i),
124 .tl_h_o (tl_o_pre),
125 .tl_d_o (tl_socket_h2d),
126 .tl_d_i (tl_socket_d2h),
127 .dev_select_i (reg_steer)
128 );
129
130 // Create steering logic
131 always_comb begin
132 1/1 reg_steer =
Tests: T1 T2 T3
133 tl_i.a_address[AW-1:0] inside {[2048:4095]} ? 1'd0 :
134 // Default set to register
135 1'd1;
136
137 // Override this in case of an integrity error
138 1/1 if (intg_err) begin
Tests: T1 T2 T3
139 1/1 reg_steer = 1'd1;
Tests: T269 T276 T277
140 end
MISSING_ELSE
141 end
142
143 tlul_adapter_reg #(
144 .RegAw(AW),
145 .RegDw(DW),
146 .EnableDataIntgGen(0)
147 ) u_reg_if (
148 .clk_i (clk_i),
149 .rst_ni (rst_ni),
150
151 .tl_i (tl_reg_h2d),
152 .tl_o (tl_reg_d2h),
153
154 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
155 .intg_error_o(),
156
157 .we_o (reg_we),
158 .re_o (reg_re),
159 .addr_o (reg_addr),
160 .wdata_o (reg_wdata),
161 .be_o (reg_be),
162 .busy_i (reg_busy),
163 .rdata_i (reg_rdata),
164 .error_i (reg_error)
165 );
166
167 // cdc oversampling signals
168
169 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T1 T2 T3
170 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T2 T28 T30
171
172 // Define SW related signals
173 // Format: <reg>_<field>_{wd|we|qs}
174 // or <reg>_{wd|we|qs} if field == 1 or 0
175 logic intr_state_we;
176 logic intr_state_pkt_received_qs;
177 logic intr_state_pkt_sent_qs;
178 logic intr_state_disconnected_qs;
179 logic intr_state_disconnected_wd;
180 logic intr_state_host_lost_qs;
181 logic intr_state_host_lost_wd;
182 logic intr_state_link_reset_qs;
183 logic intr_state_link_reset_wd;
184 logic intr_state_link_suspend_qs;
185 logic intr_state_link_suspend_wd;
186 logic intr_state_link_resume_qs;
187 logic intr_state_link_resume_wd;
188 logic intr_state_av_out_empty_qs;
189 logic intr_state_rx_full_qs;
190 logic intr_state_av_overflow_qs;
191 logic intr_state_av_overflow_wd;
192 logic intr_state_link_in_err_qs;
193 logic intr_state_link_in_err_wd;
194 logic intr_state_rx_crc_err_qs;
195 logic intr_state_rx_crc_err_wd;
196 logic intr_state_rx_pid_err_qs;
197 logic intr_state_rx_pid_err_wd;
198 logic intr_state_rx_bitstuff_err_qs;
199 logic intr_state_rx_bitstuff_err_wd;
200 logic intr_state_frame_qs;
201 logic intr_state_frame_wd;
202 logic intr_state_powered_qs;
203 logic intr_state_powered_wd;
204 logic intr_state_link_out_err_qs;
205 logic intr_state_link_out_err_wd;
206 logic intr_state_av_setup_empty_qs;
207 logic intr_enable_we;
208 logic intr_enable_pkt_received_qs;
209 logic intr_enable_pkt_received_wd;
210 logic intr_enable_pkt_sent_qs;
211 logic intr_enable_pkt_sent_wd;
212 logic intr_enable_disconnected_qs;
213 logic intr_enable_disconnected_wd;
214 logic intr_enable_host_lost_qs;
215 logic intr_enable_host_lost_wd;
216 logic intr_enable_link_reset_qs;
217 logic intr_enable_link_reset_wd;
218 logic intr_enable_link_suspend_qs;
219 logic intr_enable_link_suspend_wd;
220 logic intr_enable_link_resume_qs;
221 logic intr_enable_link_resume_wd;
222 logic intr_enable_av_out_empty_qs;
223 logic intr_enable_av_out_empty_wd;
224 logic intr_enable_rx_full_qs;
225 logic intr_enable_rx_full_wd;
226 logic intr_enable_av_overflow_qs;
227 logic intr_enable_av_overflow_wd;
228 logic intr_enable_link_in_err_qs;
229 logic intr_enable_link_in_err_wd;
230 logic intr_enable_rx_crc_err_qs;
231 logic intr_enable_rx_crc_err_wd;
232 logic intr_enable_rx_pid_err_qs;
233 logic intr_enable_rx_pid_err_wd;
234 logic intr_enable_rx_bitstuff_err_qs;
235 logic intr_enable_rx_bitstuff_err_wd;
236 logic intr_enable_frame_qs;
237 logic intr_enable_frame_wd;
238 logic intr_enable_powered_qs;
239 logic intr_enable_powered_wd;
240 logic intr_enable_link_out_err_qs;
241 logic intr_enable_link_out_err_wd;
242 logic intr_enable_av_setup_empty_qs;
243 logic intr_enable_av_setup_empty_wd;
244 logic intr_test_we;
245 logic intr_test_pkt_received_wd;
246 logic intr_test_pkt_sent_wd;
247 logic intr_test_disconnected_wd;
248 logic intr_test_host_lost_wd;
249 logic intr_test_link_reset_wd;
250 logic intr_test_link_suspend_wd;
251 logic intr_test_link_resume_wd;
252 logic intr_test_av_out_empty_wd;
253 logic intr_test_rx_full_wd;
254 logic intr_test_av_overflow_wd;
255 logic intr_test_link_in_err_wd;
256 logic intr_test_rx_crc_err_wd;
257 logic intr_test_rx_pid_err_wd;
258 logic intr_test_rx_bitstuff_err_wd;
259 logic intr_test_frame_wd;
260 logic intr_test_powered_wd;
261 logic intr_test_link_out_err_wd;
262 logic intr_test_av_setup_empty_wd;
263 logic alert_test_we;
264 logic alert_test_wd;
265 logic usbctrl_we;
266 logic usbctrl_enable_qs;
267 logic usbctrl_enable_wd;
268 logic usbctrl_resume_link_active_wd;
269 logic [6:0] usbctrl_device_address_qs;
270 logic [6:0] usbctrl_device_address_wd;
271 logic ep_out_enable_we;
272 logic ep_out_enable_enable_0_qs;
273 logic ep_out_enable_enable_0_wd;
274 logic ep_out_enable_enable_1_qs;
275 logic ep_out_enable_enable_1_wd;
276 logic ep_out_enable_enable_2_qs;
277 logic ep_out_enable_enable_2_wd;
278 logic ep_out_enable_enable_3_qs;
279 logic ep_out_enable_enable_3_wd;
280 logic ep_out_enable_enable_4_qs;
281 logic ep_out_enable_enable_4_wd;
282 logic ep_out_enable_enable_5_qs;
283 logic ep_out_enable_enable_5_wd;
284 logic ep_out_enable_enable_6_qs;
285 logic ep_out_enable_enable_6_wd;
286 logic ep_out_enable_enable_7_qs;
287 logic ep_out_enable_enable_7_wd;
288 logic ep_out_enable_enable_8_qs;
289 logic ep_out_enable_enable_8_wd;
290 logic ep_out_enable_enable_9_qs;
291 logic ep_out_enable_enable_9_wd;
292 logic ep_out_enable_enable_10_qs;
293 logic ep_out_enable_enable_10_wd;
294 logic ep_out_enable_enable_11_qs;
295 logic ep_out_enable_enable_11_wd;
296 logic ep_in_enable_we;
297 logic ep_in_enable_enable_0_qs;
298 logic ep_in_enable_enable_0_wd;
299 logic ep_in_enable_enable_1_qs;
300 logic ep_in_enable_enable_1_wd;
301 logic ep_in_enable_enable_2_qs;
302 logic ep_in_enable_enable_2_wd;
303 logic ep_in_enable_enable_3_qs;
304 logic ep_in_enable_enable_3_wd;
305 logic ep_in_enable_enable_4_qs;
306 logic ep_in_enable_enable_4_wd;
307 logic ep_in_enable_enable_5_qs;
308 logic ep_in_enable_enable_5_wd;
309 logic ep_in_enable_enable_6_qs;
310 logic ep_in_enable_enable_6_wd;
311 logic ep_in_enable_enable_7_qs;
312 logic ep_in_enable_enable_7_wd;
313 logic ep_in_enable_enable_8_qs;
314 logic ep_in_enable_enable_8_wd;
315 logic ep_in_enable_enable_9_qs;
316 logic ep_in_enable_enable_9_wd;
317 logic ep_in_enable_enable_10_qs;
318 logic ep_in_enable_enable_10_wd;
319 logic ep_in_enable_enable_11_qs;
320 logic ep_in_enable_enable_11_wd;
321 logic usbstat_re;
322 logic [10:0] usbstat_frame_qs;
323 logic usbstat_host_lost_qs;
324 logic [2:0] usbstat_link_state_qs;
325 logic usbstat_sense_qs;
326 logic [3:0] usbstat_av_out_depth_qs;
327 logic [2:0] usbstat_av_setup_depth_qs;
328 logic usbstat_av_out_full_qs;
329 logic [3:0] usbstat_rx_depth_qs;
330 logic usbstat_av_setup_full_qs;
331 logic usbstat_rx_empty_qs;
332 logic avoutbuffer_we;
333 logic [4:0] avoutbuffer_wd;
334 logic avsetupbuffer_we;
335 logic [4:0] avsetupbuffer_wd;
336 logic rxfifo_re;
337 logic [4:0] rxfifo_buffer_qs;
338 logic [6:0] rxfifo_size_qs;
339 logic rxfifo_setup_qs;
340 logic [3:0] rxfifo_ep_qs;
341 logic rxenable_setup_we;
342 logic rxenable_setup_setup_0_qs;
343 logic rxenable_setup_setup_0_wd;
344 logic rxenable_setup_setup_1_qs;
345 logic rxenable_setup_setup_1_wd;
346 logic rxenable_setup_setup_2_qs;
347 logic rxenable_setup_setup_2_wd;
348 logic rxenable_setup_setup_3_qs;
349 logic rxenable_setup_setup_3_wd;
350 logic rxenable_setup_setup_4_qs;
351 logic rxenable_setup_setup_4_wd;
352 logic rxenable_setup_setup_5_qs;
353 logic rxenable_setup_setup_5_wd;
354 logic rxenable_setup_setup_6_qs;
355 logic rxenable_setup_setup_6_wd;
356 logic rxenable_setup_setup_7_qs;
357 logic rxenable_setup_setup_7_wd;
358 logic rxenable_setup_setup_8_qs;
359 logic rxenable_setup_setup_8_wd;
360 logic rxenable_setup_setup_9_qs;
361 logic rxenable_setup_setup_9_wd;
362 logic rxenable_setup_setup_10_qs;
363 logic rxenable_setup_setup_10_wd;
364 logic rxenable_setup_setup_11_qs;
365 logic rxenable_setup_setup_11_wd;
366 logic rxenable_out_we;
367 logic rxenable_out_out_0_qs;
368 logic rxenable_out_out_0_wd;
369 logic rxenable_out_out_1_qs;
370 logic rxenable_out_out_1_wd;
371 logic rxenable_out_out_2_qs;
372 logic rxenable_out_out_2_wd;
373 logic rxenable_out_out_3_qs;
374 logic rxenable_out_out_3_wd;
375 logic rxenable_out_out_4_qs;
376 logic rxenable_out_out_4_wd;
377 logic rxenable_out_out_5_qs;
378 logic rxenable_out_out_5_wd;
379 logic rxenable_out_out_6_qs;
380 logic rxenable_out_out_6_wd;
381 logic rxenable_out_out_7_qs;
382 logic rxenable_out_out_7_wd;
383 logic rxenable_out_out_8_qs;
384 logic rxenable_out_out_8_wd;
385 logic rxenable_out_out_9_qs;
386 logic rxenable_out_out_9_wd;
387 logic rxenable_out_out_10_qs;
388 logic rxenable_out_out_10_wd;
389 logic rxenable_out_out_11_qs;
390 logic rxenable_out_out_11_wd;
391 logic set_nak_out_we;
392 logic set_nak_out_enable_0_qs;
393 logic set_nak_out_enable_0_wd;
394 logic set_nak_out_enable_1_qs;
395 logic set_nak_out_enable_1_wd;
396 logic set_nak_out_enable_2_qs;
397 logic set_nak_out_enable_2_wd;
398 logic set_nak_out_enable_3_qs;
399 logic set_nak_out_enable_3_wd;
400 logic set_nak_out_enable_4_qs;
401 logic set_nak_out_enable_4_wd;
402 logic set_nak_out_enable_5_qs;
403 logic set_nak_out_enable_5_wd;
404 logic set_nak_out_enable_6_qs;
405 logic set_nak_out_enable_6_wd;
406 logic set_nak_out_enable_7_qs;
407 logic set_nak_out_enable_7_wd;
408 logic set_nak_out_enable_8_qs;
409 logic set_nak_out_enable_8_wd;
410 logic set_nak_out_enable_9_qs;
411 logic set_nak_out_enable_9_wd;
412 logic set_nak_out_enable_10_qs;
413 logic set_nak_out_enable_10_wd;
414 logic set_nak_out_enable_11_qs;
415 logic set_nak_out_enable_11_wd;
416 logic in_sent_we;
417 logic in_sent_sent_0_qs;
418 logic in_sent_sent_0_wd;
419 logic in_sent_sent_1_qs;
420 logic in_sent_sent_1_wd;
421 logic in_sent_sent_2_qs;
422 logic in_sent_sent_2_wd;
423 logic in_sent_sent_3_qs;
424 logic in_sent_sent_3_wd;
425 logic in_sent_sent_4_qs;
426 logic in_sent_sent_4_wd;
427 logic in_sent_sent_5_qs;
428 logic in_sent_sent_5_wd;
429 logic in_sent_sent_6_qs;
430 logic in_sent_sent_6_wd;
431 logic in_sent_sent_7_qs;
432 logic in_sent_sent_7_wd;
433 logic in_sent_sent_8_qs;
434 logic in_sent_sent_8_wd;
435 logic in_sent_sent_9_qs;
436 logic in_sent_sent_9_wd;
437 logic in_sent_sent_10_qs;
438 logic in_sent_sent_10_wd;
439 logic in_sent_sent_11_qs;
440 logic in_sent_sent_11_wd;
441 logic out_stall_we;
442 logic out_stall_endpoint_0_qs;
443 logic out_stall_endpoint_0_wd;
444 logic out_stall_endpoint_1_qs;
445 logic out_stall_endpoint_1_wd;
446 logic out_stall_endpoint_2_qs;
447 logic out_stall_endpoint_2_wd;
448 logic out_stall_endpoint_3_qs;
449 logic out_stall_endpoint_3_wd;
450 logic out_stall_endpoint_4_qs;
451 logic out_stall_endpoint_4_wd;
452 logic out_stall_endpoint_5_qs;
453 logic out_stall_endpoint_5_wd;
454 logic out_stall_endpoint_6_qs;
455 logic out_stall_endpoint_6_wd;
456 logic out_stall_endpoint_7_qs;
457 logic out_stall_endpoint_7_wd;
458 logic out_stall_endpoint_8_qs;
459 logic out_stall_endpoint_8_wd;
460 logic out_stall_endpoint_9_qs;
461 logic out_stall_endpoint_9_wd;
462 logic out_stall_endpoint_10_qs;
463 logic out_stall_endpoint_10_wd;
464 logic out_stall_endpoint_11_qs;
465 logic out_stall_endpoint_11_wd;
466 logic in_stall_we;
467 logic in_stall_endpoint_0_qs;
468 logic in_stall_endpoint_0_wd;
469 logic in_stall_endpoint_1_qs;
470 logic in_stall_endpoint_1_wd;
471 logic in_stall_endpoint_2_qs;
472 logic in_stall_endpoint_2_wd;
473 logic in_stall_endpoint_3_qs;
474 logic in_stall_endpoint_3_wd;
475 logic in_stall_endpoint_4_qs;
476 logic in_stall_endpoint_4_wd;
477 logic in_stall_endpoint_5_qs;
478 logic in_stall_endpoint_5_wd;
479 logic in_stall_endpoint_6_qs;
480 logic in_stall_endpoint_6_wd;
481 logic in_stall_endpoint_7_qs;
482 logic in_stall_endpoint_7_wd;
483 logic in_stall_endpoint_8_qs;
484 logic in_stall_endpoint_8_wd;
485 logic in_stall_endpoint_9_qs;
486 logic in_stall_endpoint_9_wd;
487 logic in_stall_endpoint_10_qs;
488 logic in_stall_endpoint_10_wd;
489 logic in_stall_endpoint_11_qs;
490 logic in_stall_endpoint_11_wd;
491 logic configin_0_we;
492 logic [4:0] configin_0_buffer_0_qs;
493 logic [4:0] configin_0_buffer_0_wd;
494 logic [6:0] configin_0_size_0_qs;
495 logic [6:0] configin_0_size_0_wd;
496 logic configin_0_sending_0_qs;
497 logic configin_0_sending_0_wd;
498 logic configin_0_pend_0_qs;
499 logic configin_0_pend_0_wd;
500 logic configin_0_rdy_0_qs;
501 logic configin_0_rdy_0_wd;
502 logic configin_1_we;
503 logic [4:0] configin_1_buffer_1_qs;
504 logic [4:0] configin_1_buffer_1_wd;
505 logic [6:0] configin_1_size_1_qs;
506 logic [6:0] configin_1_size_1_wd;
507 logic configin_1_sending_1_qs;
508 logic configin_1_sending_1_wd;
509 logic configin_1_pend_1_qs;
510 logic configin_1_pend_1_wd;
511 logic configin_1_rdy_1_qs;
512 logic configin_1_rdy_1_wd;
513 logic configin_2_we;
514 logic [4:0] configin_2_buffer_2_qs;
515 logic [4:0] configin_2_buffer_2_wd;
516 logic [6:0] configin_2_size_2_qs;
517 logic [6:0] configin_2_size_2_wd;
518 logic configin_2_sending_2_qs;
519 logic configin_2_sending_2_wd;
520 logic configin_2_pend_2_qs;
521 logic configin_2_pend_2_wd;
522 logic configin_2_rdy_2_qs;
523 logic configin_2_rdy_2_wd;
524 logic configin_3_we;
525 logic [4:0] configin_3_buffer_3_qs;
526 logic [4:0] configin_3_buffer_3_wd;
527 logic [6:0] configin_3_size_3_qs;
528 logic [6:0] configin_3_size_3_wd;
529 logic configin_3_sending_3_qs;
530 logic configin_3_sending_3_wd;
531 logic configin_3_pend_3_qs;
532 logic configin_3_pend_3_wd;
533 logic configin_3_rdy_3_qs;
534 logic configin_3_rdy_3_wd;
535 logic configin_4_we;
536 logic [4:0] configin_4_buffer_4_qs;
537 logic [4:0] configin_4_buffer_4_wd;
538 logic [6:0] configin_4_size_4_qs;
539 logic [6:0] configin_4_size_4_wd;
540 logic configin_4_sending_4_qs;
541 logic configin_4_sending_4_wd;
542 logic configin_4_pend_4_qs;
543 logic configin_4_pend_4_wd;
544 logic configin_4_rdy_4_qs;
545 logic configin_4_rdy_4_wd;
546 logic configin_5_we;
547 logic [4:0] configin_5_buffer_5_qs;
548 logic [4:0] configin_5_buffer_5_wd;
549 logic [6:0] configin_5_size_5_qs;
550 logic [6:0] configin_5_size_5_wd;
551 logic configin_5_sending_5_qs;
552 logic configin_5_sending_5_wd;
553 logic configin_5_pend_5_qs;
554 logic configin_5_pend_5_wd;
555 logic configin_5_rdy_5_qs;
556 logic configin_5_rdy_5_wd;
557 logic configin_6_we;
558 logic [4:0] configin_6_buffer_6_qs;
559 logic [4:0] configin_6_buffer_6_wd;
560 logic [6:0] configin_6_size_6_qs;
561 logic [6:0] configin_6_size_6_wd;
562 logic configin_6_sending_6_qs;
563 logic configin_6_sending_6_wd;
564 logic configin_6_pend_6_qs;
565 logic configin_6_pend_6_wd;
566 logic configin_6_rdy_6_qs;
567 logic configin_6_rdy_6_wd;
568 logic configin_7_we;
569 logic [4:0] configin_7_buffer_7_qs;
570 logic [4:0] configin_7_buffer_7_wd;
571 logic [6:0] configin_7_size_7_qs;
572 logic [6:0] configin_7_size_7_wd;
573 logic configin_7_sending_7_qs;
574 logic configin_7_sending_7_wd;
575 logic configin_7_pend_7_qs;
576 logic configin_7_pend_7_wd;
577 logic configin_7_rdy_7_qs;
578 logic configin_7_rdy_7_wd;
579 logic configin_8_we;
580 logic [4:0] configin_8_buffer_8_qs;
581 logic [4:0] configin_8_buffer_8_wd;
582 logic [6:0] configin_8_size_8_qs;
583 logic [6:0] configin_8_size_8_wd;
584 logic configin_8_sending_8_qs;
585 logic configin_8_sending_8_wd;
586 logic configin_8_pend_8_qs;
587 logic configin_8_pend_8_wd;
588 logic configin_8_rdy_8_qs;
589 logic configin_8_rdy_8_wd;
590 logic configin_9_we;
591 logic [4:0] configin_9_buffer_9_qs;
592 logic [4:0] configin_9_buffer_9_wd;
593 logic [6:0] configin_9_size_9_qs;
594 logic [6:0] configin_9_size_9_wd;
595 logic configin_9_sending_9_qs;
596 logic configin_9_sending_9_wd;
597 logic configin_9_pend_9_qs;
598 logic configin_9_pend_9_wd;
599 logic configin_9_rdy_9_qs;
600 logic configin_9_rdy_9_wd;
601 logic configin_10_we;
602 logic [4:0] configin_10_buffer_10_qs;
603 logic [4:0] configin_10_buffer_10_wd;
604 logic [6:0] configin_10_size_10_qs;
605 logic [6:0] configin_10_size_10_wd;
606 logic configin_10_sending_10_qs;
607 logic configin_10_sending_10_wd;
608 logic configin_10_pend_10_qs;
609 logic configin_10_pend_10_wd;
610 logic configin_10_rdy_10_qs;
611 logic configin_10_rdy_10_wd;
612 logic configin_11_we;
613 logic [4:0] configin_11_buffer_11_qs;
614 logic [4:0] configin_11_buffer_11_wd;
615 logic [6:0] configin_11_size_11_qs;
616 logic [6:0] configin_11_size_11_wd;
617 logic configin_11_sending_11_qs;
618 logic configin_11_sending_11_wd;
619 logic configin_11_pend_11_qs;
620 logic configin_11_pend_11_wd;
621 logic configin_11_rdy_11_qs;
622 logic configin_11_rdy_11_wd;
623 logic out_iso_we;
624 logic out_iso_iso_0_qs;
625 logic out_iso_iso_0_wd;
626 logic out_iso_iso_1_qs;
627 logic out_iso_iso_1_wd;
628 logic out_iso_iso_2_qs;
629 logic out_iso_iso_2_wd;
630 logic out_iso_iso_3_qs;
631 logic out_iso_iso_3_wd;
632 logic out_iso_iso_4_qs;
633 logic out_iso_iso_4_wd;
634 logic out_iso_iso_5_qs;
635 logic out_iso_iso_5_wd;
636 logic out_iso_iso_6_qs;
637 logic out_iso_iso_6_wd;
638 logic out_iso_iso_7_qs;
639 logic out_iso_iso_7_wd;
640 logic out_iso_iso_8_qs;
641 logic out_iso_iso_8_wd;
642 logic out_iso_iso_9_qs;
643 logic out_iso_iso_9_wd;
644 logic out_iso_iso_10_qs;
645 logic out_iso_iso_10_wd;
646 logic out_iso_iso_11_qs;
647 logic out_iso_iso_11_wd;
648 logic in_iso_we;
649 logic in_iso_iso_0_qs;
650 logic in_iso_iso_0_wd;
651 logic in_iso_iso_1_qs;
652 logic in_iso_iso_1_wd;
653 logic in_iso_iso_2_qs;
654 logic in_iso_iso_2_wd;
655 logic in_iso_iso_3_qs;
656 logic in_iso_iso_3_wd;
657 logic in_iso_iso_4_qs;
658 logic in_iso_iso_4_wd;
659 logic in_iso_iso_5_qs;
660 logic in_iso_iso_5_wd;
661 logic in_iso_iso_6_qs;
662 logic in_iso_iso_6_wd;
663 logic in_iso_iso_7_qs;
664 logic in_iso_iso_7_wd;
665 logic in_iso_iso_8_qs;
666 logic in_iso_iso_8_wd;
667 logic in_iso_iso_9_qs;
668 logic in_iso_iso_9_wd;
669 logic in_iso_iso_10_qs;
670 logic in_iso_iso_10_wd;
671 logic in_iso_iso_11_qs;
672 logic in_iso_iso_11_wd;
673 logic out_data_toggle_re;
674 logic out_data_toggle_we;
675 logic [11:0] out_data_toggle_status_qs;
676 logic [11:0] out_data_toggle_status_wd;
677 logic [11:0] out_data_toggle_mask_qs;
678 logic [11:0] out_data_toggle_mask_wd;
679 logic in_data_toggle_re;
680 logic in_data_toggle_we;
681 logic [11:0] in_data_toggle_status_qs;
682 logic [11:0] in_data_toggle_status_wd;
683 logic [11:0] in_data_toggle_mask_qs;
684 logic [11:0] in_data_toggle_mask_wd;
685 logic phy_pins_sense_re;
686 logic phy_pins_sense_rx_dp_i_qs;
687 logic phy_pins_sense_rx_dn_i_qs;
688 logic phy_pins_sense_rx_d_i_qs;
689 logic phy_pins_sense_tx_dp_o_qs;
690 logic phy_pins_sense_tx_dn_o_qs;
691 logic phy_pins_sense_tx_d_o_qs;
692 logic phy_pins_sense_tx_se0_o_qs;
693 logic phy_pins_sense_tx_oe_o_qs;
694 logic phy_pins_sense_pwr_sense_qs;
695 logic phy_pins_drive_we;
696 logic phy_pins_drive_dp_o_qs;
697 logic phy_pins_drive_dp_o_wd;
698 logic phy_pins_drive_dn_o_qs;
699 logic phy_pins_drive_dn_o_wd;
700 logic phy_pins_drive_d_o_qs;
701 logic phy_pins_drive_d_o_wd;
702 logic phy_pins_drive_se0_o_qs;
703 logic phy_pins_drive_se0_o_wd;
704 logic phy_pins_drive_oe_o_qs;
705 logic phy_pins_drive_oe_o_wd;
706 logic phy_pins_drive_rx_enable_o_qs;
707 logic phy_pins_drive_rx_enable_o_wd;
708 logic phy_pins_drive_dp_pullup_en_o_qs;
709 logic phy_pins_drive_dp_pullup_en_o_wd;
710 logic phy_pins_drive_dn_pullup_en_o_qs;
711 logic phy_pins_drive_dn_pullup_en_o_wd;
712 logic phy_pins_drive_en_qs;
713 logic phy_pins_drive_en_wd;
714 logic phy_config_we;
715 logic phy_config_use_diff_rcvr_qs;
716 logic phy_config_use_diff_rcvr_wd;
717 logic phy_config_tx_use_d_se0_qs;
718 logic phy_config_tx_use_d_se0_wd;
719 logic phy_config_eop_single_bit_qs;
720 logic phy_config_eop_single_bit_wd;
721 logic phy_config_pinflip_qs;
722 logic phy_config_pinflip_wd;
723 logic phy_config_usb_ref_disable_qs;
724 logic phy_config_usb_ref_disable_wd;
725 logic phy_config_tx_osc_test_mode_qs;
726 logic phy_config_tx_osc_test_mode_wd;
727 logic wake_control_we;
728 logic [1:0] wake_control_qs;
729 logic wake_control_busy;
730 logic [10:0] wake_events_qs;
731 logic wake_events_busy;
732 logic fifo_ctrl_we;
733 logic fifo_ctrl_avout_rst_wd;
734 logic fifo_ctrl_avsetup_rst_wd;
735 logic fifo_ctrl_rx_rst_wd;
736 logic count_out_re;
737 logic count_out_we;
738 logic [7:0] count_out_count_qs;
739 logic count_out_datatog_out_qs;
740 logic count_out_datatog_out_wd;
741 logic count_out_drop_rx_qs;
742 logic count_out_drop_rx_wd;
743 logic count_out_drop_avout_qs;
744 logic count_out_drop_avout_wd;
745 logic count_out_ign_avsetup_qs;
746 logic count_out_ign_avsetup_wd;
747 logic [11:0] count_out_endpoints_qs;
748 logic [11:0] count_out_endpoints_wd;
749 logic count_out_rst_wd;
750 logic count_in_re;
751 logic count_in_we;
752 logic [7:0] count_in_count_qs;
753 logic count_in_nodata_qs;
754 logic count_in_nodata_wd;
755 logic count_in_nak_qs;
756 logic count_in_nak_wd;
757 logic count_in_timeout_qs;
758 logic count_in_timeout_wd;
759 logic [11:0] count_in_endpoints_qs;
760 logic [11:0] count_in_endpoints_wd;
761 logic count_in_rst_wd;
762 logic count_nodata_in_re;
763 logic count_nodata_in_we;
764 logic [7:0] count_nodata_in_count_qs;
765 logic [11:0] count_nodata_in_endpoints_qs;
766 logic [11:0] count_nodata_in_endpoints_wd;
767 logic count_nodata_in_rst_wd;
768 logic count_errors_re;
769 logic count_errors_we;
770 logic [7:0] count_errors_count_qs;
771 logic count_errors_pid_invalid_qs;
772 logic count_errors_pid_invalid_wd;
773 logic count_errors_bitstuff_qs;
774 logic count_errors_bitstuff_wd;
775 logic count_errors_crc16_qs;
776 logic count_errors_crc16_wd;
777 logic count_errors_crc5_qs;
778 logic count_errors_crc5_wd;
779 logic count_errors_rst_wd;
780 // Define register CDC handling.
781 // CDC handling is done on a per-reg instead of per-field boundary.
782
783 logic [1:0] aon_wake_control_qs;
784 logic [1:0] aon_wake_control_wdata;
785 logic aon_wake_control_we;
786 logic unused_aon_wake_control_wdata;
787
788 always_comb begin
789 0/1 ==> aon_wake_control_qs = 2'h0;
790 end
791
792 prim_reg_cdc #(
793 .DataWidth(2),
794 .ResetVal(2'h0),
795 .BitMask(2'h3),
796 .DstWrReq(0)
797 ) u_wake_control_cdc (
798 .clk_src_i (clk_i),
799 .rst_src_ni (rst_ni),
800 .clk_dst_i (clk_aon_i),
801 .rst_dst_ni (rst_aon_ni),
802 .src_regwen_i ('0),
803 .src_we_i (wake_control_we),
804 .src_re_i ('0),
805 .src_wd_i (reg_wdata[1:0]),
806 .src_busy_o (wake_control_busy),
807 .src_qs_o (wake_control_qs), // for software read back
808 .dst_update_i ('0),
809 .dst_ds_i ('0),
810 .dst_qs_i (aon_wake_control_qs),
811 .dst_we_o (aon_wake_control_we),
812 .dst_re_o (),
813 .dst_regwen_o (),
814 .dst_wd_o (aon_wake_control_wdata)
815 );
816 1/1 assign unused_aon_wake_control_wdata =
Tests: T1 T2 T3
817 ^aon_wake_control_wdata;
818
819 logic aon_wake_events_module_active_ds_int;
820 logic aon_wake_events_module_active_qs_int;
821 logic aon_wake_events_disconnected_ds_int;
822 logic aon_wake_events_disconnected_qs_int;
823 logic aon_wake_events_bus_reset_ds_int;
824 logic aon_wake_events_bus_reset_qs_int;
825 logic aon_wake_events_bus_not_idle_ds_int;
826 logic aon_wake_events_bus_not_idle_qs_int;
827 logic [10:0] aon_wake_events_ds;
828 logic aon_wake_events_qe;
829 logic [10:0] aon_wake_events_qs;
830
831 always_comb begin
832 1/1 aon_wake_events_qs = 11'h0;
Tests: T7 T8 T9
833 1/1 aon_wake_events_ds = 11'h0;
Tests: T7 T8 T9
834 1/1 aon_wake_events_ds[0] = aon_wake_events_module_active_ds_int;
Tests: T7 T8 T9
835 1/1 aon_wake_events_qs[0] = aon_wake_events_module_active_qs_int;
Tests: T7 T8 T9
836 1/1 aon_wake_events_ds[8] = aon_wake_events_disconnected_ds_int;
Tests: T7 T8 T9
837 1/1 aon_wake_events_qs[8] = aon_wake_events_disconnected_qs_int;
Tests: T7 T8 T9
838 1/1 aon_wake_events_ds[9] = aon_wake_events_bus_reset_ds_int;
Tests: T7 T8 T9
839 1/1 aon_wake_events_qs[9] = aon_wake_events_bus_reset_qs_int;
Tests: T7 T8 T9
840 1/1 aon_wake_events_ds[10] = aon_wake_events_bus_not_idle_ds_int;
Tests: T7 T8 T9
841 1/1 aon_wake_events_qs[10] = aon_wake_events_bus_not_idle_qs_int;
Tests: T7 T8 T9
842 end
843
844 prim_reg_cdc #(
845 .DataWidth(11),
846 .ResetVal(11'h0),
847 .BitMask(11'h701),
848 .DstWrReq(1)
849 ) u_wake_events_cdc (
850 .clk_src_i (clk_i),
851 .rst_src_ni (rst_ni),
852 .clk_dst_i (clk_aon_i),
853 .rst_dst_ni (rst_aon_ni),
854 .src_regwen_i ('0),
855 .src_we_i ('0),
856 .src_re_i ('0),
857 .src_wd_i ('0),
858 .src_busy_o (wake_events_busy),
859 .src_qs_o (wake_events_qs), // for software read back
860 .dst_update_i (aon_wake_events_qe),
861 .dst_ds_i (aon_wake_events_ds),
862 .dst_qs_i (aon_wake_events_qs),
863 .dst_we_o (),
864 .dst_re_o (),
865 .dst_regwen_o (),
866 .dst_wd_o ()
867 );
868
869 // Register instances
870 // R[intr_state]: V(False)
871 // F[pkt_received]: 0:0
872 prim_subreg #(
873 .DW (1),
874 .SwAccess(prim_subreg_pkg::SwAccessRO),
875 .RESVAL (1'h0),
876 .Mubi (1'b0)
877 ) u_intr_state_pkt_received (
878 .clk_i (clk_i),
879 .rst_ni (rst_ni),
880
881 // from register interface
882 .we (1'b0),
883 .wd ('0),
884
885 // from internal hardware
886 .de (hw2reg.intr_state.pkt_received.de),
887 .d (hw2reg.intr_state.pkt_received.d),
888
889 // to internal hardware
890 .qe (),
891 .q (reg2hw.intr_state.pkt_received.q),
892 .ds (),
893
894 // to register interface (read)
895 .qs (intr_state_pkt_received_qs)
896 );
897
898 // F[pkt_sent]: 1:1
899 prim_subreg #(
900 .DW (1),
901 .SwAccess(prim_subreg_pkg::SwAccessRO),
902 .RESVAL (1'h0),
903 .Mubi (1'b0)
904 ) u_intr_state_pkt_sent (
905 .clk_i (clk_i),
906 .rst_ni (rst_ni),
907
908 // from register interface
909 .we (1'b0),
910 .wd ('0),
911
912 // from internal hardware
913 .de (hw2reg.intr_state.pkt_sent.de),
914 .d (hw2reg.intr_state.pkt_sent.d),
915
916 // to internal hardware
917 .qe (),
918 .q (reg2hw.intr_state.pkt_sent.q),
919 .ds (),
920
921 // to register interface (read)
922 .qs (intr_state_pkt_sent_qs)
923 );
924
925 // F[disconnected]: 2:2
926 prim_subreg #(
927 .DW (1),
928 .SwAccess(prim_subreg_pkg::SwAccessW1C),
929 .RESVAL (1'h0),
930 .Mubi (1'b0)
931 ) u_intr_state_disconnected (
932 .clk_i (clk_i),
933 .rst_ni (rst_ni),
934
935 // from register interface
936 .we (intr_state_we),
937 .wd (intr_state_disconnected_wd),
938
939 // from internal hardware
940 .de (hw2reg.intr_state.disconnected.de),
941 .d (hw2reg.intr_state.disconnected.d),
942
943 // to internal hardware
944 .qe (),
945 .q (reg2hw.intr_state.disconnected.q),
946 .ds (),
947
948 // to register interface (read)
949 .qs (intr_state_disconnected_qs)
950 );
951
952 // F[host_lost]: 3:3
953 prim_subreg #(
954 .DW (1),
955 .SwAccess(prim_subreg_pkg::SwAccessW1C),
956 .RESVAL (1'h0),
957 .Mubi (1'b0)
958 ) u_intr_state_host_lost (
959 .clk_i (clk_i),
960 .rst_ni (rst_ni),
961
962 // from register interface
963 .we (intr_state_we),
964 .wd (intr_state_host_lost_wd),
965
966 // from internal hardware
967 .de (hw2reg.intr_state.host_lost.de),
968 .d (hw2reg.intr_state.host_lost.d),
969
970 // to internal hardware
971 .qe (),
972 .q (reg2hw.intr_state.host_lost.q),
973 .ds (),
974
975 // to register interface (read)
976 .qs (intr_state_host_lost_qs)
977 );
978
979 // F[link_reset]: 4:4
980 prim_subreg #(
981 .DW (1),
982 .SwAccess(prim_subreg_pkg::SwAccessW1C),
983 .RESVAL (1'h0),
984 .Mubi (1'b0)
985 ) u_intr_state_link_reset (
986 .clk_i (clk_i),
987 .rst_ni (rst_ni),
988
989 // from register interface
990 .we (intr_state_we),
991 .wd (intr_state_link_reset_wd),
992
993 // from internal hardware
994 .de (hw2reg.intr_state.link_reset.de),
995 .d (hw2reg.intr_state.link_reset.d),
996
997 // to internal hardware
998 .qe (),
999 .q (reg2hw.intr_state.link_reset.q),
1000 .ds (),
1001
1002 // to register interface (read)
1003 .qs (intr_state_link_reset_qs)
1004 );
1005
1006 // F[link_suspend]: 5:5
1007 prim_subreg #(
1008 .DW (1),
1009 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1010 .RESVAL (1'h0),
1011 .Mubi (1'b0)
1012 ) u_intr_state_link_suspend (
1013 .clk_i (clk_i),
1014 .rst_ni (rst_ni),
1015
1016 // from register interface
1017 .we (intr_state_we),
1018 .wd (intr_state_link_suspend_wd),
1019
1020 // from internal hardware
1021 .de (hw2reg.intr_state.link_suspend.de),
1022 .d (hw2reg.intr_state.link_suspend.d),
1023
1024 // to internal hardware
1025 .qe (),
1026 .q (reg2hw.intr_state.link_suspend.q),
1027 .ds (),
1028
1029 // to register interface (read)
1030 .qs (intr_state_link_suspend_qs)
1031 );
1032
1033 // F[link_resume]: 6:6
1034 prim_subreg #(
1035 .DW (1),
1036 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1037 .RESVAL (1'h0),
1038 .Mubi (1'b0)
1039 ) u_intr_state_link_resume (
1040 .clk_i (clk_i),
1041 .rst_ni (rst_ni),
1042
1043 // from register interface
1044 .we (intr_state_we),
1045 .wd (intr_state_link_resume_wd),
1046
1047 // from internal hardware
1048 .de (hw2reg.intr_state.link_resume.de),
1049 .d (hw2reg.intr_state.link_resume.d),
1050
1051 // to internal hardware
1052 .qe (),
1053 .q (reg2hw.intr_state.link_resume.q),
1054 .ds (),
1055
1056 // to register interface (read)
1057 .qs (intr_state_link_resume_qs)
1058 );
1059
1060 // F[av_out_empty]: 7:7
1061 prim_subreg #(
1062 .DW (1),
1063 .SwAccess(prim_subreg_pkg::SwAccessRO),
1064 .RESVAL (1'h0),
1065 .Mubi (1'b0)
1066 ) u_intr_state_av_out_empty (
1067 .clk_i (clk_i),
1068 .rst_ni (rst_ni),
1069
1070 // from register interface
1071 .we (1'b0),
1072 .wd ('0),
1073
1074 // from internal hardware
1075 .de (hw2reg.intr_state.av_out_empty.de),
1076 .d (hw2reg.intr_state.av_out_empty.d),
1077
1078 // to internal hardware
1079 .qe (),
1080 .q (reg2hw.intr_state.av_out_empty.q),
1081 .ds (),
1082
1083 // to register interface (read)
1084 .qs (intr_state_av_out_empty_qs)
1085 );
1086
1087 // F[rx_full]: 8:8
1088 prim_subreg #(
1089 .DW (1),
1090 .SwAccess(prim_subreg_pkg::SwAccessRO),
1091 .RESVAL (1'h0),
1092 .Mubi (1'b0)
1093 ) u_intr_state_rx_full (
1094 .clk_i (clk_i),
1095 .rst_ni (rst_ni),
1096
1097 // from register interface
1098 .we (1'b0),
1099 .wd ('0),
1100
1101 // from internal hardware
1102 .de (hw2reg.intr_state.rx_full.de),
1103 .d (hw2reg.intr_state.rx_full.d),
1104
1105 // to internal hardware
1106 .qe (),
1107 .q (reg2hw.intr_state.rx_full.q),
1108 .ds (),
1109
1110 // to register interface (read)
1111 .qs (intr_state_rx_full_qs)
1112 );
1113
1114 // F[av_overflow]: 9:9
1115 prim_subreg #(
1116 .DW (1),
1117 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1118 .RESVAL (1'h0),
1119 .Mubi (1'b0)
1120 ) u_intr_state_av_overflow (
1121 .clk_i (clk_i),
1122 .rst_ni (rst_ni),
1123
1124 // from register interface
1125 .we (intr_state_we),
1126 .wd (intr_state_av_overflow_wd),
1127
1128 // from internal hardware
1129 .de (hw2reg.intr_state.av_overflow.de),
1130 .d (hw2reg.intr_state.av_overflow.d),
1131
1132 // to internal hardware
1133 .qe (),
1134 .q (reg2hw.intr_state.av_overflow.q),
1135 .ds (),
1136
1137 // to register interface (read)
1138 .qs (intr_state_av_overflow_qs)
1139 );
1140
1141 // F[link_in_err]: 10:10
1142 prim_subreg #(
1143 .DW (1),
1144 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1145 .RESVAL (1'h0),
1146 .Mubi (1'b0)
1147 ) u_intr_state_link_in_err (
1148 .clk_i (clk_i),
1149 .rst_ni (rst_ni),
1150
1151 // from register interface
1152 .we (intr_state_we),
1153 .wd (intr_state_link_in_err_wd),
1154
1155 // from internal hardware
1156 .de (hw2reg.intr_state.link_in_err.de),
1157 .d (hw2reg.intr_state.link_in_err.d),
1158
1159 // to internal hardware
1160 .qe (),
1161 .q (reg2hw.intr_state.link_in_err.q),
1162 .ds (),
1163
1164 // to register interface (read)
1165 .qs (intr_state_link_in_err_qs)
1166 );
1167
1168 // F[rx_crc_err]: 11:11
1169 prim_subreg #(
1170 .DW (1),
1171 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1172 .RESVAL (1'h0),
1173 .Mubi (1'b0)
1174 ) u_intr_state_rx_crc_err (
1175 .clk_i (clk_i),
1176 .rst_ni (rst_ni),
1177
1178 // from register interface
1179 .we (intr_state_we),
1180 .wd (intr_state_rx_crc_err_wd),
1181
1182 // from internal hardware
1183 .de (hw2reg.intr_state.rx_crc_err.de),
1184 .d (hw2reg.intr_state.rx_crc_err.d),
1185
1186 // to internal hardware
1187 .qe (),
1188 .q (reg2hw.intr_state.rx_crc_err.q),
1189 .ds (),
1190
1191 // to register interface (read)
1192 .qs (intr_state_rx_crc_err_qs)
1193 );
1194
1195 // F[rx_pid_err]: 12:12
1196 prim_subreg #(
1197 .DW (1),
1198 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1199 .RESVAL (1'h0),
1200 .Mubi (1'b0)
1201 ) u_intr_state_rx_pid_err (
1202 .clk_i (clk_i),
1203 .rst_ni (rst_ni),
1204
1205 // from register interface
1206 .we (intr_state_we),
1207 .wd (intr_state_rx_pid_err_wd),
1208
1209 // from internal hardware
1210 .de (hw2reg.intr_state.rx_pid_err.de),
1211 .d (hw2reg.intr_state.rx_pid_err.d),
1212
1213 // to internal hardware
1214 .qe (),
1215 .q (reg2hw.intr_state.rx_pid_err.q),
1216 .ds (),
1217
1218 // to register interface (read)
1219 .qs (intr_state_rx_pid_err_qs)
1220 );
1221
1222 // F[rx_bitstuff_err]: 13:13
1223 prim_subreg #(
1224 .DW (1),
1225 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1226 .RESVAL (1'h0),
1227 .Mubi (1'b0)
1228 ) u_intr_state_rx_bitstuff_err (
1229 .clk_i (clk_i),
1230 .rst_ni (rst_ni),
1231
1232 // from register interface
1233 .we (intr_state_we),
1234 .wd (intr_state_rx_bitstuff_err_wd),
1235
1236 // from internal hardware
1237 .de (hw2reg.intr_state.rx_bitstuff_err.de),
1238 .d (hw2reg.intr_state.rx_bitstuff_err.d),
1239
1240 // to internal hardware
1241 .qe (),
1242 .q (reg2hw.intr_state.rx_bitstuff_err.q),
1243 .ds (),
1244
1245 // to register interface (read)
1246 .qs (intr_state_rx_bitstuff_err_qs)
1247 );
1248
1249 // F[frame]: 14:14
1250 prim_subreg #(
1251 .DW (1),
1252 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1253 .RESVAL (1'h0),
1254 .Mubi (1'b0)
1255 ) u_intr_state_frame (
1256 .clk_i (clk_i),
1257 .rst_ni (rst_ni),
1258
1259 // from register interface
1260 .we (intr_state_we),
1261 .wd (intr_state_frame_wd),
1262
1263 // from internal hardware
1264 .de (hw2reg.intr_state.frame.de),
1265 .d (hw2reg.intr_state.frame.d),
1266
1267 // to internal hardware
1268 .qe (),
1269 .q (reg2hw.intr_state.frame.q),
1270 .ds (),
1271
1272 // to register interface (read)
1273 .qs (intr_state_frame_qs)
1274 );
1275
1276 // F[powered]: 15:15
1277 prim_subreg #(
1278 .DW (1),
1279 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1280 .RESVAL (1'h0),
1281 .Mubi (1'b0)
1282 ) u_intr_state_powered (
1283 .clk_i (clk_i),
1284 .rst_ni (rst_ni),
1285
1286 // from register interface
1287 .we (intr_state_we),
1288 .wd (intr_state_powered_wd),
1289
1290 // from internal hardware
1291 .de (hw2reg.intr_state.powered.de),
1292 .d (hw2reg.intr_state.powered.d),
1293
1294 // to internal hardware
1295 .qe (),
1296 .q (reg2hw.intr_state.powered.q),
1297 .ds (),
1298
1299 // to register interface (read)
1300 .qs (intr_state_powered_qs)
1301 );
1302
1303 // F[link_out_err]: 16:16
1304 prim_subreg #(
1305 .DW (1),
1306 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1307 .RESVAL (1'h0),
1308 .Mubi (1'b0)
1309 ) u_intr_state_link_out_err (
1310 .clk_i (clk_i),
1311 .rst_ni (rst_ni),
1312
1313 // from register interface
1314 .we (intr_state_we),
1315 .wd (intr_state_link_out_err_wd),
1316
1317 // from internal hardware
1318 .de (hw2reg.intr_state.link_out_err.de),
1319 .d (hw2reg.intr_state.link_out_err.d),
1320
1321 // to internal hardware
1322 .qe (),
1323 .q (reg2hw.intr_state.link_out_err.q),
1324 .ds (),
1325
1326 // to register interface (read)
1327 .qs (intr_state_link_out_err_qs)
1328 );
1329
1330 // F[av_setup_empty]: 17:17
1331 prim_subreg #(
1332 .DW (1),
1333 .SwAccess(prim_subreg_pkg::SwAccessRO),
1334 .RESVAL (1'h0),
1335 .Mubi (1'b0)
1336 ) u_intr_state_av_setup_empty (
1337 .clk_i (clk_i),
1338 .rst_ni (rst_ni),
1339
1340 // from register interface
1341 .we (1'b0),
1342 .wd ('0),
1343
1344 // from internal hardware
1345 .de (hw2reg.intr_state.av_setup_empty.de),
1346 .d (hw2reg.intr_state.av_setup_empty.d),
1347
1348 // to internal hardware
1349 .qe (),
1350 .q (reg2hw.intr_state.av_setup_empty.q),
1351 .ds (),
1352
1353 // to register interface (read)
1354 .qs (intr_state_av_setup_empty_qs)
1355 );
1356
1357
1358 // R[intr_enable]: V(False)
1359 // F[pkt_received]: 0:0
1360 prim_subreg #(
1361 .DW (1),
1362 .SwAccess(prim_subreg_pkg::SwAccessRW),
1363 .RESVAL (1'h0),
1364 .Mubi (1'b0)
1365 ) u_intr_enable_pkt_received (
1366 .clk_i (clk_i),
1367 .rst_ni (rst_ni),
1368
1369 // from register interface
1370 .we (intr_enable_we),
1371 .wd (intr_enable_pkt_received_wd),
1372
1373 // from internal hardware
1374 .de (1'b0),
1375 .d ('0),
1376
1377 // to internal hardware
1378 .qe (),
1379 .q (reg2hw.intr_enable.pkt_received.q),
1380 .ds (),
1381
1382 // to register interface (read)
1383 .qs (intr_enable_pkt_received_qs)
1384 );
1385
1386 // F[pkt_sent]: 1:1
1387 prim_subreg #(
1388 .DW (1),
1389 .SwAccess(prim_subreg_pkg::SwAccessRW),
1390 .RESVAL (1'h0),
1391 .Mubi (1'b0)
1392 ) u_intr_enable_pkt_sent (
1393 .clk_i (clk_i),
1394 .rst_ni (rst_ni),
1395
1396 // from register interface
1397 .we (intr_enable_we),
1398 .wd (intr_enable_pkt_sent_wd),
1399
1400 // from internal hardware
1401 .de (1'b0),
1402 .d ('0),
1403
1404 // to internal hardware
1405 .qe (),
1406 .q (reg2hw.intr_enable.pkt_sent.q),
1407 .ds (),
1408
1409 // to register interface (read)
1410 .qs (intr_enable_pkt_sent_qs)
1411 );
1412
1413 // F[disconnected]: 2:2
1414 prim_subreg #(
1415 .DW (1),
1416 .SwAccess(prim_subreg_pkg::SwAccessRW),
1417 .RESVAL (1'h0),
1418 .Mubi (1'b0)
1419 ) u_intr_enable_disconnected (
1420 .clk_i (clk_i),
1421 .rst_ni (rst_ni),
1422
1423 // from register interface
1424 .we (intr_enable_we),
1425 .wd (intr_enable_disconnected_wd),
1426
1427 // from internal hardware
1428 .de (1'b0),
1429 .d ('0),
1430
1431 // to internal hardware
1432 .qe (),
1433 .q (reg2hw.intr_enable.disconnected.q),
1434 .ds (),
1435
1436 // to register interface (read)
1437 .qs (intr_enable_disconnected_qs)
1438 );
1439
1440 // F[host_lost]: 3:3
1441 prim_subreg #(
1442 .DW (1),
1443 .SwAccess(prim_subreg_pkg::SwAccessRW),
1444 .RESVAL (1'h0),
1445 .Mubi (1'b0)
1446 ) u_intr_enable_host_lost (
1447 .clk_i (clk_i),
1448 .rst_ni (rst_ni),
1449
1450 // from register interface
1451 .we (intr_enable_we),
1452 .wd (intr_enable_host_lost_wd),
1453
1454 // from internal hardware
1455 .de (1'b0),
1456 .d ('0),
1457
1458 // to internal hardware
1459 .qe (),
1460 .q (reg2hw.intr_enable.host_lost.q),
1461 .ds (),
1462
1463 // to register interface (read)
1464 .qs (intr_enable_host_lost_qs)
1465 );
1466
1467 // F[link_reset]: 4:4
1468 prim_subreg #(
1469 .DW (1),
1470 .SwAccess(prim_subreg_pkg::SwAccessRW),
1471 .RESVAL (1'h0),
1472 .Mubi (1'b0)
1473 ) u_intr_enable_link_reset (
1474 .clk_i (clk_i),
1475 .rst_ni (rst_ni),
1476
1477 // from register interface
1478 .we (intr_enable_we),
1479 .wd (intr_enable_link_reset_wd),
1480
1481 // from internal hardware
1482 .de (1'b0),
1483 .d ('0),
1484
1485 // to internal hardware
1486 .qe (),
1487 .q (reg2hw.intr_enable.link_reset.q),
1488 .ds (),
1489
1490 // to register interface (read)
1491 .qs (intr_enable_link_reset_qs)
1492 );
1493
1494 // F[link_suspend]: 5:5
1495 prim_subreg #(
1496 .DW (1),
1497 .SwAccess(prim_subreg_pkg::SwAccessRW),
1498 .RESVAL (1'h0),
1499 .Mubi (1'b0)
1500 ) u_intr_enable_link_suspend (
1501 .clk_i (clk_i),
1502 .rst_ni (rst_ni),
1503
1504 // from register interface
1505 .we (intr_enable_we),
1506 .wd (intr_enable_link_suspend_wd),
1507
1508 // from internal hardware
1509 .de (1'b0),
1510 .d ('0),
1511
1512 // to internal hardware
1513 .qe (),
1514 .q (reg2hw.intr_enable.link_suspend.q),
1515 .ds (),
1516
1517 // to register interface (read)
1518 .qs (intr_enable_link_suspend_qs)
1519 );
1520
1521 // F[link_resume]: 6:6
1522 prim_subreg #(
1523 .DW (1),
1524 .SwAccess(prim_subreg_pkg::SwAccessRW),
1525 .RESVAL (1'h0),
1526 .Mubi (1'b0)
1527 ) u_intr_enable_link_resume (
1528 .clk_i (clk_i),
1529 .rst_ni (rst_ni),
1530
1531 // from register interface
1532 .we (intr_enable_we),
1533 .wd (intr_enable_link_resume_wd),
1534
1535 // from internal hardware
1536 .de (1'b0),
1537 .d ('0),
1538
1539 // to internal hardware
1540 .qe (),
1541 .q (reg2hw.intr_enable.link_resume.q),
1542 .ds (),
1543
1544 // to register interface (read)
1545 .qs (intr_enable_link_resume_qs)
1546 );
1547
1548 // F[av_out_empty]: 7:7
1549 prim_subreg #(
1550 .DW (1),
1551 .SwAccess(prim_subreg_pkg::SwAccessRW),
1552 .RESVAL (1'h0),
1553 .Mubi (1'b0)
1554 ) u_intr_enable_av_out_empty (
1555 .clk_i (clk_i),
1556 .rst_ni (rst_ni),
1557
1558 // from register interface
1559 .we (intr_enable_we),
1560 .wd (intr_enable_av_out_empty_wd),
1561
1562 // from internal hardware
1563 .de (1'b0),
1564 .d ('0),
1565
1566 // to internal hardware
1567 .qe (),
1568 .q (reg2hw.intr_enable.av_out_empty.q),
1569 .ds (),
1570
1571 // to register interface (read)
1572 .qs (intr_enable_av_out_empty_qs)
1573 );
1574
1575 // F[rx_full]: 8:8
1576 prim_subreg #(
1577 .DW (1),
1578 .SwAccess(prim_subreg_pkg::SwAccessRW),
1579 .RESVAL (1'h0),
1580 .Mubi (1'b0)
1581 ) u_intr_enable_rx_full (
1582 .clk_i (clk_i),
1583 .rst_ni (rst_ni),
1584
1585 // from register interface
1586 .we (intr_enable_we),
1587 .wd (intr_enable_rx_full_wd),
1588
1589 // from internal hardware
1590 .de (1'b0),
1591 .d ('0),
1592
1593 // to internal hardware
1594 .qe (),
1595 .q (reg2hw.intr_enable.rx_full.q),
1596 .ds (),
1597
1598 // to register interface (read)
1599 .qs (intr_enable_rx_full_qs)
1600 );
1601
1602 // F[av_overflow]: 9:9
1603 prim_subreg #(
1604 .DW (1),
1605 .SwAccess(prim_subreg_pkg::SwAccessRW),
1606 .RESVAL (1'h0),
1607 .Mubi (1'b0)
1608 ) u_intr_enable_av_overflow (
1609 .clk_i (clk_i),
1610 .rst_ni (rst_ni),
1611
1612 // from register interface
1613 .we (intr_enable_we),
1614 .wd (intr_enable_av_overflow_wd),
1615
1616 // from internal hardware
1617 .de (1'b0),
1618 .d ('0),
1619
1620 // to internal hardware
1621 .qe (),
1622 .q (reg2hw.intr_enable.av_overflow.q),
1623 .ds (),
1624
1625 // to register interface (read)
1626 .qs (intr_enable_av_overflow_qs)
1627 );
1628
1629 // F[link_in_err]: 10:10
1630 prim_subreg #(
1631 .DW (1),
1632 .SwAccess(prim_subreg_pkg::SwAccessRW),
1633 .RESVAL (1'h0),
1634 .Mubi (1'b0)
1635 ) u_intr_enable_link_in_err (
1636 .clk_i (clk_i),
1637 .rst_ni (rst_ni),
1638
1639 // from register interface
1640 .we (intr_enable_we),
1641 .wd (intr_enable_link_in_err_wd),
1642
1643 // from internal hardware
1644 .de (1'b0),
1645 .d ('0),
1646
1647 // to internal hardware
1648 .qe (),
1649 .q (reg2hw.intr_enable.link_in_err.q),
1650 .ds (),
1651
1652 // to register interface (read)
1653 .qs (intr_enable_link_in_err_qs)
1654 );
1655
1656 // F[rx_crc_err]: 11:11
1657 prim_subreg #(
1658 .DW (1),
1659 .SwAccess(prim_subreg_pkg::SwAccessRW),
1660 .RESVAL (1'h0),
1661 .Mubi (1'b0)
1662 ) u_intr_enable_rx_crc_err (
1663 .clk_i (clk_i),
1664 .rst_ni (rst_ni),
1665
1666 // from register interface
1667 .we (intr_enable_we),
1668 .wd (intr_enable_rx_crc_err_wd),
1669
1670 // from internal hardware
1671 .de (1'b0),
1672 .d ('0),
1673
1674 // to internal hardware
1675 .qe (),
1676 .q (reg2hw.intr_enable.rx_crc_err.q),
1677 .ds (),
1678
1679 // to register interface (read)
1680 .qs (intr_enable_rx_crc_err_qs)
1681 );
1682
1683 // F[rx_pid_err]: 12:12
1684 prim_subreg #(
1685 .DW (1),
1686 .SwAccess(prim_subreg_pkg::SwAccessRW),
1687 .RESVAL (1'h0),
1688 .Mubi (1'b0)
1689 ) u_intr_enable_rx_pid_err (
1690 .clk_i (clk_i),
1691 .rst_ni (rst_ni),
1692
1693 // from register interface
1694 .we (intr_enable_we),
1695 .wd (intr_enable_rx_pid_err_wd),
1696
1697 // from internal hardware
1698 .de (1'b0),
1699 .d ('0),
1700
1701 // to internal hardware
1702 .qe (),
1703 .q (reg2hw.intr_enable.rx_pid_err.q),
1704 .ds (),
1705
1706 // to register interface (read)
1707 .qs (intr_enable_rx_pid_err_qs)
1708 );
1709
1710 // F[rx_bitstuff_err]: 13:13
1711 prim_subreg #(
1712 .DW (1),
1713 .SwAccess(prim_subreg_pkg::SwAccessRW),
1714 .RESVAL (1'h0),
1715 .Mubi (1'b0)
1716 ) u_intr_enable_rx_bitstuff_err (
1717 .clk_i (clk_i),
1718 .rst_ni (rst_ni),
1719
1720 // from register interface
1721 .we (intr_enable_we),
1722 .wd (intr_enable_rx_bitstuff_err_wd),
1723
1724 // from internal hardware
1725 .de (1'b0),
1726 .d ('0),
1727
1728 // to internal hardware
1729 .qe (),
1730 .q (reg2hw.intr_enable.rx_bitstuff_err.q),
1731 .ds (),
1732
1733 // to register interface (read)
1734 .qs (intr_enable_rx_bitstuff_err_qs)
1735 );
1736
1737 // F[frame]: 14:14
1738 prim_subreg #(
1739 .DW (1),
1740 .SwAccess(prim_subreg_pkg::SwAccessRW),
1741 .RESVAL (1'h0),
1742 .Mubi (1'b0)
1743 ) u_intr_enable_frame (
1744 .clk_i (clk_i),
1745 .rst_ni (rst_ni),
1746
1747 // from register interface
1748 .we (intr_enable_we),
1749 .wd (intr_enable_frame_wd),
1750
1751 // from internal hardware
1752 .de (1'b0),
1753 .d ('0),
1754
1755 // to internal hardware
1756 .qe (),
1757 .q (reg2hw.intr_enable.frame.q),
1758 .ds (),
1759
1760 // to register interface (read)
1761 .qs (intr_enable_frame_qs)
1762 );
1763
1764 // F[powered]: 15:15
1765 prim_subreg #(
1766 .DW (1),
1767 .SwAccess(prim_subreg_pkg::SwAccessRW),
1768 .RESVAL (1'h0),
1769 .Mubi (1'b0)
1770 ) u_intr_enable_powered (
1771 .clk_i (clk_i),
1772 .rst_ni (rst_ni),
1773
1774 // from register interface
1775 .we (intr_enable_we),
1776 .wd (intr_enable_powered_wd),
1777
1778 // from internal hardware
1779 .de (1'b0),
1780 .d ('0),
1781
1782 // to internal hardware
1783 .qe (),
1784 .q (reg2hw.intr_enable.powered.q),
1785 .ds (),
1786
1787 // to register interface (read)
1788 .qs (intr_enable_powered_qs)
1789 );
1790
1791 // F[link_out_err]: 16:16
1792 prim_subreg #(
1793 .DW (1),
1794 .SwAccess(prim_subreg_pkg::SwAccessRW),
1795 .RESVAL (1'h0),
1796 .Mubi (1'b0)
1797 ) u_intr_enable_link_out_err (
1798 .clk_i (clk_i),
1799 .rst_ni (rst_ni),
1800
1801 // from register interface
1802 .we (intr_enable_we),
1803 .wd (intr_enable_link_out_err_wd),
1804
1805 // from internal hardware
1806 .de (1'b0),
1807 .d ('0),
1808
1809 // to internal hardware
1810 .qe (),
1811 .q (reg2hw.intr_enable.link_out_err.q),
1812 .ds (),
1813
1814 // to register interface (read)
1815 .qs (intr_enable_link_out_err_qs)
1816 );
1817
1818 // F[av_setup_empty]: 17:17
1819 prim_subreg #(
1820 .DW (1),
1821 .SwAccess(prim_subreg_pkg::SwAccessRW),
1822 .RESVAL (1'h0),
1823 .Mubi (1'b0)
1824 ) u_intr_enable_av_setup_empty (
1825 .clk_i (clk_i),
1826 .rst_ni (rst_ni),
1827
1828 // from register interface
1829 .we (intr_enable_we),
1830 .wd (intr_enable_av_setup_empty_wd),
1831
1832 // from internal hardware
1833 .de (1'b0),
1834 .d ('0),
1835
1836 // to internal hardware
1837 .qe (),
1838 .q (reg2hw.intr_enable.av_setup_empty.q),
1839 .ds (),
1840
1841 // to register interface (read)
1842 .qs (intr_enable_av_setup_empty_qs)
1843 );
1844
1845
1846 // R[intr_test]: V(True)
1847 logic intr_test_qe;
1848 logic [17:0] intr_test_flds_we;
1849 1/1 assign intr_test_qe = &intr_test_flds_we;
Tests: T262 T261 T249
1850 // F[pkt_received]: 0:0
1851 prim_subreg_ext #(
1852 .DW (1)
1853 ) u_intr_test_pkt_received (
1854 .re (1'b0),
1855 .we (intr_test_we),
1856 .wd (intr_test_pkt_received_wd),
1857 .d ('0),
1858 .qre (),
1859 .qe (intr_test_flds_we[0]),
1860 .q (reg2hw.intr_test.pkt_received.q),
1861 .ds (),
1862 .qs ()
1863 );
1864 1/1 assign reg2hw.intr_test.pkt_received.qe = intr_test_qe;
Tests: T262 T261 T249
1865
1866 // F[pkt_sent]: 1:1
1867 prim_subreg_ext #(
1868 .DW (1)
1869 ) u_intr_test_pkt_sent (
1870 .re (1'b0),
1871 .we (intr_test_we),
1872 .wd (intr_test_pkt_sent_wd),
1873 .d ('0),
1874 .qre (),
1875 .qe (intr_test_flds_we[1]),
1876 .q (reg2hw.intr_test.pkt_sent.q),
1877 .ds (),
1878 .qs ()
1879 );
1880 1/1 assign reg2hw.intr_test.pkt_sent.qe = intr_test_qe;
Tests: T262 T261 T249
1881
1882 // F[disconnected]: 2:2
1883 prim_subreg_ext #(
1884 .DW (1)
1885 ) u_intr_test_disconnected (
1886 .re (1'b0),
1887 .we (intr_test_we),
1888 .wd (intr_test_disconnected_wd),
1889 .d ('0),
1890 .qre (),
1891 .qe (intr_test_flds_we[2]),
1892 .q (reg2hw.intr_test.disconnected.q),
1893 .ds (),
1894 .qs ()
1895 );
1896 1/1 assign reg2hw.intr_test.disconnected.qe = intr_test_qe;
Tests: T262 T261 T249
1897
1898 // F[host_lost]: 3:3
1899 prim_subreg_ext #(
1900 .DW (1)
1901 ) u_intr_test_host_lost (
1902 .re (1'b0),
1903 .we (intr_test_we),
1904 .wd (intr_test_host_lost_wd),
1905 .d ('0),
1906 .qre (),
1907 .qe (intr_test_flds_we[3]),
1908 .q (reg2hw.intr_test.host_lost.q),
1909 .ds (),
1910 .qs ()
1911 );
1912 1/1 assign reg2hw.intr_test.host_lost.qe = intr_test_qe;
Tests: T262 T261 T249
1913
1914 // F[link_reset]: 4:4
1915 prim_subreg_ext #(
1916 .DW (1)
1917 ) u_intr_test_link_reset (
1918 .re (1'b0),
1919 .we (intr_test_we),
1920 .wd (intr_test_link_reset_wd),
1921 .d ('0),
1922 .qre (),
1923 .qe (intr_test_flds_we[4]),
1924 .q (reg2hw.intr_test.link_reset.q),
1925 .ds (),
1926 .qs ()
1927 );
1928 1/1 assign reg2hw.intr_test.link_reset.qe = intr_test_qe;
Tests: T262 T261 T249
1929
1930 // F[link_suspend]: 5:5
1931 prim_subreg_ext #(
1932 .DW (1)
1933 ) u_intr_test_link_suspend (
1934 .re (1'b0),
1935 .we (intr_test_we),
1936 .wd (intr_test_link_suspend_wd),
1937 .d ('0),
1938 .qre (),
1939 .qe (intr_test_flds_we[5]),
1940 .q (reg2hw.intr_test.link_suspend.q),
1941 .ds (),
1942 .qs ()
1943 );
1944 1/1 assign reg2hw.intr_test.link_suspend.qe = intr_test_qe;
Tests: T262 T261 T249
1945
1946 // F[link_resume]: 6:6
1947 prim_subreg_ext #(
1948 .DW (1)
1949 ) u_intr_test_link_resume (
1950 .re (1'b0),
1951 .we (intr_test_we),
1952 .wd (intr_test_link_resume_wd),
1953 .d ('0),
1954 .qre (),
1955 .qe (intr_test_flds_we[6]),
1956 .q (reg2hw.intr_test.link_resume.q),
1957 .ds (),
1958 .qs ()
1959 );
1960 1/1 assign reg2hw.intr_test.link_resume.qe = intr_test_qe;
Tests: T262 T261 T249
1961
1962 // F[av_out_empty]: 7:7
1963 prim_subreg_ext #(
1964 .DW (1)
1965 ) u_intr_test_av_out_empty (
1966 .re (1'b0),
1967 .we (intr_test_we),
1968 .wd (intr_test_av_out_empty_wd),
1969 .d ('0),
1970 .qre (),
1971 .qe (intr_test_flds_we[7]),
1972 .q (reg2hw.intr_test.av_out_empty.q),
1973 .ds (),
1974 .qs ()
1975 );
1976 1/1 assign reg2hw.intr_test.av_out_empty.qe = intr_test_qe;
Tests: T262 T261 T249
1977
1978 // F[rx_full]: 8:8
1979 prim_subreg_ext #(
1980 .DW (1)
1981 ) u_intr_test_rx_full (
1982 .re (1'b0),
1983 .we (intr_test_we),
1984 .wd (intr_test_rx_full_wd),
1985 .d ('0),
1986 .qre (),
1987 .qe (intr_test_flds_we[8]),
1988 .q (reg2hw.intr_test.rx_full.q),
1989 .ds (),
1990 .qs ()
1991 );
1992 1/1 assign reg2hw.intr_test.rx_full.qe = intr_test_qe;
Tests: T262 T261 T249
1993
1994 // F[av_overflow]: 9:9
1995 prim_subreg_ext #(
1996 .DW (1)
1997 ) u_intr_test_av_overflow (
1998 .re (1'b0),
1999 .we (intr_test_we),
2000 .wd (intr_test_av_overflow_wd),
2001 .d ('0),
2002 .qre (),
2003 .qe (intr_test_flds_we[9]),
2004 .q (reg2hw.intr_test.av_overflow.q),
2005 .ds (),
2006 .qs ()
2007 );
2008 1/1 assign reg2hw.intr_test.av_overflow.qe = intr_test_qe;
Tests: T262 T261 T249
2009
2010 // F[link_in_err]: 10:10
2011 prim_subreg_ext #(
2012 .DW (1)
2013 ) u_intr_test_link_in_err (
2014 .re (1'b0),
2015 .we (intr_test_we),
2016 .wd (intr_test_link_in_err_wd),
2017 .d ('0),
2018 .qre (),
2019 .qe (intr_test_flds_we[10]),
2020 .q (reg2hw.intr_test.link_in_err.q),
2021 .ds (),
2022 .qs ()
2023 );
2024 1/1 assign reg2hw.intr_test.link_in_err.qe = intr_test_qe;
Tests: T262 T261 T249
2025
2026 // F[rx_crc_err]: 11:11
2027 prim_subreg_ext #(
2028 .DW (1)
2029 ) u_intr_test_rx_crc_err (
2030 .re (1'b0),
2031 .we (intr_test_we),
2032 .wd (intr_test_rx_crc_err_wd),
2033 .d ('0),
2034 .qre (),
2035 .qe (intr_test_flds_we[11]),
2036 .q (reg2hw.intr_test.rx_crc_err.q),
2037 .ds (),
2038 .qs ()
2039 );
2040 1/1 assign reg2hw.intr_test.rx_crc_err.qe = intr_test_qe;
Tests: T262 T261 T249
2041
2042 // F[rx_pid_err]: 12:12
2043 prim_subreg_ext #(
2044 .DW (1)
2045 ) u_intr_test_rx_pid_err (
2046 .re (1'b0),
2047 .we (intr_test_we),
2048 .wd (intr_test_rx_pid_err_wd),
2049 .d ('0),
2050 .qre (),
2051 .qe (intr_test_flds_we[12]),
2052 .q (reg2hw.intr_test.rx_pid_err.q),
2053 .ds (),
2054 .qs ()
2055 );
2056 1/1 assign reg2hw.intr_test.rx_pid_err.qe = intr_test_qe;
Tests: T262 T261 T249
2057
2058 // F[rx_bitstuff_err]: 13:13
2059 prim_subreg_ext #(
2060 .DW (1)
2061 ) u_intr_test_rx_bitstuff_err (
2062 .re (1'b0),
2063 .we (intr_test_we),
2064 .wd (intr_test_rx_bitstuff_err_wd),
2065 .d ('0),
2066 .qre (),
2067 .qe (intr_test_flds_we[13]),
2068 .q (reg2hw.intr_test.rx_bitstuff_err.q),
2069 .ds (),
2070 .qs ()
2071 );
2072 1/1 assign reg2hw.intr_test.rx_bitstuff_err.qe = intr_test_qe;
Tests: T262 T261 T249
2073
2074 // F[frame]: 14:14
2075 prim_subreg_ext #(
2076 .DW (1)
2077 ) u_intr_test_frame (
2078 .re (1'b0),
2079 .we (intr_test_we),
2080 .wd (intr_test_frame_wd),
2081 .d ('0),
2082 .qre (),
2083 .qe (intr_test_flds_we[14]),
2084 .q (reg2hw.intr_test.frame.q),
2085 .ds (),
2086 .qs ()
2087 );
2088 1/1 assign reg2hw.intr_test.frame.qe = intr_test_qe;
Tests: T262 T261 T249
2089
2090 // F[powered]: 15:15
2091 prim_subreg_ext #(
2092 .DW (1)
2093 ) u_intr_test_powered (
2094 .re (1'b0),
2095 .we (intr_test_we),
2096 .wd (intr_test_powered_wd),
2097 .d ('0),
2098 .qre (),
2099 .qe (intr_test_flds_we[15]),
2100 .q (reg2hw.intr_test.powered.q),
2101 .ds (),
2102 .qs ()
2103 );
2104 1/1 assign reg2hw.intr_test.powered.qe = intr_test_qe;
Tests: T262 T261 T249
2105
2106 // F[link_out_err]: 16:16
2107 prim_subreg_ext #(
2108 .DW (1)
2109 ) u_intr_test_link_out_err (
2110 .re (1'b0),
2111 .we (intr_test_we),
2112 .wd (intr_test_link_out_err_wd),
2113 .d ('0),
2114 .qre (),
2115 .qe (intr_test_flds_we[16]),
2116 .q (reg2hw.intr_test.link_out_err.q),
2117 .ds (),
2118 .qs ()
2119 );
2120 1/1 assign reg2hw.intr_test.link_out_err.qe = intr_test_qe;
Tests: T262 T261 T249
2121
2122 // F[av_setup_empty]: 17:17
2123 prim_subreg_ext #(
2124 .DW (1)
2125 ) u_intr_test_av_setup_empty (
2126 .re (1'b0),
2127 .we (intr_test_we),
2128 .wd (intr_test_av_setup_empty_wd),
2129 .d ('0),
2130 .qre (),
2131 .qe (intr_test_flds_we[17]),
2132 .q (reg2hw.intr_test.av_setup_empty.q),
2133 .ds (),
2134 .qs ()
2135 );
2136 1/1 assign reg2hw.intr_test.av_setup_empty.qe = intr_test_qe;
Tests: T262 T261 T249
2137
2138
2139 // R[alert_test]: V(True)
2140 logic alert_test_qe;
2141 logic [0:0] alert_test_flds_we;
2142 1/1 assign alert_test_qe = &alert_test_flds_we;
Tests: T39 T241 T242
2143 prim_subreg_ext #(
2144 .DW (1)
2145 ) u_alert_test (
2146 .re (1'b0),
2147 .we (alert_test_we),
2148 .wd (alert_test_wd),
2149 .d ('0),
2150 .qre (),
2151 .qe (alert_test_flds_we[0]),
2152 .q (reg2hw.alert_test.q),
2153 .ds (),
2154 .qs ()
2155 );
2156 1/1 assign reg2hw.alert_test.qe = alert_test_qe;
Tests: T39 T241 T242
2157
2158
2159 // R[usbctrl]: V(False)
2160 logic usbctrl_qe;
2161 logic [2:0] usbctrl_flds_we;
2162 prim_flop #(
2163 .Width(1),
2164 .ResetValue(0)
2165 ) u_usbctrl0_qe (
2166 .clk_i(clk_i),
2167 .rst_ni(rst_ni),
2168 .d_i(&usbctrl_flds_we),
2169 .q_o(usbctrl_qe)
2170 );
2171 // F[enable]: 0:0
2172 prim_subreg #(
2173 .DW (1),
2174 .SwAccess(prim_subreg_pkg::SwAccessRW),
2175 .RESVAL (1'h0),
2176 .Mubi (1'b0)
2177 ) u_usbctrl_enable (
2178 .clk_i (clk_i),
2179 .rst_ni (rst_ni),
2180
2181 // from register interface
2182 .we (usbctrl_we),
2183 .wd (usbctrl_enable_wd),
2184
2185 // from internal hardware
2186 .de (1'b0),
2187 .d ('0),
2188
2189 // to internal hardware
2190 .qe (usbctrl_flds_we[0]),
2191 .q (reg2hw.usbctrl.enable.q),
2192 .ds (),
2193
2194 // to register interface (read)
2195 .qs (usbctrl_enable_qs)
2196 );
2197
2198 // F[resume_link_active]: 1:1
2199 prim_subreg #(
2200 .DW (1),
2201 .SwAccess(prim_subreg_pkg::SwAccessWO),
2202 .RESVAL (1'h0),
2203 .Mubi (1'b0)
2204 ) u_usbctrl_resume_link_active (
2205 .clk_i (clk_i),
2206 .rst_ni (rst_ni),
2207
2208 // from register interface
2209 .we (usbctrl_we),
2210 .wd (usbctrl_resume_link_active_wd),
2211
2212 // from internal hardware
2213 .de (1'b0),
2214 .d ('0),
2215
2216 // to internal hardware
2217 .qe (usbctrl_flds_we[1]),
2218 .q (reg2hw.usbctrl.resume_link_active.q),
2219 .ds (),
2220
2221 // to register interface (read)
2222 .qs ()
2223 );
2224 1/1 assign reg2hw.usbctrl.resume_link_active.qe = usbctrl_qe;
Tests: T1 T2 T3
2225
2226 // F[device_address]: 22:16
2227 prim_subreg #(
2228 .DW (7),
2229 .SwAccess(prim_subreg_pkg::SwAccessRW),
2230 .RESVAL (7'h0),
2231 .Mubi (1'b0)
2232 ) u_usbctrl_device_address (
2233 .clk_i (clk_i),
2234 .rst_ni (rst_ni),
2235
2236 // from register interface
2237 .we (usbctrl_we),
2238 .wd (usbctrl_device_address_wd),
2239
2240 // from internal hardware
2241 .de (hw2reg.usbctrl.device_address.de),
2242 .d (hw2reg.usbctrl.device_address.d),
2243
2244 // to internal hardware
2245 .qe (usbctrl_flds_we[2]),
2246 .q (reg2hw.usbctrl.device_address.q),
2247 .ds (),
2248
2249 // to register interface (read)
2250 .qs (usbctrl_device_address_qs)
2251 );
2252
2253
2254 // Subregister 0 of Multireg ep_out_enable
2255 // R[ep_out_enable]: V(False)
2256 // F[enable_0]: 0:0
2257 prim_subreg #(
2258 .DW (1),
2259 .SwAccess(prim_subreg_pkg::SwAccessRW),
2260 .RESVAL (1'h0),
2261 .Mubi (1'b0)
2262 ) u_ep_out_enable_enable_0 (
2263 .clk_i (clk_i),
2264 .rst_ni (rst_ni),
2265
2266 // from register interface
2267 .we (ep_out_enable_we),
2268 .wd (ep_out_enable_enable_0_wd),
2269
2270 // from internal hardware
2271 .de (1'b0),
2272 .d ('0),
2273
2274 // to internal hardware
2275 .qe (),
2276 .q (reg2hw.ep_out_enable[0].q),
2277 .ds (),
2278
2279 // to register interface (read)
2280 .qs (ep_out_enable_enable_0_qs)
2281 );
2282
2283 // F[enable_1]: 1:1
2284 prim_subreg #(
2285 .DW (1),
2286 .SwAccess(prim_subreg_pkg::SwAccessRW),
2287 .RESVAL (1'h0),
2288 .Mubi (1'b0)
2289 ) u_ep_out_enable_enable_1 (
2290 .clk_i (clk_i),
2291 .rst_ni (rst_ni),
2292
2293 // from register interface
2294 .we (ep_out_enable_we),
2295 .wd (ep_out_enable_enable_1_wd),
2296
2297 // from internal hardware
2298 .de (1'b0),
2299 .d ('0),
2300
2301 // to internal hardware
2302 .qe (),
2303 .q (reg2hw.ep_out_enable[1].q),
2304 .ds (),
2305
2306 // to register interface (read)
2307 .qs (ep_out_enable_enable_1_qs)
2308 );
2309
2310 // F[enable_2]: 2:2
2311 prim_subreg #(
2312 .DW (1),
2313 .SwAccess(prim_subreg_pkg::SwAccessRW),
2314 .RESVAL (1'h0),
2315 .Mubi (1'b0)
2316 ) u_ep_out_enable_enable_2 (
2317 .clk_i (clk_i),
2318 .rst_ni (rst_ni),
2319
2320 // from register interface
2321 .we (ep_out_enable_we),
2322 .wd (ep_out_enable_enable_2_wd),
2323
2324 // from internal hardware
2325 .de (1'b0),
2326 .d ('0),
2327
2328 // to internal hardware
2329 .qe (),
2330 .q (reg2hw.ep_out_enable[2].q),
2331 .ds (),
2332
2333 // to register interface (read)
2334 .qs (ep_out_enable_enable_2_qs)
2335 );
2336
2337 // F[enable_3]: 3:3
2338 prim_subreg #(
2339 .DW (1),
2340 .SwAccess(prim_subreg_pkg::SwAccessRW),
2341 .RESVAL (1'h0),
2342 .Mubi (1'b0)
2343 ) u_ep_out_enable_enable_3 (
2344 .clk_i (clk_i),
2345 .rst_ni (rst_ni),
2346
2347 // from register interface
2348 .we (ep_out_enable_we),
2349 .wd (ep_out_enable_enable_3_wd),
2350
2351 // from internal hardware
2352 .de (1'b0),
2353 .d ('0),
2354
2355 // to internal hardware
2356 .qe (),
2357 .q (reg2hw.ep_out_enable[3].q),
2358 .ds (),
2359
2360 // to register interface (read)
2361 .qs (ep_out_enable_enable_3_qs)
2362 );
2363
2364 // F[enable_4]: 4:4
2365 prim_subreg #(
2366 .DW (1),
2367 .SwAccess(prim_subreg_pkg::SwAccessRW),
2368 .RESVAL (1'h0),
2369 .Mubi (1'b0)
2370 ) u_ep_out_enable_enable_4 (
2371 .clk_i (clk_i),
2372 .rst_ni (rst_ni),
2373
2374 // from register interface
2375 .we (ep_out_enable_we),
2376 .wd (ep_out_enable_enable_4_wd),
2377
2378 // from internal hardware
2379 .de (1'b0),
2380 .d ('0),
2381
2382 // to internal hardware
2383 .qe (),
2384 .q (reg2hw.ep_out_enable[4].q),
2385 .ds (),
2386
2387 // to register interface (read)
2388 .qs (ep_out_enable_enable_4_qs)
2389 );
2390
2391 // F[enable_5]: 5:5
2392 prim_subreg #(
2393 .DW (1),
2394 .SwAccess(prim_subreg_pkg::SwAccessRW),
2395 .RESVAL (1'h0),
2396 .Mubi (1'b0)
2397 ) u_ep_out_enable_enable_5 (
2398 .clk_i (clk_i),
2399 .rst_ni (rst_ni),
2400
2401 // from register interface
2402 .we (ep_out_enable_we),
2403 .wd (ep_out_enable_enable_5_wd),
2404
2405 // from internal hardware
2406 .de (1'b0),
2407 .d ('0),
2408
2409 // to internal hardware
2410 .qe (),
2411 .q (reg2hw.ep_out_enable[5].q),
2412 .ds (),
2413
2414 // to register interface (read)
2415 .qs (ep_out_enable_enable_5_qs)
2416 );
2417
2418 // F[enable_6]: 6:6
2419 prim_subreg #(
2420 .DW (1),
2421 .SwAccess(prim_subreg_pkg::SwAccessRW),
2422 .RESVAL (1'h0),
2423 .Mubi (1'b0)
2424 ) u_ep_out_enable_enable_6 (
2425 .clk_i (clk_i),
2426 .rst_ni (rst_ni),
2427
2428 // from register interface
2429 .we (ep_out_enable_we),
2430 .wd (ep_out_enable_enable_6_wd),
2431
2432 // from internal hardware
2433 .de (1'b0),
2434 .d ('0),
2435
2436 // to internal hardware
2437 .qe (),
2438 .q (reg2hw.ep_out_enable[6].q),
2439 .ds (),
2440
2441 // to register interface (read)
2442 .qs (ep_out_enable_enable_6_qs)
2443 );
2444
2445 // F[enable_7]: 7:7
2446 prim_subreg #(
2447 .DW (1),
2448 .SwAccess(prim_subreg_pkg::SwAccessRW),
2449 .RESVAL (1'h0),
2450 .Mubi (1'b0)
2451 ) u_ep_out_enable_enable_7 (
2452 .clk_i (clk_i),
2453 .rst_ni (rst_ni),
2454
2455 // from register interface
2456 .we (ep_out_enable_we),
2457 .wd (ep_out_enable_enable_7_wd),
2458
2459 // from internal hardware
2460 .de (1'b0),
2461 .d ('0),
2462
2463 // to internal hardware
2464 .qe (),
2465 .q (reg2hw.ep_out_enable[7].q),
2466 .ds (),
2467
2468 // to register interface (read)
2469 .qs (ep_out_enable_enable_7_qs)
2470 );
2471
2472 // F[enable_8]: 8:8
2473 prim_subreg #(
2474 .DW (1),
2475 .SwAccess(prim_subreg_pkg::SwAccessRW),
2476 .RESVAL (1'h0),
2477 .Mubi (1'b0)
2478 ) u_ep_out_enable_enable_8 (
2479 .clk_i (clk_i),
2480 .rst_ni (rst_ni),
2481
2482 // from register interface
2483 .we (ep_out_enable_we),
2484 .wd (ep_out_enable_enable_8_wd),
2485
2486 // from internal hardware
2487 .de (1'b0),
2488 .d ('0),
2489
2490 // to internal hardware
2491 .qe (),
2492 .q (reg2hw.ep_out_enable[8].q),
2493 .ds (),
2494
2495 // to register interface (read)
2496 .qs (ep_out_enable_enable_8_qs)
2497 );
2498
2499 // F[enable_9]: 9:9
2500 prim_subreg #(
2501 .DW (1),
2502 .SwAccess(prim_subreg_pkg::SwAccessRW),
2503 .RESVAL (1'h0),
2504 .Mubi (1'b0)
2505 ) u_ep_out_enable_enable_9 (
2506 .clk_i (clk_i),
2507 .rst_ni (rst_ni),
2508
2509 // from register interface
2510 .we (ep_out_enable_we),
2511 .wd (ep_out_enable_enable_9_wd),
2512
2513 // from internal hardware
2514 .de (1'b0),
2515 .d ('0),
2516
2517 // to internal hardware
2518 .qe (),
2519 .q (reg2hw.ep_out_enable[9].q),
2520 .ds (),
2521
2522 // to register interface (read)
2523 .qs (ep_out_enable_enable_9_qs)
2524 );
2525
2526 // F[enable_10]: 10:10
2527 prim_subreg #(
2528 .DW (1),
2529 .SwAccess(prim_subreg_pkg::SwAccessRW),
2530 .RESVAL (1'h0),
2531 .Mubi (1'b0)
2532 ) u_ep_out_enable_enable_10 (
2533 .clk_i (clk_i),
2534 .rst_ni (rst_ni),
2535
2536 // from register interface
2537 .we (ep_out_enable_we),
2538 .wd (ep_out_enable_enable_10_wd),
2539
2540 // from internal hardware
2541 .de (1'b0),
2542 .d ('0),
2543
2544 // to internal hardware
2545 .qe (),
2546 .q (reg2hw.ep_out_enable[10].q),
2547 .ds (),
2548
2549 // to register interface (read)
2550 .qs (ep_out_enable_enable_10_qs)
2551 );
2552
2553 // F[enable_11]: 11:11
2554 prim_subreg #(
2555 .DW (1),
2556 .SwAccess(prim_subreg_pkg::SwAccessRW),
2557 .RESVAL (1'h0),
2558 .Mubi (1'b0)
2559 ) u_ep_out_enable_enable_11 (
2560 .clk_i (clk_i),
2561 .rst_ni (rst_ni),
2562
2563 // from register interface
2564 .we (ep_out_enable_we),
2565 .wd (ep_out_enable_enable_11_wd),
2566
2567 // from internal hardware
2568 .de (1'b0),
2569 .d ('0),
2570
2571 // to internal hardware
2572 .qe (),
2573 .q (reg2hw.ep_out_enable[11].q),
2574 .ds (),
2575
2576 // to register interface (read)
2577 .qs (ep_out_enable_enable_11_qs)
2578 );
2579
2580
2581 // Subregister 0 of Multireg ep_in_enable
2582 // R[ep_in_enable]: V(False)
2583 // F[enable_0]: 0:0
2584 prim_subreg #(
2585 .DW (1),
2586 .SwAccess(prim_subreg_pkg::SwAccessRW),
2587 .RESVAL (1'h0),
2588 .Mubi (1'b0)
2589 ) u_ep_in_enable_enable_0 (
2590 .clk_i (clk_i),
2591 .rst_ni (rst_ni),
2592
2593 // from register interface
2594 .we (ep_in_enable_we),
2595 .wd (ep_in_enable_enable_0_wd),
2596
2597 // from internal hardware
2598 .de (1'b0),
2599 .d ('0),
2600
2601 // to internal hardware
2602 .qe (),
2603 .q (reg2hw.ep_in_enable[0].q),
2604 .ds (),
2605
2606 // to register interface (read)
2607 .qs (ep_in_enable_enable_0_qs)
2608 );
2609
2610 // F[enable_1]: 1:1
2611 prim_subreg #(
2612 .DW (1),
2613 .SwAccess(prim_subreg_pkg::SwAccessRW),
2614 .RESVAL (1'h0),
2615 .Mubi (1'b0)
2616 ) u_ep_in_enable_enable_1 (
2617 .clk_i (clk_i),
2618 .rst_ni (rst_ni),
2619
2620 // from register interface
2621 .we (ep_in_enable_we),
2622 .wd (ep_in_enable_enable_1_wd),
2623
2624 // from internal hardware
2625 .de (1'b0),
2626 .d ('0),
2627
2628 // to internal hardware
2629 .qe (),
2630 .q (reg2hw.ep_in_enable[1].q),
2631 .ds (),
2632
2633 // to register interface (read)
2634 .qs (ep_in_enable_enable_1_qs)
2635 );
2636
2637 // F[enable_2]: 2:2
2638 prim_subreg #(
2639 .DW (1),
2640 .SwAccess(prim_subreg_pkg::SwAccessRW),
2641 .RESVAL (1'h0),
2642 .Mubi (1'b0)
2643 ) u_ep_in_enable_enable_2 (
2644 .clk_i (clk_i),
2645 .rst_ni (rst_ni),
2646
2647 // from register interface
2648 .we (ep_in_enable_we),
2649 .wd (ep_in_enable_enable_2_wd),
2650
2651 // from internal hardware
2652 .de (1'b0),
2653 .d ('0),
2654
2655 // to internal hardware
2656 .qe (),
2657 .q (reg2hw.ep_in_enable[2].q),
2658 .ds (),
2659
2660 // to register interface (read)
2661 .qs (ep_in_enable_enable_2_qs)
2662 );
2663
2664 // F[enable_3]: 3:3
2665 prim_subreg #(
2666 .DW (1),
2667 .SwAccess(prim_subreg_pkg::SwAccessRW),
2668 .RESVAL (1'h0),
2669 .Mubi (1'b0)
2670 ) u_ep_in_enable_enable_3 (
2671 .clk_i (clk_i),
2672 .rst_ni (rst_ni),
2673
2674 // from register interface
2675 .we (ep_in_enable_we),
2676 .wd (ep_in_enable_enable_3_wd),
2677
2678 // from internal hardware
2679 .de (1'b0),
2680 .d ('0),
2681
2682 // to internal hardware
2683 .qe (),
2684 .q (reg2hw.ep_in_enable[3].q),
2685 .ds (),
2686
2687 // to register interface (read)
2688 .qs (ep_in_enable_enable_3_qs)
2689 );
2690
2691 // F[enable_4]: 4:4
2692 prim_subreg #(
2693 .DW (1),
2694 .SwAccess(prim_subreg_pkg::SwAccessRW),
2695 .RESVAL (1'h0),
2696 .Mubi (1'b0)
2697 ) u_ep_in_enable_enable_4 (
2698 .clk_i (clk_i),
2699 .rst_ni (rst_ni),
2700
2701 // from register interface
2702 .we (ep_in_enable_we),
2703 .wd (ep_in_enable_enable_4_wd),
2704
2705 // from internal hardware
2706 .de (1'b0),
2707 .d ('0),
2708
2709 // to internal hardware
2710 .qe (),
2711 .q (reg2hw.ep_in_enable[4].q),
2712 .ds (),
2713
2714 // to register interface (read)
2715 .qs (ep_in_enable_enable_4_qs)
2716 );
2717
2718 // F[enable_5]: 5:5
2719 prim_subreg #(
2720 .DW (1),
2721 .SwAccess(prim_subreg_pkg::SwAccessRW),
2722 .RESVAL (1'h0),
2723 .Mubi (1'b0)
2724 ) u_ep_in_enable_enable_5 (
2725 .clk_i (clk_i),
2726 .rst_ni (rst_ni),
2727
2728 // from register interface
2729 .we (ep_in_enable_we),
2730 .wd (ep_in_enable_enable_5_wd),
2731
2732 // from internal hardware
2733 .de (1'b0),
2734 .d ('0),
2735
2736 // to internal hardware
2737 .qe (),
2738 .q (reg2hw.ep_in_enable[5].q),
2739 .ds (),
2740
2741 // to register interface (read)
2742 .qs (ep_in_enable_enable_5_qs)
2743 );
2744
2745 // F[enable_6]: 6:6
2746 prim_subreg #(
2747 .DW (1),
2748 .SwAccess(prim_subreg_pkg::SwAccessRW),
2749 .RESVAL (1'h0),
2750 .Mubi (1'b0)
2751 ) u_ep_in_enable_enable_6 (
2752 .clk_i (clk_i),
2753 .rst_ni (rst_ni),
2754
2755 // from register interface
2756 .we (ep_in_enable_we),
2757 .wd (ep_in_enable_enable_6_wd),
2758
2759 // from internal hardware
2760 .de (1'b0),
2761 .d ('0),
2762
2763 // to internal hardware
2764 .qe (),
2765 .q (reg2hw.ep_in_enable[6].q),
2766 .ds (),
2767
2768 // to register interface (read)
2769 .qs (ep_in_enable_enable_6_qs)
2770 );
2771
2772 // F[enable_7]: 7:7
2773 prim_subreg #(
2774 .DW (1),
2775 .SwAccess(prim_subreg_pkg::SwAccessRW),
2776 .RESVAL (1'h0),
2777 .Mubi (1'b0)
2778 ) u_ep_in_enable_enable_7 (
2779 .clk_i (clk_i),
2780 .rst_ni (rst_ni),
2781
2782 // from register interface
2783 .we (ep_in_enable_we),
2784 .wd (ep_in_enable_enable_7_wd),
2785
2786 // from internal hardware
2787 .de (1'b0),
2788 .d ('0),
2789
2790 // to internal hardware
2791 .qe (),
2792 .q (reg2hw.ep_in_enable[7].q),
2793 .ds (),
2794
2795 // to register interface (read)
2796 .qs (ep_in_enable_enable_7_qs)
2797 );
2798
2799 // F[enable_8]: 8:8
2800 prim_subreg #(
2801 .DW (1),
2802 .SwAccess(prim_subreg_pkg::SwAccessRW),
2803 .RESVAL (1'h0),
2804 .Mubi (1'b0)
2805 ) u_ep_in_enable_enable_8 (
2806 .clk_i (clk_i),
2807 .rst_ni (rst_ni),
2808
2809 // from register interface
2810 .we (ep_in_enable_we),
2811 .wd (ep_in_enable_enable_8_wd),
2812
2813 // from internal hardware
2814 .de (1'b0),
2815 .d ('0),
2816
2817 // to internal hardware
2818 .qe (),
2819 .q (reg2hw.ep_in_enable[8].q),
2820 .ds (),
2821
2822 // to register interface (read)
2823 .qs (ep_in_enable_enable_8_qs)
2824 );
2825
2826 // F[enable_9]: 9:9
2827 prim_subreg #(
2828 .DW (1),
2829 .SwAccess(prim_subreg_pkg::SwAccessRW),
2830 .RESVAL (1'h0),
2831 .Mubi (1'b0)
2832 ) u_ep_in_enable_enable_9 (
2833 .clk_i (clk_i),
2834 .rst_ni (rst_ni),
2835
2836 // from register interface
2837 .we (ep_in_enable_we),
2838 .wd (ep_in_enable_enable_9_wd),
2839
2840 // from internal hardware
2841 .de (1'b0),
2842 .d ('0),
2843
2844 // to internal hardware
2845 .qe (),
2846 .q (reg2hw.ep_in_enable[9].q),
2847 .ds (),
2848
2849 // to register interface (read)
2850 .qs (ep_in_enable_enable_9_qs)
2851 );
2852
2853 // F[enable_10]: 10:10
2854 prim_subreg #(
2855 .DW (1),
2856 .SwAccess(prim_subreg_pkg::SwAccessRW),
2857 .RESVAL (1'h0),
2858 .Mubi (1'b0)
2859 ) u_ep_in_enable_enable_10 (
2860 .clk_i (clk_i),
2861 .rst_ni (rst_ni),
2862
2863 // from register interface
2864 .we (ep_in_enable_we),
2865 .wd (ep_in_enable_enable_10_wd),
2866
2867 // from internal hardware
2868 .de (1'b0),
2869 .d ('0),
2870
2871 // to internal hardware
2872 .qe (),
2873 .q (reg2hw.ep_in_enable[10].q),
2874 .ds (),
2875
2876 // to register interface (read)
2877 .qs (ep_in_enable_enable_10_qs)
2878 );
2879
2880 // F[enable_11]: 11:11
2881 prim_subreg #(
2882 .DW (1),
2883 .SwAccess(prim_subreg_pkg::SwAccessRW),
2884 .RESVAL (1'h0),
2885 .Mubi (1'b0)
2886 ) u_ep_in_enable_enable_11 (
2887 .clk_i (clk_i),
2888 .rst_ni (rst_ni),
2889
2890 // from register interface
2891 .we (ep_in_enable_we),
2892 .wd (ep_in_enable_enable_11_wd),
2893
2894 // from internal hardware
2895 .de (1'b0),
2896 .d ('0),
2897
2898 // to internal hardware
2899 .qe (),
2900 .q (reg2hw.ep_in_enable[11].q),
2901 .ds (),
2902
2903 // to register interface (read)
2904 .qs (ep_in_enable_enable_11_qs)
2905 );
2906
2907
2908 // R[usbstat]: V(True)
2909 // F[frame]: 10:0
2910 prim_subreg_ext #(
2911 .DW (11)
2912 ) u_usbstat_frame (
2913 .re (usbstat_re),
2914 .we (1'b0),
2915 .wd ('0),
2916 .d (hw2reg.usbstat.frame.d),
2917 .qre (),
2918 .qe (),
2919 .q (),
2920 .ds (),
2921 .qs (usbstat_frame_qs)
2922 );
2923
2924 // F[host_lost]: 11:11
2925 prim_subreg_ext #(
2926 .DW (1)
2927 ) u_usbstat_host_lost (
2928 .re (usbstat_re),
2929 .we (1'b0),
2930 .wd ('0),
2931 .d (hw2reg.usbstat.host_lost.d),
2932 .qre (),
2933 .qe (),
2934 .q (),
2935 .ds (),
2936 .qs (usbstat_host_lost_qs)
2937 );
2938
2939 // F[link_state]: 14:12
2940 prim_subreg_ext #(
2941 .DW (3)
2942 ) u_usbstat_link_state (
2943 .re (usbstat_re),
2944 .we (1'b0),
2945 .wd ('0),
2946 .d (hw2reg.usbstat.link_state.d),
2947 .qre (),
2948 .qe (),
2949 .q (),
2950 .ds (),
2951 .qs (usbstat_link_state_qs)
2952 );
2953
2954 // F[sense]: 15:15
2955 prim_subreg_ext #(
2956 .DW (1)
2957 ) u_usbstat_sense (
2958 .re (usbstat_re),
2959 .we (1'b0),
2960 .wd ('0),
2961 .d (hw2reg.usbstat.sense.d),
2962 .qre (),
2963 .qe (),
2964 .q (),
2965 .ds (),
2966 .qs (usbstat_sense_qs)
2967 );
2968
2969 // F[av_out_depth]: 19:16
2970 prim_subreg_ext #(
2971 .DW (4)
2972 ) u_usbstat_av_out_depth (
2973 .re (usbstat_re),
2974 .we (1'b0),
2975 .wd ('0),
2976 .d (hw2reg.usbstat.av_out_depth.d),
2977 .qre (),
2978 .qe (),
2979 .q (),
2980 .ds (),
2981 .qs (usbstat_av_out_depth_qs)
2982 );
2983
2984 // F[av_setup_depth]: 22:20
2985 prim_subreg_ext #(
2986 .DW (3)
2987 ) u_usbstat_av_setup_depth (
2988 .re (usbstat_re),
2989 .we (1'b0),
2990 .wd ('0),
2991 .d (hw2reg.usbstat.av_setup_depth.d),
2992 .qre (),
2993 .qe (),
2994 .q (),
2995 .ds (),
2996 .qs (usbstat_av_setup_depth_qs)
2997 );
2998
2999 // F[av_out_full]: 23:23
3000 prim_subreg_ext #(
3001 .DW (1)
3002 ) u_usbstat_av_out_full (
3003 .re (usbstat_re),
3004 .we (1'b0),
3005 .wd ('0),
3006 .d (hw2reg.usbstat.av_out_full.d),
3007 .qre (),
3008 .qe (),
3009 .q (),
3010 .ds (),
3011 .qs (usbstat_av_out_full_qs)
3012 );
3013
3014 // F[rx_depth]: 27:24
3015 prim_subreg_ext #(
3016 .DW (4)
3017 ) u_usbstat_rx_depth (
3018 .re (usbstat_re),
3019 .we (1'b0),
3020 .wd ('0),
3021 .d (hw2reg.usbstat.rx_depth.d),
3022 .qre (),
3023 .qe (),
3024 .q (),
3025 .ds (),
3026 .qs (usbstat_rx_depth_qs)
3027 );
3028
3029 // F[av_setup_full]: 30:30
3030 prim_subreg_ext #(
3031 .DW (1)
3032 ) u_usbstat_av_setup_full (
3033 .re (usbstat_re),
3034 .we (1'b0),
3035 .wd ('0),
3036 .d (hw2reg.usbstat.av_setup_full.d),
3037 .qre (),
3038 .qe (),
3039 .q (),
3040 .ds (),
3041 .qs (usbstat_av_setup_full_qs)
3042 );
3043
3044 // F[rx_empty]: 31:31
3045 prim_subreg_ext #(
3046 .DW (1)
3047 ) u_usbstat_rx_empty (
3048 .re (usbstat_re),
3049 .we (1'b0),
3050 .wd ('0),
3051 .d (hw2reg.usbstat.rx_empty.d),
3052 .qre (),
3053 .qe (),
3054 .q (),
3055 .ds (),
3056 .qs (usbstat_rx_empty_qs)
3057 );
3058
3059
3060 // R[avoutbuffer]: V(True)
3061 logic avoutbuffer_qe;
3062 logic [0:0] avoutbuffer_flds_we;
3063 1/1 assign avoutbuffer_qe = &avoutbuffer_flds_we;
Tests: T3 T29 T30
3064 prim_subreg_ext #(
3065 .DW (5)
3066 ) u_avoutbuffer (
3067 .re (1'b0),
3068 .we (avoutbuffer_we),
3069 .wd (avoutbuffer_wd),
3070 .d ('0),
3071 .qre (),
3072 .qe (avoutbuffer_flds_we[0]),
3073 .q (reg2hw.avoutbuffer.q),
3074 .ds (),
3075 .qs ()
3076 );
3077 1/1 assign reg2hw.avoutbuffer.qe = avoutbuffer_qe;
Tests: T3 T29 T30
3078
3079
3080 // R[avsetupbuffer]: V(True)
3081 logic avsetupbuffer_qe;
3082 logic [0:0] avsetupbuffer_flds_we;
3083 1/1 assign avsetupbuffer_qe = &avsetupbuffer_flds_we;
Tests: T1 T2 T28
3084 prim_subreg_ext #(
3085 .DW (5)
3086 ) u_avsetupbuffer (
3087 .re (1'b0),
3088 .we (avsetupbuffer_we),
3089 .wd (avsetupbuffer_wd),
3090 .d ('0),
3091 .qre (),
3092 .qe (avsetupbuffer_flds_we[0]),
3093 .q (reg2hw.avsetupbuffer.q),
3094 .ds (),
3095 .qs ()
3096 );
3097 1/1 assign reg2hw.avsetupbuffer.qe = avsetupbuffer_qe;
Tests: T1 T2 T28
3098
3099
3100 // R[rxfifo]: V(True)
3101 // F[buffer]: 4:0
3102 prim_subreg_ext #(
3103 .DW (5)
3104 ) u_rxfifo_buffer (
3105 .re (rxfifo_re),
3106 .we (1'b0),
3107 .wd ('0),
3108 .d (hw2reg.rxfifo.buffer.d),
3109 .qre (reg2hw.rxfifo.buffer.re),
3110 .qe (),
3111 .q (reg2hw.rxfifo.buffer.q),
3112 .ds (),
3113 .qs (rxfifo_buffer_qs)
3114 );
3115
3116 // F[size]: 14:8
3117 prim_subreg_ext #(
3118 .DW (7)
3119 ) u_rxfifo_size (
3120 .re (rxfifo_re),
3121 .we (1'b0),
3122 .wd ('0),
3123 .d (hw2reg.rxfifo.size.d),
3124 .qre (reg2hw.rxfifo.size.re),
3125 .qe (),
3126 .q (reg2hw.rxfifo.size.q),
3127 .ds (),
3128 .qs (rxfifo_size_qs)
3129 );
3130
3131 // F[setup]: 19:19
3132 prim_subreg_ext #(
3133 .DW (1)
3134 ) u_rxfifo_setup (
3135 .re (rxfifo_re),
3136 .we (1'b0),
3137 .wd ('0),
3138 .d (hw2reg.rxfifo.setup.d),
3139 .qre (reg2hw.rxfifo.setup.re),
3140 .qe (),
3141 .q (reg2hw.rxfifo.setup.q),
3142 .ds (),
3143 .qs (rxfifo_setup_qs)
3144 );
3145
3146 // F[ep]: 23:20
3147 prim_subreg_ext #(
3148 .DW (4)
3149 ) u_rxfifo_ep (
3150 .re (rxfifo_re),
3151 .we (1'b0),
3152 .wd ('0),
3153 .d (hw2reg.rxfifo.ep.d),
3154 .qre (reg2hw.rxfifo.ep.re),
3155 .qe (),
3156 .q (reg2hw.rxfifo.ep.q),
3157 .ds (),
3158 .qs (rxfifo_ep_qs)
3159 );
3160
3161
3162 // Subregister 0 of Multireg rxenable_setup
3163 // R[rxenable_setup]: V(False)
3164 // F[setup_0]: 0:0
3165 prim_subreg #(
3166 .DW (1),
3167 .SwAccess(prim_subreg_pkg::SwAccessRW),
3168 .RESVAL (1'h0),
3169 .Mubi (1'b0)
3170 ) u_rxenable_setup_setup_0 (
3171 .clk_i (clk_i),
3172 .rst_ni (rst_ni),
3173
3174 // from register interface
3175 .we (rxenable_setup_we),
3176 .wd (rxenable_setup_setup_0_wd),
3177
3178 // from internal hardware
3179 .de (1'b0),
3180 .d ('0),
3181
3182 // to internal hardware
3183 .qe (),
3184 .q (reg2hw.rxenable_setup[0].q),
3185 .ds (),
3186
3187 // to register interface (read)
3188 .qs (rxenable_setup_setup_0_qs)
3189 );
3190
3191 // F[setup_1]: 1:1
3192 prim_subreg #(
3193 .DW (1),
3194 .SwAccess(prim_subreg_pkg::SwAccessRW),
3195 .RESVAL (1'h0),
3196 .Mubi (1'b0)
3197 ) u_rxenable_setup_setup_1 (
3198 .clk_i (clk_i),
3199 .rst_ni (rst_ni),
3200
3201 // from register interface
3202 .we (rxenable_setup_we),
3203 .wd (rxenable_setup_setup_1_wd),
3204
3205 // from internal hardware
3206 .de (1'b0),
3207 .d ('0),
3208
3209 // to internal hardware
3210 .qe (),
3211 .q (reg2hw.rxenable_setup[1].q),
3212 .ds (),
3213
3214 // to register interface (read)
3215 .qs (rxenable_setup_setup_1_qs)
3216 );
3217
3218 // F[setup_2]: 2:2
3219 prim_subreg #(
3220 .DW (1),
3221 .SwAccess(prim_subreg_pkg::SwAccessRW),
3222 .RESVAL (1'h0),
3223 .Mubi (1'b0)
3224 ) u_rxenable_setup_setup_2 (
3225 .clk_i (clk_i),
3226 .rst_ni (rst_ni),
3227
3228 // from register interface
3229 .we (rxenable_setup_we),
3230 .wd (rxenable_setup_setup_2_wd),
3231
3232 // from internal hardware
3233 .de (1'b0),
3234 .d ('0),
3235
3236 // to internal hardware
3237 .qe (),
3238 .q (reg2hw.rxenable_setup[2].q),
3239 .ds (),
3240
3241 // to register interface (read)
3242 .qs (rxenable_setup_setup_2_qs)
3243 );
3244
3245 // F[setup_3]: 3:3
3246 prim_subreg #(
3247 .DW (1),
3248 .SwAccess(prim_subreg_pkg::SwAccessRW),
3249 .RESVAL (1'h0),
3250 .Mubi (1'b0)
3251 ) u_rxenable_setup_setup_3 (
3252 .clk_i (clk_i),
3253 .rst_ni (rst_ni),
3254
3255 // from register interface
3256 .we (rxenable_setup_we),
3257 .wd (rxenable_setup_setup_3_wd),
3258
3259 // from internal hardware
3260 .de (1'b0),
3261 .d ('0),
3262
3263 // to internal hardware
3264 .qe (),
3265 .q (reg2hw.rxenable_setup[3].q),
3266 .ds (),
3267
3268 // to register interface (read)
3269 .qs (rxenable_setup_setup_3_qs)
3270 );
3271
3272 // F[setup_4]: 4:4
3273 prim_subreg #(
3274 .DW (1),
3275 .SwAccess(prim_subreg_pkg::SwAccessRW),
3276 .RESVAL (1'h0),
3277 .Mubi (1'b0)
3278 ) u_rxenable_setup_setup_4 (
3279 .clk_i (clk_i),
3280 .rst_ni (rst_ni),
3281
3282 // from register interface
3283 .we (rxenable_setup_we),
3284 .wd (rxenable_setup_setup_4_wd),
3285
3286 // from internal hardware
3287 .de (1'b0),
3288 .d ('0),
3289
3290 // to internal hardware
3291 .qe (),
3292 .q (reg2hw.rxenable_setup[4].q),
3293 .ds (),
3294
3295 // to register interface (read)
3296 .qs (rxenable_setup_setup_4_qs)
3297 );
3298
3299 // F[setup_5]: 5:5
3300 prim_subreg #(
3301 .DW (1),
3302 .SwAccess(prim_subreg_pkg::SwAccessRW),
3303 .RESVAL (1'h0),
3304 .Mubi (1'b0)
3305 ) u_rxenable_setup_setup_5 (
3306 .clk_i (clk_i),
3307 .rst_ni (rst_ni),
3308
3309 // from register interface
3310 .we (rxenable_setup_we),
3311 .wd (rxenable_setup_setup_5_wd),
3312
3313 // from internal hardware
3314 .de (1'b0),
3315 .d ('0),
3316
3317 // to internal hardware
3318 .qe (),
3319 .q (reg2hw.rxenable_setup[5].q),
3320 .ds (),
3321
3322 // to register interface (read)
3323 .qs (rxenable_setup_setup_5_qs)
3324 );
3325
3326 // F[setup_6]: 6:6
3327 prim_subreg #(
3328 .DW (1),
3329 .SwAccess(prim_subreg_pkg::SwAccessRW),
3330 .RESVAL (1'h0),
3331 .Mubi (1'b0)
3332 ) u_rxenable_setup_setup_6 (
3333 .clk_i (clk_i),
3334 .rst_ni (rst_ni),
3335
3336 // from register interface
3337 .we (rxenable_setup_we),
3338 .wd (rxenable_setup_setup_6_wd),
3339
3340 // from internal hardware
3341 .de (1'b0),
3342 .d ('0),
3343
3344 // to internal hardware
3345 .qe (),
3346 .q (reg2hw.rxenable_setup[6].q),
3347 .ds (),
3348
3349 // to register interface (read)
3350 .qs (rxenable_setup_setup_6_qs)
3351 );
3352
3353 // F[setup_7]: 7:7
3354 prim_subreg #(
3355 .DW (1),
3356 .SwAccess(prim_subreg_pkg::SwAccessRW),
3357 .RESVAL (1'h0),
3358 .Mubi (1'b0)
3359 ) u_rxenable_setup_setup_7 (
3360 .clk_i (clk_i),
3361 .rst_ni (rst_ni),
3362
3363 // from register interface
3364 .we (rxenable_setup_we),
3365 .wd (rxenable_setup_setup_7_wd),
3366
3367 // from internal hardware
3368 .de (1'b0),
3369 .d ('0),
3370
3371 // to internal hardware
3372 .qe (),
3373 .q (reg2hw.rxenable_setup[7].q),
3374 .ds (),
3375
3376 // to register interface (read)
3377 .qs (rxenable_setup_setup_7_qs)
3378 );
3379
3380 // F[setup_8]: 8:8
3381 prim_subreg #(
3382 .DW (1),
3383 .SwAccess(prim_subreg_pkg::SwAccessRW),
3384 .RESVAL (1'h0),
3385 .Mubi (1'b0)
3386 ) u_rxenable_setup_setup_8 (
3387 .clk_i (clk_i),
3388 .rst_ni (rst_ni),
3389
3390 // from register interface
3391 .we (rxenable_setup_we),
3392 .wd (rxenable_setup_setup_8_wd),
3393
3394 // from internal hardware
3395 .de (1'b0),
3396 .d ('0),
3397
3398 // to internal hardware
3399 .qe (),
3400 .q (reg2hw.rxenable_setup[8].q),
3401 .ds (),
3402
3403 // to register interface (read)
3404 .qs (rxenable_setup_setup_8_qs)
3405 );
3406
3407 // F[setup_9]: 9:9
3408 prim_subreg #(
3409 .DW (1),
3410 .SwAccess(prim_subreg_pkg::SwAccessRW),
3411 .RESVAL (1'h0),
3412 .Mubi (1'b0)
3413 ) u_rxenable_setup_setup_9 (
3414 .clk_i (clk_i),
3415 .rst_ni (rst_ni),
3416
3417 // from register interface
3418 .we (rxenable_setup_we),
3419 .wd (rxenable_setup_setup_9_wd),
3420
3421 // from internal hardware
3422 .de (1'b0),
3423 .d ('0),
3424
3425 // to internal hardware
3426 .qe (),
3427 .q (reg2hw.rxenable_setup[9].q),
3428 .ds (),
3429
3430 // to register interface (read)
3431 .qs (rxenable_setup_setup_9_qs)
3432 );
3433
3434 // F[setup_10]: 10:10
3435 prim_subreg #(
3436 .DW (1),
3437 .SwAccess(prim_subreg_pkg::SwAccessRW),
3438 .RESVAL (1'h0),
3439 .Mubi (1'b0)
3440 ) u_rxenable_setup_setup_10 (
3441 .clk_i (clk_i),
3442 .rst_ni (rst_ni),
3443
3444 // from register interface
3445 .we (rxenable_setup_we),
3446 .wd (rxenable_setup_setup_10_wd),
3447
3448 // from internal hardware
3449 .de (1'b0),
3450 .d ('0),
3451
3452 // to internal hardware
3453 .qe (),
3454 .q (reg2hw.rxenable_setup[10].q),
3455 .ds (),
3456
3457 // to register interface (read)
3458 .qs (rxenable_setup_setup_10_qs)
3459 );
3460
3461 // F[setup_11]: 11:11
3462 prim_subreg #(
3463 .DW (1),
3464 .SwAccess(prim_subreg_pkg::SwAccessRW),
3465 .RESVAL (1'h0),
3466 .Mubi (1'b0)
3467 ) u_rxenable_setup_setup_11 (
3468 .clk_i (clk_i),
3469 .rst_ni (rst_ni),
3470
3471 // from register interface
3472 .we (rxenable_setup_we),
3473 .wd (rxenable_setup_setup_11_wd),
3474
3475 // from internal hardware
3476 .de (1'b0),
3477 .d ('0),
3478
3479 // to internal hardware
3480 .qe (),
3481 .q (reg2hw.rxenable_setup[11].q),
3482 .ds (),
3483
3484 // to register interface (read)
3485 .qs (rxenable_setup_setup_11_qs)
3486 );
3487
3488
3489 // Subregister 0 of Multireg rxenable_out
3490 // R[rxenable_out]: V(False)
3491 // F[out_0]: 0:0
3492 prim_subreg #(
3493 .DW (1),
3494 .SwAccess(prim_subreg_pkg::SwAccessRW),
3495 .RESVAL (1'h0),
3496 .Mubi (1'b0)
3497 ) u_rxenable_out_out_0 (
3498 .clk_i (clk_i),
3499 .rst_ni (rst_ni),
3500
3501 // from register interface
3502 .we (rxenable_out_we),
3503 .wd (rxenable_out_out_0_wd),
3504
3505 // from internal hardware
3506 .de (hw2reg.rxenable_out[0].de),
3507 .d (hw2reg.rxenable_out[0].d),
3508
3509 // to internal hardware
3510 .qe (),
3511 .q (reg2hw.rxenable_out[0].q),
3512 .ds (),
3513
3514 // to register interface (read)
3515 .qs (rxenable_out_out_0_qs)
3516 );
3517
3518 // F[out_1]: 1:1
3519 prim_subreg #(
3520 .DW (1),
3521 .SwAccess(prim_subreg_pkg::SwAccessRW),
3522 .RESVAL (1'h0),
3523 .Mubi (1'b0)
3524 ) u_rxenable_out_out_1 (
3525 .clk_i (clk_i),
3526 .rst_ni (rst_ni),
3527
3528 // from register interface
3529 .we (rxenable_out_we),
3530 .wd (rxenable_out_out_1_wd),
3531
3532 // from internal hardware
3533 .de (hw2reg.rxenable_out[1].de),
3534 .d (hw2reg.rxenable_out[1].d),
3535
3536 // to internal hardware
3537 .qe (),
3538 .q (reg2hw.rxenable_out[1].q),
3539 .ds (),
3540
3541 // to register interface (read)
3542 .qs (rxenable_out_out_1_qs)
3543 );
3544
3545 // F[out_2]: 2:2
3546 prim_subreg #(
3547 .DW (1),
3548 .SwAccess(prim_subreg_pkg::SwAccessRW),
3549 .RESVAL (1'h0),
3550 .Mubi (1'b0)
3551 ) u_rxenable_out_out_2 (
3552 .clk_i (clk_i),
3553 .rst_ni (rst_ni),
3554
3555 // from register interface
3556 .we (rxenable_out_we),
3557 .wd (rxenable_out_out_2_wd),
3558
3559 // from internal hardware
3560 .de (hw2reg.rxenable_out[2].de),
3561 .d (hw2reg.rxenable_out[2].d),
3562
3563 // to internal hardware
3564 .qe (),
3565 .q (reg2hw.rxenable_out[2].q),
3566 .ds (),
3567
3568 // to register interface (read)
3569 .qs (rxenable_out_out_2_qs)
3570 );
3571
3572 // F[out_3]: 3:3
3573 prim_subreg #(
3574 .DW (1),
3575 .SwAccess(prim_subreg_pkg::SwAccessRW),
3576 .RESVAL (1'h0),
3577 .Mubi (1'b0)
3578 ) u_rxenable_out_out_3 (
3579 .clk_i (clk_i),
3580 .rst_ni (rst_ni),
3581
3582 // from register interface
3583 .we (rxenable_out_we),
3584 .wd (rxenable_out_out_3_wd),
3585
3586 // from internal hardware
3587 .de (hw2reg.rxenable_out[3].de),
3588 .d (hw2reg.rxenable_out[3].d),
3589
3590 // to internal hardware
3591 .qe (),
3592 .q (reg2hw.rxenable_out[3].q),
3593 .ds (),
3594
3595 // to register interface (read)
3596 .qs (rxenable_out_out_3_qs)
3597 );
3598
3599 // F[out_4]: 4:4
3600 prim_subreg #(
3601 .DW (1),
3602 .SwAccess(prim_subreg_pkg::SwAccessRW),
3603 .RESVAL (1'h0),
3604 .Mubi (1'b0)
3605 ) u_rxenable_out_out_4 (
3606 .clk_i (clk_i),
3607 .rst_ni (rst_ni),
3608
3609 // from register interface
3610 .we (rxenable_out_we),
3611 .wd (rxenable_out_out_4_wd),
3612
3613 // from internal hardware
3614 .de (hw2reg.rxenable_out[4].de),
3615 .d (hw2reg.rxenable_out[4].d),
3616
3617 // to internal hardware
3618 .qe (),
3619 .q (reg2hw.rxenable_out[4].q),
3620 .ds (),
3621
3622 // to register interface (read)
3623 .qs (rxenable_out_out_4_qs)
3624 );
3625
3626 // F[out_5]: 5:5
3627 prim_subreg #(
3628 .DW (1),
3629 .SwAccess(prim_subreg_pkg::SwAccessRW),
3630 .RESVAL (1'h0),
3631 .Mubi (1'b0)
3632 ) u_rxenable_out_out_5 (
3633 .clk_i (clk_i),
3634 .rst_ni (rst_ni),
3635
3636 // from register interface
3637 .we (rxenable_out_we),
3638 .wd (rxenable_out_out_5_wd),
3639
3640 // from internal hardware
3641 .de (hw2reg.rxenable_out[5].de),
3642 .d (hw2reg.rxenable_out[5].d),
3643
3644 // to internal hardware
3645 .qe (),
3646 .q (reg2hw.rxenable_out[5].q),
3647 .ds (),
3648
3649 // to register interface (read)
3650 .qs (rxenable_out_out_5_qs)
3651 );
3652
3653 // F[out_6]: 6:6
3654 prim_subreg #(
3655 .DW (1),
3656 .SwAccess(prim_subreg_pkg::SwAccessRW),
3657 .RESVAL (1'h0),
3658 .Mubi (1'b0)
3659 ) u_rxenable_out_out_6 (
3660 .clk_i (clk_i),
3661 .rst_ni (rst_ni),
3662
3663 // from register interface
3664 .we (rxenable_out_we),
3665 .wd (rxenable_out_out_6_wd),
3666
3667 // from internal hardware
3668 .de (hw2reg.rxenable_out[6].de),
3669 .d (hw2reg.rxenable_out[6].d),
3670
3671 // to internal hardware
3672 .qe (),
3673 .q (reg2hw.rxenable_out[6].q),
3674 .ds (),
3675
3676 // to register interface (read)
3677 .qs (rxenable_out_out_6_qs)
3678 );
3679
3680 // F[out_7]: 7:7
3681 prim_subreg #(
3682 .DW (1),
3683 .SwAccess(prim_subreg_pkg::SwAccessRW),
3684 .RESVAL (1'h0),
3685 .Mubi (1'b0)
3686 ) u_rxenable_out_out_7 (
3687 .clk_i (clk_i),
3688 .rst_ni (rst_ni),
3689
3690 // from register interface
3691 .we (rxenable_out_we),
3692 .wd (rxenable_out_out_7_wd),
3693
3694 // from internal hardware
3695 .de (hw2reg.rxenable_out[7].de),
3696 .d (hw2reg.rxenable_out[7].d),
3697
3698 // to internal hardware
3699 .qe (),
3700 .q (reg2hw.rxenable_out[7].q),
3701 .ds (),
3702
3703 // to register interface (read)
3704 .qs (rxenable_out_out_7_qs)
3705 );
3706
3707 // F[out_8]: 8:8
3708 prim_subreg #(
3709 .DW (1),
3710 .SwAccess(prim_subreg_pkg::SwAccessRW),
3711 .RESVAL (1'h0),
3712 .Mubi (1'b0)
3713 ) u_rxenable_out_out_8 (
3714 .clk_i (clk_i),
3715 .rst_ni (rst_ni),
3716
3717 // from register interface
3718 .we (rxenable_out_we),
3719 .wd (rxenable_out_out_8_wd),
3720
3721 // from internal hardware
3722 .de (hw2reg.rxenable_out[8].de),
3723 .d (hw2reg.rxenable_out[8].d),
3724
3725 // to internal hardware
3726 .qe (),
3727 .q (reg2hw.rxenable_out[8].q),
3728 .ds (),
3729
3730 // to register interface (read)
3731 .qs (rxenable_out_out_8_qs)
3732 );
3733
3734 // F[out_9]: 9:9
3735 prim_subreg #(
3736 .DW (1),
3737 .SwAccess(prim_subreg_pkg::SwAccessRW),
3738 .RESVAL (1'h0),
3739 .Mubi (1'b0)
3740 ) u_rxenable_out_out_9 (
3741 .clk_i (clk_i),
3742 .rst_ni (rst_ni),
3743
3744 // from register interface
3745 .we (rxenable_out_we),
3746 .wd (rxenable_out_out_9_wd),
3747
3748 // from internal hardware
3749 .de (hw2reg.rxenable_out[9].de),
3750 .d (hw2reg.rxenable_out[9].d),
3751
3752 // to internal hardware
3753 .qe (),
3754 .q (reg2hw.rxenable_out[9].q),
3755 .ds (),
3756
3757 // to register interface (read)
3758 .qs (rxenable_out_out_9_qs)
3759 );
3760
3761 // F[out_10]: 10:10
3762 prim_subreg #(
3763 .DW (1),
3764 .SwAccess(prim_subreg_pkg::SwAccessRW),
3765 .RESVAL (1'h0),
3766 .Mubi (1'b0)
3767 ) u_rxenable_out_out_10 (
3768 .clk_i (clk_i),
3769 .rst_ni (rst_ni),
3770
3771 // from register interface
3772 .we (rxenable_out_we),
3773 .wd (rxenable_out_out_10_wd),
3774
3775 // from internal hardware
3776 .de (hw2reg.rxenable_out[10].de),
3777 .d (hw2reg.rxenable_out[10].d),
3778
3779 // to internal hardware
3780 .qe (),
3781 .q (reg2hw.rxenable_out[10].q),
3782 .ds (),
3783
3784 // to register interface (read)
3785 .qs (rxenable_out_out_10_qs)
3786 );
3787
3788 // F[out_11]: 11:11
3789 prim_subreg #(
3790 .DW (1),
3791 .SwAccess(prim_subreg_pkg::SwAccessRW),
3792 .RESVAL (1'h0),
3793 .Mubi (1'b0)
3794 ) u_rxenable_out_out_11 (
3795 .clk_i (clk_i),
3796 .rst_ni (rst_ni),
3797
3798 // from register interface
3799 .we (rxenable_out_we),
3800 .wd (rxenable_out_out_11_wd),
3801
3802 // from internal hardware
3803 .de (hw2reg.rxenable_out[11].de),
3804 .d (hw2reg.rxenable_out[11].d),
3805
3806 // to internal hardware
3807 .qe (),
3808 .q (reg2hw.rxenable_out[11].q),
3809 .ds (),
3810
3811 // to register interface (read)
3812 .qs (rxenable_out_out_11_qs)
3813 );
3814
3815
3816 // Subregister 0 of Multireg set_nak_out
3817 // R[set_nak_out]: V(False)
3818 // F[enable_0]: 0:0
3819 prim_subreg #(
3820 .DW (1),
3821 .SwAccess(prim_subreg_pkg::SwAccessRW),
3822 .RESVAL (1'h0),
3823 .Mubi (1'b0)
3824 ) u_set_nak_out_enable_0 (
3825 .clk_i (clk_i),
3826 .rst_ni (rst_ni),
3827
3828 // from register interface
3829 .we (set_nak_out_we),
3830 .wd (set_nak_out_enable_0_wd),
3831
3832 // from internal hardware
3833 .de (1'b0),
3834 .d ('0),
3835
3836 // to internal hardware
3837 .qe (),
3838 .q (reg2hw.set_nak_out[0].q),
3839 .ds (),
3840
3841 // to register interface (read)
3842 .qs (set_nak_out_enable_0_qs)
3843 );
3844
3845 // F[enable_1]: 1:1
3846 prim_subreg #(
3847 .DW (1),
3848 .SwAccess(prim_subreg_pkg::SwAccessRW),
3849 .RESVAL (1'h0),
3850 .Mubi (1'b0)
3851 ) u_set_nak_out_enable_1 (
3852 .clk_i (clk_i),
3853 .rst_ni (rst_ni),
3854
3855 // from register interface
3856 .we (set_nak_out_we),
3857 .wd (set_nak_out_enable_1_wd),
3858
3859 // from internal hardware
3860 .de (1'b0),
3861 .d ('0),
3862
3863 // to internal hardware
3864 .qe (),
3865 .q (reg2hw.set_nak_out[1].q),
3866 .ds (),
3867
3868 // to register interface (read)
3869 .qs (set_nak_out_enable_1_qs)
3870 );
3871
3872 // F[enable_2]: 2:2
3873 prim_subreg #(
3874 .DW (1),
3875 .SwAccess(prim_subreg_pkg::SwAccessRW),
3876 .RESVAL (1'h0),
3877 .Mubi (1'b0)
3878 ) u_set_nak_out_enable_2 (
3879 .clk_i (clk_i),
3880 .rst_ni (rst_ni),
3881
3882 // from register interface
3883 .we (set_nak_out_we),
3884 .wd (set_nak_out_enable_2_wd),
3885
3886 // from internal hardware
3887 .de (1'b0),
3888 .d ('0),
3889
3890 // to internal hardware
3891 .qe (),
3892 .q (reg2hw.set_nak_out[2].q),
3893 .ds (),
3894
3895 // to register interface (read)
3896 .qs (set_nak_out_enable_2_qs)
3897 );
3898
3899 // F[enable_3]: 3:3
3900 prim_subreg #(
3901 .DW (1),
3902 .SwAccess(prim_subreg_pkg::SwAccessRW),
3903 .RESVAL (1'h0),
3904 .Mubi (1'b0)
3905 ) u_set_nak_out_enable_3 (
3906 .clk_i (clk_i),
3907 .rst_ni (rst_ni),
3908
3909 // from register interface
3910 .we (set_nak_out_we),
3911 .wd (set_nak_out_enable_3_wd),
3912
3913 // from internal hardware
3914 .de (1'b0),
3915 .d ('0),
3916
3917 // to internal hardware
3918 .qe (),
3919 .q (reg2hw.set_nak_out[3].q),
3920 .ds (),
3921
3922 // to register interface (read)
3923 .qs (set_nak_out_enable_3_qs)
3924 );
3925
3926 // F[enable_4]: 4:4
3927 prim_subreg #(
3928 .DW (1),
3929 .SwAccess(prim_subreg_pkg::SwAccessRW),
3930 .RESVAL (1'h0),
3931 .Mubi (1'b0)
3932 ) u_set_nak_out_enable_4 (
3933 .clk_i (clk_i),
3934 .rst_ni (rst_ni),
3935
3936 // from register interface
3937 .we (set_nak_out_we),
3938 .wd (set_nak_out_enable_4_wd),
3939
3940 // from internal hardware
3941 .de (1'b0),
3942 .d ('0),
3943
3944 // to internal hardware
3945 .qe (),
3946 .q (reg2hw.set_nak_out[4].q),
3947 .ds (),
3948
3949 // to register interface (read)
3950 .qs (set_nak_out_enable_4_qs)
3951 );
3952
3953 // F[enable_5]: 5:5
3954 prim_subreg #(
3955 .DW (1),
3956 .SwAccess(prim_subreg_pkg::SwAccessRW),
3957 .RESVAL (1'h0),
3958 .Mubi (1'b0)
3959 ) u_set_nak_out_enable_5 (
3960 .clk_i (clk_i),
3961 .rst_ni (rst_ni),
3962
3963 // from register interface
3964 .we (set_nak_out_we),
3965 .wd (set_nak_out_enable_5_wd),
3966
3967 // from internal hardware
3968 .de (1'b0),
3969 .d ('0),
3970
3971 // to internal hardware
3972 .qe (),
3973 .q (reg2hw.set_nak_out[5].q),
3974 .ds (),
3975
3976 // to register interface (read)
3977 .qs (set_nak_out_enable_5_qs)
3978 );
3979
3980 // F[enable_6]: 6:6
3981 prim_subreg #(
3982 .DW (1),
3983 .SwAccess(prim_subreg_pkg::SwAccessRW),
3984 .RESVAL (1'h0),
3985 .Mubi (1'b0)
3986 ) u_set_nak_out_enable_6 (
3987 .clk_i (clk_i),
3988 .rst_ni (rst_ni),
3989
3990 // from register interface
3991 .we (set_nak_out_we),
3992 .wd (set_nak_out_enable_6_wd),
3993
3994 // from internal hardware
3995 .de (1'b0),
3996 .d ('0),
3997
3998 // to internal hardware
3999 .qe (),
4000 .q (reg2hw.set_nak_out[6].q),
4001 .ds (),
4002
4003 // to register interface (read)
4004 .qs (set_nak_out_enable_6_qs)
4005 );
4006
4007 // F[enable_7]: 7:7
4008 prim_subreg #(
4009 .DW (1),
4010 .SwAccess(prim_subreg_pkg::SwAccessRW),
4011 .RESVAL (1'h0),
4012 .Mubi (1'b0)
4013 ) u_set_nak_out_enable_7 (
4014 .clk_i (clk_i),
4015 .rst_ni (rst_ni),
4016
4017 // from register interface
4018 .we (set_nak_out_we),
4019 .wd (set_nak_out_enable_7_wd),
4020
4021 // from internal hardware
4022 .de (1'b0),
4023 .d ('0),
4024
4025 // to internal hardware
4026 .qe (),
4027 .q (reg2hw.set_nak_out[7].q),
4028 .ds (),
4029
4030 // to register interface (read)
4031 .qs (set_nak_out_enable_7_qs)
4032 );
4033
4034 // F[enable_8]: 8:8
4035 prim_subreg #(
4036 .DW (1),
4037 .SwAccess(prim_subreg_pkg::SwAccessRW),
4038 .RESVAL (1'h0),
4039 .Mubi (1'b0)
4040 ) u_set_nak_out_enable_8 (
4041 .clk_i (clk_i),
4042 .rst_ni (rst_ni),
4043
4044 // from register interface
4045 .we (set_nak_out_we),
4046 .wd (set_nak_out_enable_8_wd),
4047
4048 // from internal hardware
4049 .de (1'b0),
4050 .d ('0),
4051
4052 // to internal hardware
4053 .qe (),
4054 .q (reg2hw.set_nak_out[8].q),
4055 .ds (),
4056
4057 // to register interface (read)
4058 .qs (set_nak_out_enable_8_qs)
4059 );
4060
4061 // F[enable_9]: 9:9
4062 prim_subreg #(
4063 .DW (1),
4064 .SwAccess(prim_subreg_pkg::SwAccessRW),
4065 .RESVAL (1'h0),
4066 .Mubi (1'b0)
4067 ) u_set_nak_out_enable_9 (
4068 .clk_i (clk_i),
4069 .rst_ni (rst_ni),
4070
4071 // from register interface
4072 .we (set_nak_out_we),
4073 .wd (set_nak_out_enable_9_wd),
4074
4075 // from internal hardware
4076 .de (1'b0),
4077 .d ('0),
4078
4079 // to internal hardware
4080 .qe (),
4081 .q (reg2hw.set_nak_out[9].q),
4082 .ds (),
4083
4084 // to register interface (read)
4085 .qs (set_nak_out_enable_9_qs)
4086 );
4087
4088 // F[enable_10]: 10:10
4089 prim_subreg #(
4090 .DW (1),
4091 .SwAccess(prim_subreg_pkg::SwAccessRW),
4092 .RESVAL (1'h0),
4093 .Mubi (1'b0)
4094 ) u_set_nak_out_enable_10 (
4095 .clk_i (clk_i),
4096 .rst_ni (rst_ni),
4097
4098 // from register interface
4099 .we (set_nak_out_we),
4100 .wd (set_nak_out_enable_10_wd),
4101
4102 // from internal hardware
4103 .de (1'b0),
4104 .d ('0),
4105
4106 // to internal hardware
4107 .qe (),
4108 .q (reg2hw.set_nak_out[10].q),
4109 .ds (),
4110
4111 // to register interface (read)
4112 .qs (set_nak_out_enable_10_qs)
4113 );
4114
4115 // F[enable_11]: 11:11
4116 prim_subreg #(
4117 .DW (1),
4118 .SwAccess(prim_subreg_pkg::SwAccessRW),
4119 .RESVAL (1'h0),
4120 .Mubi (1'b0)
4121 ) u_set_nak_out_enable_11 (
4122 .clk_i (clk_i),
4123 .rst_ni (rst_ni),
4124
4125 // from register interface
4126 .we (set_nak_out_we),
4127 .wd (set_nak_out_enable_11_wd),
4128
4129 // from internal hardware
4130 .de (1'b0),
4131 .d ('0),
4132
4133 // to internal hardware
4134 .qe (),
4135 .q (reg2hw.set_nak_out[11].q),
4136 .ds (),
4137
4138 // to register interface (read)
4139 .qs (set_nak_out_enable_11_qs)
4140 );
4141
4142
4143 // Subregister 0 of Multireg in_sent
4144 // R[in_sent]: V(False)
4145 // F[sent_0]: 0:0
4146 prim_subreg #(
4147 .DW (1),
4148 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4149 .RESVAL (1'h0),
4150 .Mubi (1'b0)
4151 ) u_in_sent_sent_0 (
4152 .clk_i (clk_i),
4153 .rst_ni (rst_ni),
4154
4155 // from register interface
4156 .we (in_sent_we),
4157 .wd (in_sent_sent_0_wd),
4158
4159 // from internal hardware
4160 .de (hw2reg.in_sent[0].de),
4161 .d (hw2reg.in_sent[0].d),
4162
4163 // to internal hardware
4164 .qe (),
4165 .q (reg2hw.in_sent[0].q),
4166 .ds (),
4167
4168 // to register interface (read)
4169 .qs (in_sent_sent_0_qs)
4170 );
4171
4172 // F[sent_1]: 1:1
4173 prim_subreg #(
4174 .DW (1),
4175 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4176 .RESVAL (1'h0),
4177 .Mubi (1'b0)
4178 ) u_in_sent_sent_1 (
4179 .clk_i (clk_i),
4180 .rst_ni (rst_ni),
4181
4182 // from register interface
4183 .we (in_sent_we),
4184 .wd (in_sent_sent_1_wd),
4185
4186 // from internal hardware
4187 .de (hw2reg.in_sent[1].de),
4188 .d (hw2reg.in_sent[1].d),
4189
4190 // to internal hardware
4191 .qe (),
4192 .q (reg2hw.in_sent[1].q),
4193 .ds (),
4194
4195 // to register interface (read)
4196 .qs (in_sent_sent_1_qs)
4197 );
4198
4199 // F[sent_2]: 2:2
4200 prim_subreg #(
4201 .DW (1),
4202 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4203 .RESVAL (1'h0),
4204 .Mubi (1'b0)
4205 ) u_in_sent_sent_2 (
4206 .clk_i (clk_i),
4207 .rst_ni (rst_ni),
4208
4209 // from register interface
4210 .we (in_sent_we),
4211 .wd (in_sent_sent_2_wd),
4212
4213 // from internal hardware
4214 .de (hw2reg.in_sent[2].de),
4215 .d (hw2reg.in_sent[2].d),
4216
4217 // to internal hardware
4218 .qe (),
4219 .q (reg2hw.in_sent[2].q),
4220 .ds (),
4221
4222 // to register interface (read)
4223 .qs (in_sent_sent_2_qs)
4224 );
4225
4226 // F[sent_3]: 3:3
4227 prim_subreg #(
4228 .DW (1),
4229 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4230 .RESVAL (1'h0),
4231 .Mubi (1'b0)
4232 ) u_in_sent_sent_3 (
4233 .clk_i (clk_i),
4234 .rst_ni (rst_ni),
4235
4236 // from register interface
4237 .we (in_sent_we),
4238 .wd (in_sent_sent_3_wd),
4239
4240 // from internal hardware
4241 .de (hw2reg.in_sent[3].de),
4242 .d (hw2reg.in_sent[3].d),
4243
4244 // to internal hardware
4245 .qe (),
4246 .q (reg2hw.in_sent[3].q),
4247 .ds (),
4248
4249 // to register interface (read)
4250 .qs (in_sent_sent_3_qs)
4251 );
4252
4253 // F[sent_4]: 4:4
4254 prim_subreg #(
4255 .DW (1),
4256 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4257 .RESVAL (1'h0),
4258 .Mubi (1'b0)
4259 ) u_in_sent_sent_4 (
4260 .clk_i (clk_i),
4261 .rst_ni (rst_ni),
4262
4263 // from register interface
4264 .we (in_sent_we),
4265 .wd (in_sent_sent_4_wd),
4266
4267 // from internal hardware
4268 .de (hw2reg.in_sent[4].de),
4269 .d (hw2reg.in_sent[4].d),
4270
4271 // to internal hardware
4272 .qe (),
4273 .q (reg2hw.in_sent[4].q),
4274 .ds (),
4275
4276 // to register interface (read)
4277 .qs (in_sent_sent_4_qs)
4278 );
4279
4280 // F[sent_5]: 5:5
4281 prim_subreg #(
4282 .DW (1),
4283 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4284 .RESVAL (1'h0),
4285 .Mubi (1'b0)
4286 ) u_in_sent_sent_5 (
4287 .clk_i (clk_i),
4288 .rst_ni (rst_ni),
4289
4290 // from register interface
4291 .we (in_sent_we),
4292 .wd (in_sent_sent_5_wd),
4293
4294 // from internal hardware
4295 .de (hw2reg.in_sent[5].de),
4296 .d (hw2reg.in_sent[5].d),
4297
4298 // to internal hardware
4299 .qe (),
4300 .q (reg2hw.in_sent[5].q),
4301 .ds (),
4302
4303 // to register interface (read)
4304 .qs (in_sent_sent_5_qs)
4305 );
4306
4307 // F[sent_6]: 6:6
4308 prim_subreg #(
4309 .DW (1),
4310 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4311 .RESVAL (1'h0),
4312 .Mubi (1'b0)
4313 ) u_in_sent_sent_6 (
4314 .clk_i (clk_i),
4315 .rst_ni (rst_ni),
4316
4317 // from register interface
4318 .we (in_sent_we),
4319 .wd (in_sent_sent_6_wd),
4320
4321 // from internal hardware
4322 .de (hw2reg.in_sent[6].de),
4323 .d (hw2reg.in_sent[6].d),
4324
4325 // to internal hardware
4326 .qe (),
4327 .q (reg2hw.in_sent[6].q),
4328 .ds (),
4329
4330 // to register interface (read)
4331 .qs (in_sent_sent_6_qs)
4332 );
4333
4334 // F[sent_7]: 7:7
4335 prim_subreg #(
4336 .DW (1),
4337 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4338 .RESVAL (1'h0),
4339 .Mubi (1'b0)
4340 ) u_in_sent_sent_7 (
4341 .clk_i (clk_i),
4342 .rst_ni (rst_ni),
4343
4344 // from register interface
4345 .we (in_sent_we),
4346 .wd (in_sent_sent_7_wd),
4347
4348 // from internal hardware
4349 .de (hw2reg.in_sent[7].de),
4350 .d (hw2reg.in_sent[7].d),
4351
4352 // to internal hardware
4353 .qe (),
4354 .q (reg2hw.in_sent[7].q),
4355 .ds (),
4356
4357 // to register interface (read)
4358 .qs (in_sent_sent_7_qs)
4359 );
4360
4361 // F[sent_8]: 8:8
4362 prim_subreg #(
4363 .DW (1),
4364 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4365 .RESVAL (1'h0),
4366 .Mubi (1'b0)
4367 ) u_in_sent_sent_8 (
4368 .clk_i (clk_i),
4369 .rst_ni (rst_ni),
4370
4371 // from register interface
4372 .we (in_sent_we),
4373 .wd (in_sent_sent_8_wd),
4374
4375 // from internal hardware
4376 .de (hw2reg.in_sent[8].de),
4377 .d (hw2reg.in_sent[8].d),
4378
4379 // to internal hardware
4380 .qe (),
4381 .q (reg2hw.in_sent[8].q),
4382 .ds (),
4383
4384 // to register interface (read)
4385 .qs (in_sent_sent_8_qs)
4386 );
4387
4388 // F[sent_9]: 9:9
4389 prim_subreg #(
4390 .DW (1),
4391 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4392 .RESVAL (1'h0),
4393 .Mubi (1'b0)
4394 ) u_in_sent_sent_9 (
4395 .clk_i (clk_i),
4396 .rst_ni (rst_ni),
4397
4398 // from register interface
4399 .we (in_sent_we),
4400 .wd (in_sent_sent_9_wd),
4401
4402 // from internal hardware
4403 .de (hw2reg.in_sent[9].de),
4404 .d (hw2reg.in_sent[9].d),
4405
4406 // to internal hardware
4407 .qe (),
4408 .q (reg2hw.in_sent[9].q),
4409 .ds (),
4410
4411 // to register interface (read)
4412 .qs (in_sent_sent_9_qs)
4413 );
4414
4415 // F[sent_10]: 10:10
4416 prim_subreg #(
4417 .DW (1),
4418 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4419 .RESVAL (1'h0),
4420 .Mubi (1'b0)
4421 ) u_in_sent_sent_10 (
4422 .clk_i (clk_i),
4423 .rst_ni (rst_ni),
4424
4425 // from register interface
4426 .we (in_sent_we),
4427 .wd (in_sent_sent_10_wd),
4428
4429 // from internal hardware
4430 .de (hw2reg.in_sent[10].de),
4431 .d (hw2reg.in_sent[10].d),
4432
4433 // to internal hardware
4434 .qe (),
4435 .q (reg2hw.in_sent[10].q),
4436 .ds (),
4437
4438 // to register interface (read)
4439 .qs (in_sent_sent_10_qs)
4440 );
4441
4442 // F[sent_11]: 11:11
4443 prim_subreg #(
4444 .DW (1),
4445 .SwAccess(prim_subreg_pkg::SwAccessW1C),
4446 .RESVAL (1'h0),
4447 .Mubi (1'b0)
4448 ) u_in_sent_sent_11 (
4449 .clk_i (clk_i),
4450 .rst_ni (rst_ni),
4451
4452 // from register interface
4453 .we (in_sent_we),
4454 .wd (in_sent_sent_11_wd),
4455
4456 // from internal hardware
4457 .de (hw2reg.in_sent[11].de),
4458 .d (hw2reg.in_sent[11].d),
4459
4460 // to internal hardware
4461 .qe (),
4462 .q (reg2hw.in_sent[11].q),
4463 .ds (),
4464
4465 // to register interface (read)
4466 .qs (in_sent_sent_11_qs)
4467 );
4468
4469
4470 // Subregister 0 of Multireg out_stall
4471 // R[out_stall]: V(False)
4472 // F[endpoint_0]: 0:0
4473 prim_subreg #(
4474 .DW (1),
4475 .SwAccess(prim_subreg_pkg::SwAccessRW),
4476 .RESVAL (1'h0),
4477 .Mubi (1'b0)
4478 ) u_out_stall_endpoint_0 (
4479 .clk_i (clk_i),
4480 .rst_ni (rst_ni),
4481
4482 // from register interface
4483 .we (out_stall_we),
4484 .wd (out_stall_endpoint_0_wd),
4485
4486 // from internal hardware
4487 .de (hw2reg.out_stall[0].de),
4488 .d (hw2reg.out_stall[0].d),
4489
4490 // to internal hardware
4491 .qe (),
4492 .q (reg2hw.out_stall[0].q),
4493 .ds (),
4494
4495 // to register interface (read)
4496 .qs (out_stall_endpoint_0_qs)
4497 );
4498
4499 // F[endpoint_1]: 1:1
4500 prim_subreg #(
4501 .DW (1),
4502 .SwAccess(prim_subreg_pkg::SwAccessRW),
4503 .RESVAL (1'h0),
4504 .Mubi (1'b0)
4505 ) u_out_stall_endpoint_1 (
4506 .clk_i (clk_i),
4507 .rst_ni (rst_ni),
4508
4509 // from register interface
4510 .we (out_stall_we),
4511 .wd (out_stall_endpoint_1_wd),
4512
4513 // from internal hardware
4514 .de (hw2reg.out_stall[1].de),
4515 .d (hw2reg.out_stall[1].d),
4516
4517 // to internal hardware
4518 .qe (),
4519 .q (reg2hw.out_stall[1].q),
4520 .ds (),
4521
4522 // to register interface (read)
4523 .qs (out_stall_endpoint_1_qs)
4524 );
4525
4526 // F[endpoint_2]: 2:2
4527 prim_subreg #(
4528 .DW (1),
4529 .SwAccess(prim_subreg_pkg::SwAccessRW),
4530 .RESVAL (1'h0),
4531 .Mubi (1'b0)
4532 ) u_out_stall_endpoint_2 (
4533 .clk_i (clk_i),
4534 .rst_ni (rst_ni),
4535
4536 // from register interface
4537 .we (out_stall_we),
4538 .wd (out_stall_endpoint_2_wd),
4539
4540 // from internal hardware
4541 .de (hw2reg.out_stall[2].de),
4542 .d (hw2reg.out_stall[2].d),
4543
4544 // to internal hardware
4545 .qe (),
4546 .q (reg2hw.out_stall[2].q),
4547 .ds (),
4548
4549 // to register interface (read)
4550 .qs (out_stall_endpoint_2_qs)
4551 );
4552
4553 // F[endpoint_3]: 3:3
4554 prim_subreg #(
4555 .DW (1),
4556 .SwAccess(prim_subreg_pkg::SwAccessRW),
4557 .RESVAL (1'h0),
4558 .Mubi (1'b0)
4559 ) u_out_stall_endpoint_3 (
4560 .clk_i (clk_i),
4561 .rst_ni (rst_ni),
4562
4563 // from register interface
4564 .we (out_stall_we),
4565 .wd (out_stall_endpoint_3_wd),
4566
4567 // from internal hardware
4568 .de (hw2reg.out_stall[3].de),
4569 .d (hw2reg.out_stall[3].d),
4570
4571 // to internal hardware
4572 .qe (),
4573 .q (reg2hw.out_stall[3].q),
4574 .ds (),
4575
4576 // to register interface (read)
4577 .qs (out_stall_endpoint_3_qs)
4578 );
4579
4580 // F[endpoint_4]: 4:4
4581 prim_subreg #(
4582 .DW (1),
4583 .SwAccess(prim_subreg_pkg::SwAccessRW),
4584 .RESVAL (1'h0),
4585 .Mubi (1'b0)
4586 ) u_out_stall_endpoint_4 (
4587 .clk_i (clk_i),
4588 .rst_ni (rst_ni),
4589
4590 // from register interface
4591 .we (out_stall_we),
4592 .wd (out_stall_endpoint_4_wd),
4593
4594 // from internal hardware
4595 .de (hw2reg.out_stall[4].de),
4596 .d (hw2reg.out_stall[4].d),
4597
4598 // to internal hardware
4599 .qe (),
4600 .q (reg2hw.out_stall[4].q),
4601 .ds (),
4602
4603 // to register interface (read)
4604 .qs (out_stall_endpoint_4_qs)
4605 );
4606
4607 // F[endpoint_5]: 5:5
4608 prim_subreg #(
4609 .DW (1),
4610 .SwAccess(prim_subreg_pkg::SwAccessRW),
4611 .RESVAL (1'h0),
4612 .Mubi (1'b0)
4613 ) u_out_stall_endpoint_5 (
4614 .clk_i (clk_i),
4615 .rst_ni (rst_ni),
4616
4617 // from register interface
4618 .we (out_stall_we),
4619 .wd (out_stall_endpoint_5_wd),
4620
4621 // from internal hardware
4622 .de (hw2reg.out_stall[5].de),
4623 .d (hw2reg.out_stall[5].d),
4624
4625 // to internal hardware
4626 .qe (),
4627 .q (reg2hw.out_stall[5].q),
4628 .ds (),
4629
4630 // to register interface (read)
4631 .qs (out_stall_endpoint_5_qs)
4632 );
4633
4634 // F[endpoint_6]: 6:6
4635 prim_subreg #(
4636 .DW (1),
4637 .SwAccess(prim_subreg_pkg::SwAccessRW),
4638 .RESVAL (1'h0),
4639 .Mubi (1'b0)
4640 ) u_out_stall_endpoint_6 (
4641 .clk_i (clk_i),
4642 .rst_ni (rst_ni),
4643
4644 // from register interface
4645 .we (out_stall_we),
4646 .wd (out_stall_endpoint_6_wd),
4647
4648 // from internal hardware
4649 .de (hw2reg.out_stall[6].de),
4650 .d (hw2reg.out_stall[6].d),
4651
4652 // to internal hardware
4653 .qe (),
4654 .q (reg2hw.out_stall[6].q),
4655 .ds (),
4656
4657 // to register interface (read)
4658 .qs (out_stall_endpoint_6_qs)
4659 );
4660
4661 // F[endpoint_7]: 7:7
4662 prim_subreg #(
4663 .DW (1),
4664 .SwAccess(prim_subreg_pkg::SwAccessRW),
4665 .RESVAL (1'h0),
4666 .Mubi (1'b0)
4667 ) u_out_stall_endpoint_7 (
4668 .clk_i (clk_i),
4669 .rst_ni (rst_ni),
4670
4671 // from register interface
4672 .we (out_stall_we),
4673 .wd (out_stall_endpoint_7_wd),
4674
4675 // from internal hardware
4676 .de (hw2reg.out_stall[7].de),
4677 .d (hw2reg.out_stall[7].d),
4678
4679 // to internal hardware
4680 .qe (),
4681 .q (reg2hw.out_stall[7].q),
4682 .ds (),
4683
4684 // to register interface (read)
4685 .qs (out_stall_endpoint_7_qs)
4686 );
4687
4688 // F[endpoint_8]: 8:8
4689 prim_subreg #(
4690 .DW (1),
4691 .SwAccess(prim_subreg_pkg::SwAccessRW),
4692 .RESVAL (1'h0),
4693 .Mubi (1'b0)
4694 ) u_out_stall_endpoint_8 (
4695 .clk_i (clk_i),
4696 .rst_ni (rst_ni),
4697
4698 // from register interface
4699 .we (out_stall_we),
4700 .wd (out_stall_endpoint_8_wd),
4701
4702 // from internal hardware
4703 .de (hw2reg.out_stall[8].de),
4704 .d (hw2reg.out_stall[8].d),
4705
4706 // to internal hardware
4707 .qe (),
4708 .q (reg2hw.out_stall[8].q),
4709 .ds (),
4710
4711 // to register interface (read)
4712 .qs (out_stall_endpoint_8_qs)
4713 );
4714
4715 // F[endpoint_9]: 9:9
4716 prim_subreg #(
4717 .DW (1),
4718 .SwAccess(prim_subreg_pkg::SwAccessRW),
4719 .RESVAL (1'h0),
4720 .Mubi (1'b0)
4721 ) u_out_stall_endpoint_9 (
4722 .clk_i (clk_i),
4723 .rst_ni (rst_ni),
4724
4725 // from register interface
4726 .we (out_stall_we),
4727 .wd (out_stall_endpoint_9_wd),
4728
4729 // from internal hardware
4730 .de (hw2reg.out_stall[9].de),
4731 .d (hw2reg.out_stall[9].d),
4732
4733 // to internal hardware
4734 .qe (),
4735 .q (reg2hw.out_stall[9].q),
4736 .ds (),
4737
4738 // to register interface (read)
4739 .qs (out_stall_endpoint_9_qs)
4740 );
4741
4742 // F[endpoint_10]: 10:10
4743 prim_subreg #(
4744 .DW (1),
4745 .SwAccess(prim_subreg_pkg::SwAccessRW),
4746 .RESVAL (1'h0),
4747 .Mubi (1'b0)
4748 ) u_out_stall_endpoint_10 (
4749 .clk_i (clk_i),
4750 .rst_ni (rst_ni),
4751
4752 // from register interface
4753 .we (out_stall_we),
4754 .wd (out_stall_endpoint_10_wd),
4755
4756 // from internal hardware
4757 .de (hw2reg.out_stall[10].de),
4758 .d (hw2reg.out_stall[10].d),
4759
4760 // to internal hardware
4761 .qe (),
4762 .q (reg2hw.out_stall[10].q),
4763 .ds (),
4764
4765 // to register interface (read)
4766 .qs (out_stall_endpoint_10_qs)
4767 );
4768
4769 // F[endpoint_11]: 11:11
4770 prim_subreg #(
4771 .DW (1),
4772 .SwAccess(prim_subreg_pkg::SwAccessRW),
4773 .RESVAL (1'h0),
4774 .Mubi (1'b0)
4775 ) u_out_stall_endpoint_11 (
4776 .clk_i (clk_i),
4777 .rst_ni (rst_ni),
4778
4779 // from register interface
4780 .we (out_stall_we),
4781 .wd (out_stall_endpoint_11_wd),
4782
4783 // from internal hardware
4784 .de (hw2reg.out_stall[11].de),
4785 .d (hw2reg.out_stall[11].d),
4786
4787 // to internal hardware
4788 .qe (),
4789 .q (reg2hw.out_stall[11].q),
4790 .ds (),
4791
4792 // to register interface (read)
4793 .qs (out_stall_endpoint_11_qs)
4794 );
4795
4796
4797 // Subregister 0 of Multireg in_stall
4798 // R[in_stall]: V(False)
4799 // F[endpoint_0]: 0:0
4800 prim_subreg #(
4801 .DW (1),
4802 .SwAccess(prim_subreg_pkg::SwAccessRW),
4803 .RESVAL (1'h0),
4804 .Mubi (1'b0)
4805 ) u_in_stall_endpoint_0 (
4806 .clk_i (clk_i),
4807 .rst_ni (rst_ni),
4808
4809 // from register interface
4810 .we (in_stall_we),
4811 .wd (in_stall_endpoint_0_wd),
4812
4813 // from internal hardware
4814 .de (hw2reg.in_stall[0].de),
4815 .d (hw2reg.in_stall[0].d),
4816
4817 // to internal hardware
4818 .qe (),
4819 .q (reg2hw.in_stall[0].q),
4820 .ds (),
4821
4822 // to register interface (read)
4823 .qs (in_stall_endpoint_0_qs)
4824 );
4825
4826 // F[endpoint_1]: 1:1
4827 prim_subreg #(
4828 .DW (1),
4829 .SwAccess(prim_subreg_pkg::SwAccessRW),
4830 .RESVAL (1'h0),
4831 .Mubi (1'b0)
4832 ) u_in_stall_endpoint_1 (
4833 .clk_i (clk_i),
4834 .rst_ni (rst_ni),
4835
4836 // from register interface
4837 .we (in_stall_we),
4838 .wd (in_stall_endpoint_1_wd),
4839
4840 // from internal hardware
4841 .de (hw2reg.in_stall[1].de),
4842 .d (hw2reg.in_stall[1].d),
4843
4844 // to internal hardware
4845 .qe (),
4846 .q (reg2hw.in_stall[1].q),
4847 .ds (),
4848
4849 // to register interface (read)
4850 .qs (in_stall_endpoint_1_qs)
4851 );
4852
4853 // F[endpoint_2]: 2:2
4854 prim_subreg #(
4855 .DW (1),
4856 .SwAccess(prim_subreg_pkg::SwAccessRW),
4857 .RESVAL (1'h0),
4858 .Mubi (1'b0)
4859 ) u_in_stall_endpoint_2 (
4860 .clk_i (clk_i),
4861 .rst_ni (rst_ni),
4862
4863 // from register interface
4864 .we (in_stall_we),
4865 .wd (in_stall_endpoint_2_wd),
4866
4867 // from internal hardware
4868 .de (hw2reg.in_stall[2].de),
4869 .d (hw2reg.in_stall[2].d),
4870
4871 // to internal hardware
4872 .qe (),
4873 .q (reg2hw.in_stall[2].q),
4874 .ds (),
4875
4876 // to register interface (read)
4877 .qs (in_stall_endpoint_2_qs)
4878 );
4879
4880 // F[endpoint_3]: 3:3
4881 prim_subreg #(
4882 .DW (1),
4883 .SwAccess(prim_subreg_pkg::SwAccessRW),
4884 .RESVAL (1'h0),
4885 .Mubi (1'b0)
4886 ) u_in_stall_endpoint_3 (
4887 .clk_i (clk_i),
4888 .rst_ni (rst_ni),
4889
4890 // from register interface
4891 .we (in_stall_we),
4892 .wd (in_stall_endpoint_3_wd),
4893
4894 // from internal hardware
4895 .de (hw2reg.in_stall[3].de),
4896 .d (hw2reg.in_stall[3].d),
4897
4898 // to internal hardware
4899 .qe (),
4900 .q (reg2hw.in_stall[3].q),
4901 .ds (),
4902
4903 // to register interface (read)
4904 .qs (in_stall_endpoint_3_qs)
4905 );
4906
4907 // F[endpoint_4]: 4:4
4908 prim_subreg #(
4909 .DW (1),
4910 .SwAccess(prim_subreg_pkg::SwAccessRW),
4911 .RESVAL (1'h0),
4912 .Mubi (1'b0)
4913 ) u_in_stall_endpoint_4 (
4914 .clk_i (clk_i),
4915 .rst_ni (rst_ni),
4916
4917 // from register interface
4918 .we (in_stall_we),
4919 .wd (in_stall_endpoint_4_wd),
4920
4921 // from internal hardware
4922 .de (hw2reg.in_stall[4].de),
4923 .d (hw2reg.in_stall[4].d),
4924
4925 // to internal hardware
4926 .qe (),
4927 .q (reg2hw.in_stall[4].q),
4928 .ds (),
4929
4930 // to register interface (read)
4931 .qs (in_stall_endpoint_4_qs)
4932 );
4933
4934 // F[endpoint_5]: 5:5
4935 prim_subreg #(
4936 .DW (1),
4937 .SwAccess(prim_subreg_pkg::SwAccessRW),
4938 .RESVAL (1'h0),
4939 .Mubi (1'b0)
4940 ) u_in_stall_endpoint_5 (
4941 .clk_i (clk_i),
4942 .rst_ni (rst_ni),
4943
4944 // from register interface
4945 .we (in_stall_we),
4946 .wd (in_stall_endpoint_5_wd),
4947
4948 // from internal hardware
4949 .de (hw2reg.in_stall[5].de),
4950 .d (hw2reg.in_stall[5].d),
4951
4952 // to internal hardware
4953 .qe (),
4954 .q (reg2hw.in_stall[5].q),
4955 .ds (),
4956
4957 // to register interface (read)
4958 .qs (in_stall_endpoint_5_qs)
4959 );
4960
4961 // F[endpoint_6]: 6:6
4962 prim_subreg #(
4963 .DW (1),
4964 .SwAccess(prim_subreg_pkg::SwAccessRW),
4965 .RESVAL (1'h0),
4966 .Mubi (1'b0)
4967 ) u_in_stall_endpoint_6 (
4968 .clk_i (clk_i),
4969 .rst_ni (rst_ni),
4970
4971 // from register interface
4972 .we (in_stall_we),
4973 .wd (in_stall_endpoint_6_wd),
4974
4975 // from internal hardware
4976 .de (hw2reg.in_stall[6].de),
4977 .d (hw2reg.in_stall[6].d),
4978
4979 // to internal hardware
4980 .qe (),
4981 .q (reg2hw.in_stall[6].q),
4982 .ds (),
4983
4984 // to register interface (read)
4985 .qs (in_stall_endpoint_6_qs)
4986 );
4987
4988 // F[endpoint_7]: 7:7
4989 prim_subreg #(
4990 .DW (1),
4991 .SwAccess(prim_subreg_pkg::SwAccessRW),
4992 .RESVAL (1'h0),
4993 .Mubi (1'b0)
4994 ) u_in_stall_endpoint_7 (
4995 .clk_i (clk_i),
4996 .rst_ni (rst_ni),
4997
4998 // from register interface
4999 .we (in_stall_we),
5000 .wd (in_stall_endpoint_7_wd),
5001
5002 // from internal hardware
5003 .de (hw2reg.in_stall[7].de),
5004 .d (hw2reg.in_stall[7].d),
5005
5006 // to internal hardware
5007 .qe (),
5008 .q (reg2hw.in_stall[7].q),
5009 .ds (),
5010
5011 // to register interface (read)
5012 .qs (in_stall_endpoint_7_qs)
5013 );
5014
5015 // F[endpoint_8]: 8:8
5016 prim_subreg #(
5017 .DW (1),
5018 .SwAccess(prim_subreg_pkg::SwAccessRW),
5019 .RESVAL (1'h0),
5020 .Mubi (1'b0)
5021 ) u_in_stall_endpoint_8 (
5022 .clk_i (clk_i),
5023 .rst_ni (rst_ni),
5024
5025 // from register interface
5026 .we (in_stall_we),
5027 .wd (in_stall_endpoint_8_wd),
5028
5029 // from internal hardware
5030 .de (hw2reg.in_stall[8].de),
5031 .d (hw2reg.in_stall[8].d),
5032
5033 // to internal hardware
5034 .qe (),
5035 .q (reg2hw.in_stall[8].q),
5036 .ds (),
5037
5038 // to register interface (read)
5039 .qs (in_stall_endpoint_8_qs)
5040 );
5041
5042 // F[endpoint_9]: 9:9
5043 prim_subreg #(
5044 .DW (1),
5045 .SwAccess(prim_subreg_pkg::SwAccessRW),
5046 .RESVAL (1'h0),
5047 .Mubi (1'b0)
5048 ) u_in_stall_endpoint_9 (
5049 .clk_i (clk_i),
5050 .rst_ni (rst_ni),
5051
5052 // from register interface
5053 .we (in_stall_we),
5054 .wd (in_stall_endpoint_9_wd),
5055
5056 // from internal hardware
5057 .de (hw2reg.in_stall[9].de),
5058 .d (hw2reg.in_stall[9].d),
5059
5060 // to internal hardware
5061 .qe (),
5062 .q (reg2hw.in_stall[9].q),
5063 .ds (),
5064
5065 // to register interface (read)
5066 .qs (in_stall_endpoint_9_qs)
5067 );
5068
5069 // F[endpoint_10]: 10:10
5070 prim_subreg #(
5071 .DW (1),
5072 .SwAccess(prim_subreg_pkg::SwAccessRW),
5073 .RESVAL (1'h0),
5074 .Mubi (1'b0)
5075 ) u_in_stall_endpoint_10 (
5076 .clk_i (clk_i),
5077 .rst_ni (rst_ni),
5078
5079 // from register interface
5080 .we (in_stall_we),
5081 .wd (in_stall_endpoint_10_wd),
5082
5083 // from internal hardware
5084 .de (hw2reg.in_stall[10].de),
5085 .d (hw2reg.in_stall[10].d),
5086
5087 // to internal hardware
5088 .qe (),
5089 .q (reg2hw.in_stall[10].q),
5090 .ds (),
5091
5092 // to register interface (read)
5093 .qs (in_stall_endpoint_10_qs)
5094 );
5095
5096 // F[endpoint_11]: 11:11
5097 prim_subreg #(
5098 .DW (1),
5099 .SwAccess(prim_subreg_pkg::SwAccessRW),
5100 .RESVAL (1'h0),
5101 .Mubi (1'b0)
5102 ) u_in_stall_endpoint_11 (
5103 .clk_i (clk_i),
5104 .rst_ni (rst_ni),
5105
5106 // from register interface
5107 .we (in_stall_we),
5108 .wd (in_stall_endpoint_11_wd),
5109
5110 // from internal hardware
5111 .de (hw2reg.in_stall[11].de),
5112 .d (hw2reg.in_stall[11].d),
5113
5114 // to internal hardware
5115 .qe (),
5116 .q (reg2hw.in_stall[11].q),
5117 .ds (),
5118
5119 // to register interface (read)
5120 .qs (in_stall_endpoint_11_qs)
5121 );
5122
5123
5124 // Subregister 0 of Multireg configin
5125 // R[configin_0]: V(False)
5126 // F[buffer_0]: 4:0
5127 prim_subreg #(
5128 .DW (5),
5129 .SwAccess(prim_subreg_pkg::SwAccessRW),
5130 .RESVAL (5'h0),
5131 .Mubi (1'b0)
5132 ) u_configin_0_buffer_0 (
5133 .clk_i (clk_i),
5134 .rst_ni (rst_ni),
5135
5136 // from register interface
5137 .we (configin_0_we),
5138 .wd (configin_0_buffer_0_wd),
5139
5140 // from internal hardware
5141 .de (1'b0),
5142 .d ('0),
5143
5144 // to internal hardware
5145 .qe (),
5146 .q (reg2hw.configin[0].buffer.q),
5147 .ds (),
5148
5149 // to register interface (read)
5150 .qs (configin_0_buffer_0_qs)
5151 );
5152
5153 // F[size_0]: 14:8
5154 prim_subreg #(
5155 .DW (7),
5156 .SwAccess(prim_subreg_pkg::SwAccessRW),
5157 .RESVAL (7'h0),
5158 .Mubi (1'b0)
5159 ) u_configin_0_size_0 (
5160 .clk_i (clk_i),
5161 .rst_ni (rst_ni),
5162
5163 // from register interface
5164 .we (configin_0_we),
5165 .wd (configin_0_size_0_wd),
5166
5167 // from internal hardware
5168 .de (1'b0),
5169 .d ('0),
5170
5171 // to internal hardware
5172 .qe (),
5173 .q (reg2hw.configin[0].size.q),
5174 .ds (),
5175
5176 // to register interface (read)
5177 .qs (configin_0_size_0_qs)
5178 );
5179
5180 // F[sending_0]: 29:29
5181 prim_subreg #(
5182 .DW (1),
5183 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5184 .RESVAL (1'h0),
5185 .Mubi (1'b0)
5186 ) u_configin_0_sending_0 (
5187 .clk_i (clk_i),
5188 .rst_ni (rst_ni),
5189
5190 // from register interface
5191 .we (configin_0_we),
5192 .wd (configin_0_sending_0_wd),
5193
5194 // from internal hardware
5195 .de (hw2reg.configin[0].sending.de),
5196 .d (hw2reg.configin[0].sending.d),
5197
5198 // to internal hardware
5199 .qe (),
5200 .q (),
5201 .ds (),
5202
5203 // to register interface (read)
5204 .qs (configin_0_sending_0_qs)
5205 );
5206
5207 // F[pend_0]: 30:30
5208 prim_subreg #(
5209 .DW (1),
5210 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5211 .RESVAL (1'h0),
5212 .Mubi (1'b0)
5213 ) u_configin_0_pend_0 (
5214 .clk_i (clk_i),
5215 .rst_ni (rst_ni),
5216
5217 // from register interface
5218 .we (configin_0_we),
5219 .wd (configin_0_pend_0_wd),
5220
5221 // from internal hardware
5222 .de (hw2reg.configin[0].pend.de),
5223 .d (hw2reg.configin[0].pend.d),
5224
5225 // to internal hardware
5226 .qe (),
5227 .q (reg2hw.configin[0].pend.q),
5228 .ds (),
5229
5230 // to register interface (read)
5231 .qs (configin_0_pend_0_qs)
5232 );
5233
5234 // F[rdy_0]: 31:31
5235 prim_subreg #(
5236 .DW (1),
5237 .SwAccess(prim_subreg_pkg::SwAccessRW),
5238 .RESVAL (1'h0),
5239 .Mubi (1'b0)
5240 ) u_configin_0_rdy_0 (
5241 .clk_i (clk_i),
5242 .rst_ni (rst_ni),
5243
5244 // from register interface
5245 .we (configin_0_we),
5246 .wd (configin_0_rdy_0_wd),
5247
5248 // from internal hardware
5249 .de (hw2reg.configin[0].rdy.de),
5250 .d (hw2reg.configin[0].rdy.d),
5251
5252 // to internal hardware
5253 .qe (),
5254 .q (reg2hw.configin[0].rdy.q),
5255 .ds (),
5256
5257 // to register interface (read)
5258 .qs (configin_0_rdy_0_qs)
5259 );
5260
5261
5262 // Subregister 1 of Multireg configin
5263 // R[configin_1]: V(False)
5264 // F[buffer_1]: 4:0
5265 prim_subreg #(
5266 .DW (5),
5267 .SwAccess(prim_subreg_pkg::SwAccessRW),
5268 .RESVAL (5'h0),
5269 .Mubi (1'b0)
5270 ) u_configin_1_buffer_1 (
5271 .clk_i (clk_i),
5272 .rst_ni (rst_ni),
5273
5274 // from register interface
5275 .we (configin_1_we),
5276 .wd (configin_1_buffer_1_wd),
5277
5278 // from internal hardware
5279 .de (1'b0),
5280 .d ('0),
5281
5282 // to internal hardware
5283 .qe (),
5284 .q (reg2hw.configin[1].buffer.q),
5285 .ds (),
5286
5287 // to register interface (read)
5288 .qs (configin_1_buffer_1_qs)
5289 );
5290
5291 // F[size_1]: 14:8
5292 prim_subreg #(
5293 .DW (7),
5294 .SwAccess(prim_subreg_pkg::SwAccessRW),
5295 .RESVAL (7'h0),
5296 .Mubi (1'b0)
5297 ) u_configin_1_size_1 (
5298 .clk_i (clk_i),
5299 .rst_ni (rst_ni),
5300
5301 // from register interface
5302 .we (configin_1_we),
5303 .wd (configin_1_size_1_wd),
5304
5305 // from internal hardware
5306 .de (1'b0),
5307 .d ('0),
5308
5309 // to internal hardware
5310 .qe (),
5311 .q (reg2hw.configin[1].size.q),
5312 .ds (),
5313
5314 // to register interface (read)
5315 .qs (configin_1_size_1_qs)
5316 );
5317
5318 // F[sending_1]: 29:29
5319 prim_subreg #(
5320 .DW (1),
5321 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5322 .RESVAL (1'h0),
5323 .Mubi (1'b0)
5324 ) u_configin_1_sending_1 (
5325 .clk_i (clk_i),
5326 .rst_ni (rst_ni),
5327
5328 // from register interface
5329 .we (configin_1_we),
5330 .wd (configin_1_sending_1_wd),
5331
5332 // from internal hardware
5333 .de (hw2reg.configin[1].sending.de),
5334 .d (hw2reg.configin[1].sending.d),
5335
5336 // to internal hardware
5337 .qe (),
5338 .q (),
5339 .ds (),
5340
5341 // to register interface (read)
5342 .qs (configin_1_sending_1_qs)
5343 );
5344
5345 // F[pend_1]: 30:30
5346 prim_subreg #(
5347 .DW (1),
5348 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5349 .RESVAL (1'h0),
5350 .Mubi (1'b0)
5351 ) u_configin_1_pend_1 (
5352 .clk_i (clk_i),
5353 .rst_ni (rst_ni),
5354
5355 // from register interface
5356 .we (configin_1_we),
5357 .wd (configin_1_pend_1_wd),
5358
5359 // from internal hardware
5360 .de (hw2reg.configin[1].pend.de),
5361 .d (hw2reg.configin[1].pend.d),
5362
5363 // to internal hardware
5364 .qe (),
5365 .q (reg2hw.configin[1].pend.q),
5366 .ds (),
5367
5368 // to register interface (read)
5369 .qs (configin_1_pend_1_qs)
5370 );
5371
5372 // F[rdy_1]: 31:31
5373 prim_subreg #(
5374 .DW (1),
5375 .SwAccess(prim_subreg_pkg::SwAccessRW),
5376 .RESVAL (1'h0),
5377 .Mubi (1'b0)
5378 ) u_configin_1_rdy_1 (
5379 .clk_i (clk_i),
5380 .rst_ni (rst_ni),
5381
5382 // from register interface
5383 .we (configin_1_we),
5384 .wd (configin_1_rdy_1_wd),
5385
5386 // from internal hardware
5387 .de (hw2reg.configin[1].rdy.de),
5388 .d (hw2reg.configin[1].rdy.d),
5389
5390 // to internal hardware
5391 .qe (),
5392 .q (reg2hw.configin[1].rdy.q),
5393 .ds (),
5394
5395 // to register interface (read)
5396 .qs (configin_1_rdy_1_qs)
5397 );
5398
5399
5400 // Subregister 2 of Multireg configin
5401 // R[configin_2]: V(False)
5402 // F[buffer_2]: 4:0
5403 prim_subreg #(
5404 .DW (5),
5405 .SwAccess(prim_subreg_pkg::SwAccessRW),
5406 .RESVAL (5'h0),
5407 .Mubi (1'b0)
5408 ) u_configin_2_buffer_2 (
5409 .clk_i (clk_i),
5410 .rst_ni (rst_ni),
5411
5412 // from register interface
5413 .we (configin_2_we),
5414 .wd (configin_2_buffer_2_wd),
5415
5416 // from internal hardware
5417 .de (1'b0),
5418 .d ('0),
5419
5420 // to internal hardware
5421 .qe (),
5422 .q (reg2hw.configin[2].buffer.q),
5423 .ds (),
5424
5425 // to register interface (read)
5426 .qs (configin_2_buffer_2_qs)
5427 );
5428
5429 // F[size_2]: 14:8
5430 prim_subreg #(
5431 .DW (7),
5432 .SwAccess(prim_subreg_pkg::SwAccessRW),
5433 .RESVAL (7'h0),
5434 .Mubi (1'b0)
5435 ) u_configin_2_size_2 (
5436 .clk_i (clk_i),
5437 .rst_ni (rst_ni),
5438
5439 // from register interface
5440 .we (configin_2_we),
5441 .wd (configin_2_size_2_wd),
5442
5443 // from internal hardware
5444 .de (1'b0),
5445 .d ('0),
5446
5447 // to internal hardware
5448 .qe (),
5449 .q (reg2hw.configin[2].size.q),
5450 .ds (),
5451
5452 // to register interface (read)
5453 .qs (configin_2_size_2_qs)
5454 );
5455
5456 // F[sending_2]: 29:29
5457 prim_subreg #(
5458 .DW (1),
5459 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5460 .RESVAL (1'h0),
5461 .Mubi (1'b0)
5462 ) u_configin_2_sending_2 (
5463 .clk_i (clk_i),
5464 .rst_ni (rst_ni),
5465
5466 // from register interface
5467 .we (configin_2_we),
5468 .wd (configin_2_sending_2_wd),
5469
5470 // from internal hardware
5471 .de (hw2reg.configin[2].sending.de),
5472 .d (hw2reg.configin[2].sending.d),
5473
5474 // to internal hardware
5475 .qe (),
5476 .q (),
5477 .ds (),
5478
5479 // to register interface (read)
5480 .qs (configin_2_sending_2_qs)
5481 );
5482
5483 // F[pend_2]: 30:30
5484 prim_subreg #(
5485 .DW (1),
5486 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5487 .RESVAL (1'h0),
5488 .Mubi (1'b0)
5489 ) u_configin_2_pend_2 (
5490 .clk_i (clk_i),
5491 .rst_ni (rst_ni),
5492
5493 // from register interface
5494 .we (configin_2_we),
5495 .wd (configin_2_pend_2_wd),
5496
5497 // from internal hardware
5498 .de (hw2reg.configin[2].pend.de),
5499 .d (hw2reg.configin[2].pend.d),
5500
5501 // to internal hardware
5502 .qe (),
5503 .q (reg2hw.configin[2].pend.q),
5504 .ds (),
5505
5506 // to register interface (read)
5507 .qs (configin_2_pend_2_qs)
5508 );
5509
5510 // F[rdy_2]: 31:31
5511 prim_subreg #(
5512 .DW (1),
5513 .SwAccess(prim_subreg_pkg::SwAccessRW),
5514 .RESVAL (1'h0),
5515 .Mubi (1'b0)
5516 ) u_configin_2_rdy_2 (
5517 .clk_i (clk_i),
5518 .rst_ni (rst_ni),
5519
5520 // from register interface
5521 .we (configin_2_we),
5522 .wd (configin_2_rdy_2_wd),
5523
5524 // from internal hardware
5525 .de (hw2reg.configin[2].rdy.de),
5526 .d (hw2reg.configin[2].rdy.d),
5527
5528 // to internal hardware
5529 .qe (),
5530 .q (reg2hw.configin[2].rdy.q),
5531 .ds (),
5532
5533 // to register interface (read)
5534 .qs (configin_2_rdy_2_qs)
5535 );
5536
5537
5538 // Subregister 3 of Multireg configin
5539 // R[configin_3]: V(False)
5540 // F[buffer_3]: 4:0
5541 prim_subreg #(
5542 .DW (5),
5543 .SwAccess(prim_subreg_pkg::SwAccessRW),
5544 .RESVAL (5'h0),
5545 .Mubi (1'b0)
5546 ) u_configin_3_buffer_3 (
5547 .clk_i (clk_i),
5548 .rst_ni (rst_ni),
5549
5550 // from register interface
5551 .we (configin_3_we),
5552 .wd (configin_3_buffer_3_wd),
5553
5554 // from internal hardware
5555 .de (1'b0),
5556 .d ('0),
5557
5558 // to internal hardware
5559 .qe (),
5560 .q (reg2hw.configin[3].buffer.q),
5561 .ds (),
5562
5563 // to register interface (read)
5564 .qs (configin_3_buffer_3_qs)
5565 );
5566
5567 // F[size_3]: 14:8
5568 prim_subreg #(
5569 .DW (7),
5570 .SwAccess(prim_subreg_pkg::SwAccessRW),
5571 .RESVAL (7'h0),
5572 .Mubi (1'b0)
5573 ) u_configin_3_size_3 (
5574 .clk_i (clk_i),
5575 .rst_ni (rst_ni),
5576
5577 // from register interface
5578 .we (configin_3_we),
5579 .wd (configin_3_size_3_wd),
5580
5581 // from internal hardware
5582 .de (1'b0),
5583 .d ('0),
5584
5585 // to internal hardware
5586 .qe (),
5587 .q (reg2hw.configin[3].size.q),
5588 .ds (),
5589
5590 // to register interface (read)
5591 .qs (configin_3_size_3_qs)
5592 );
5593
5594 // F[sending_3]: 29:29
5595 prim_subreg #(
5596 .DW (1),
5597 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5598 .RESVAL (1'h0),
5599 .Mubi (1'b0)
5600 ) u_configin_3_sending_3 (
5601 .clk_i (clk_i),
5602 .rst_ni (rst_ni),
5603
5604 // from register interface
5605 .we (configin_3_we),
5606 .wd (configin_3_sending_3_wd),
5607
5608 // from internal hardware
5609 .de (hw2reg.configin[3].sending.de),
5610 .d (hw2reg.configin[3].sending.d),
5611
5612 // to internal hardware
5613 .qe (),
5614 .q (),
5615 .ds (),
5616
5617 // to register interface (read)
5618 .qs (configin_3_sending_3_qs)
5619 );
5620
5621 // F[pend_3]: 30:30
5622 prim_subreg #(
5623 .DW (1),
5624 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5625 .RESVAL (1'h0),
5626 .Mubi (1'b0)
5627 ) u_configin_3_pend_3 (
5628 .clk_i (clk_i),
5629 .rst_ni (rst_ni),
5630
5631 // from register interface
5632 .we (configin_3_we),
5633 .wd (configin_3_pend_3_wd),
5634
5635 // from internal hardware
5636 .de (hw2reg.configin[3].pend.de),
5637 .d (hw2reg.configin[3].pend.d),
5638
5639 // to internal hardware
5640 .qe (),
5641 .q (reg2hw.configin[3].pend.q),
5642 .ds (),
5643
5644 // to register interface (read)
5645 .qs (configin_3_pend_3_qs)
5646 );
5647
5648 // F[rdy_3]: 31:31
5649 prim_subreg #(
5650 .DW (1),
5651 .SwAccess(prim_subreg_pkg::SwAccessRW),
5652 .RESVAL (1'h0),
5653 .Mubi (1'b0)
5654 ) u_configin_3_rdy_3 (
5655 .clk_i (clk_i),
5656 .rst_ni (rst_ni),
5657
5658 // from register interface
5659 .we (configin_3_we),
5660 .wd (configin_3_rdy_3_wd),
5661
5662 // from internal hardware
5663 .de (hw2reg.configin[3].rdy.de),
5664 .d (hw2reg.configin[3].rdy.d),
5665
5666 // to internal hardware
5667 .qe (),
5668 .q (reg2hw.configin[3].rdy.q),
5669 .ds (),
5670
5671 // to register interface (read)
5672 .qs (configin_3_rdy_3_qs)
5673 );
5674
5675
5676 // Subregister 4 of Multireg configin
5677 // R[configin_4]: V(False)
5678 // F[buffer_4]: 4:0
5679 prim_subreg #(
5680 .DW (5),
5681 .SwAccess(prim_subreg_pkg::SwAccessRW),
5682 .RESVAL (5'h0),
5683 .Mubi (1'b0)
5684 ) u_configin_4_buffer_4 (
5685 .clk_i (clk_i),
5686 .rst_ni (rst_ni),
5687
5688 // from register interface
5689 .we (configin_4_we),
5690 .wd (configin_4_buffer_4_wd),
5691
5692 // from internal hardware
5693 .de (1'b0),
5694 .d ('0),
5695
5696 // to internal hardware
5697 .qe (),
5698 .q (reg2hw.configin[4].buffer.q),
5699 .ds (),
5700
5701 // to register interface (read)
5702 .qs (configin_4_buffer_4_qs)
5703 );
5704
5705 // F[size_4]: 14:8
5706 prim_subreg #(
5707 .DW (7),
5708 .SwAccess(prim_subreg_pkg::SwAccessRW),
5709 .RESVAL (7'h0),
5710 .Mubi (1'b0)
5711 ) u_configin_4_size_4 (
5712 .clk_i (clk_i),
5713 .rst_ni (rst_ni),
5714
5715 // from register interface
5716 .we (configin_4_we),
5717 .wd (configin_4_size_4_wd),
5718
5719 // from internal hardware
5720 .de (1'b0),
5721 .d ('0),
5722
5723 // to internal hardware
5724 .qe (),
5725 .q (reg2hw.configin[4].size.q),
5726 .ds (),
5727
5728 // to register interface (read)
5729 .qs (configin_4_size_4_qs)
5730 );
5731
5732 // F[sending_4]: 29:29
5733 prim_subreg #(
5734 .DW (1),
5735 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5736 .RESVAL (1'h0),
5737 .Mubi (1'b0)
5738 ) u_configin_4_sending_4 (
5739 .clk_i (clk_i),
5740 .rst_ni (rst_ni),
5741
5742 // from register interface
5743 .we (configin_4_we),
5744 .wd (configin_4_sending_4_wd),
5745
5746 // from internal hardware
5747 .de (hw2reg.configin[4].sending.de),
5748 .d (hw2reg.configin[4].sending.d),
5749
5750 // to internal hardware
5751 .qe (),
5752 .q (),
5753 .ds (),
5754
5755 // to register interface (read)
5756 .qs (configin_4_sending_4_qs)
5757 );
5758
5759 // F[pend_4]: 30:30
5760 prim_subreg #(
5761 .DW (1),
5762 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5763 .RESVAL (1'h0),
5764 .Mubi (1'b0)
5765 ) u_configin_4_pend_4 (
5766 .clk_i (clk_i),
5767 .rst_ni (rst_ni),
5768
5769 // from register interface
5770 .we (configin_4_we),
5771 .wd (configin_4_pend_4_wd),
5772
5773 // from internal hardware
5774 .de (hw2reg.configin[4].pend.de),
5775 .d (hw2reg.configin[4].pend.d),
5776
5777 // to internal hardware
5778 .qe (),
5779 .q (reg2hw.configin[4].pend.q),
5780 .ds (),
5781
5782 // to register interface (read)
5783 .qs (configin_4_pend_4_qs)
5784 );
5785
5786 // F[rdy_4]: 31:31
5787 prim_subreg #(
5788 .DW (1),
5789 .SwAccess(prim_subreg_pkg::SwAccessRW),
5790 .RESVAL (1'h0),
5791 .Mubi (1'b0)
5792 ) u_configin_4_rdy_4 (
5793 .clk_i (clk_i),
5794 .rst_ni (rst_ni),
5795
5796 // from register interface
5797 .we (configin_4_we),
5798 .wd (configin_4_rdy_4_wd),
5799
5800 // from internal hardware
5801 .de (hw2reg.configin[4].rdy.de),
5802 .d (hw2reg.configin[4].rdy.d),
5803
5804 // to internal hardware
5805 .qe (),
5806 .q (reg2hw.configin[4].rdy.q),
5807 .ds (),
5808
5809 // to register interface (read)
5810 .qs (configin_4_rdy_4_qs)
5811 );
5812
5813
5814 // Subregister 5 of Multireg configin
5815 // R[configin_5]: V(False)
5816 // F[buffer_5]: 4:0
5817 prim_subreg #(
5818 .DW (5),
5819 .SwAccess(prim_subreg_pkg::SwAccessRW),
5820 .RESVAL (5'h0),
5821 .Mubi (1'b0)
5822 ) u_configin_5_buffer_5 (
5823 .clk_i (clk_i),
5824 .rst_ni (rst_ni),
5825
5826 // from register interface
5827 .we (configin_5_we),
5828 .wd (configin_5_buffer_5_wd),
5829
5830 // from internal hardware
5831 .de (1'b0),
5832 .d ('0),
5833
5834 // to internal hardware
5835 .qe (),
5836 .q (reg2hw.configin[5].buffer.q),
5837 .ds (),
5838
5839 // to register interface (read)
5840 .qs (configin_5_buffer_5_qs)
5841 );
5842
5843 // F[size_5]: 14:8
5844 prim_subreg #(
5845 .DW (7),
5846 .SwAccess(prim_subreg_pkg::SwAccessRW),
5847 .RESVAL (7'h0),
5848 .Mubi (1'b0)
5849 ) u_configin_5_size_5 (
5850 .clk_i (clk_i),
5851 .rst_ni (rst_ni),
5852
5853 // from register interface
5854 .we (configin_5_we),
5855 .wd (configin_5_size_5_wd),
5856
5857 // from internal hardware
5858 .de (1'b0),
5859 .d ('0),
5860
5861 // to internal hardware
5862 .qe (),
5863 .q (reg2hw.configin[5].size.q),
5864 .ds (),
5865
5866 // to register interface (read)
5867 .qs (configin_5_size_5_qs)
5868 );
5869
5870 // F[sending_5]: 29:29
5871 prim_subreg #(
5872 .DW (1),
5873 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5874 .RESVAL (1'h0),
5875 .Mubi (1'b0)
5876 ) u_configin_5_sending_5 (
5877 .clk_i (clk_i),
5878 .rst_ni (rst_ni),
5879
5880 // from register interface
5881 .we (configin_5_we),
5882 .wd (configin_5_sending_5_wd),
5883
5884 // from internal hardware
5885 .de (hw2reg.configin[5].sending.de),
5886 .d (hw2reg.configin[5].sending.d),
5887
5888 // to internal hardware
5889 .qe (),
5890 .q (),
5891 .ds (),
5892
5893 // to register interface (read)
5894 .qs (configin_5_sending_5_qs)
5895 );
5896
5897 // F[pend_5]: 30:30
5898 prim_subreg #(
5899 .DW (1),
5900 .SwAccess(prim_subreg_pkg::SwAccessW1C),
5901 .RESVAL (1'h0),
5902 .Mubi (1'b0)
5903 ) u_configin_5_pend_5 (
5904 .clk_i (clk_i),
5905 .rst_ni (rst_ni),
5906
5907 // from register interface
5908 .we (configin_5_we),
5909 .wd (configin_5_pend_5_wd),
5910
5911 // from internal hardware
5912 .de (hw2reg.configin[5].pend.de),
5913 .d (hw2reg.configin[5].pend.d),
5914
5915 // to internal hardware
5916 .qe (),
5917 .q (reg2hw.configin[5].pend.q),
5918 .ds (),
5919
5920 // to register interface (read)
5921 .qs (configin_5_pend_5_qs)
5922 );
5923
5924 // F[rdy_5]: 31:31
5925 prim_subreg #(
5926 .DW (1),
5927 .SwAccess(prim_subreg_pkg::SwAccessRW),
5928 .RESVAL (1'h0),
5929 .Mubi (1'b0)
5930 ) u_configin_5_rdy_5 (
5931 .clk_i (clk_i),
5932 .rst_ni (rst_ni),
5933
5934 // from register interface
5935 .we (configin_5_we),
5936 .wd (configin_5_rdy_5_wd),
5937
5938 // from internal hardware
5939 .de (hw2reg.configin[5].rdy.de),
5940 .d (hw2reg.configin[5].rdy.d),
5941
5942 // to internal hardware
5943 .qe (),
5944 .q (reg2hw.configin[5].rdy.q),
5945 .ds (),
5946
5947 // to register interface (read)
5948 .qs (configin_5_rdy_5_qs)
5949 );
5950
5951
5952 // Subregister 6 of Multireg configin
5953 // R[configin_6]: V(False)
5954 // F[buffer_6]: 4:0
5955 prim_subreg #(
5956 .DW (5),
5957 .SwAccess(prim_subreg_pkg::SwAccessRW),
5958 .RESVAL (5'h0),
5959 .Mubi (1'b0)
5960 ) u_configin_6_buffer_6 (
5961 .clk_i (clk_i),
5962 .rst_ni (rst_ni),
5963
5964 // from register interface
5965 .we (configin_6_we),
5966 .wd (configin_6_buffer_6_wd),
5967
5968 // from internal hardware
5969 .de (1'b0),
5970 .d ('0),
5971
5972 // to internal hardware
5973 .qe (),
5974 .q (reg2hw.configin[6].buffer.q),
5975 .ds (),
5976
5977 // to register interface (read)
5978 .qs (configin_6_buffer_6_qs)
5979 );
5980
5981 // F[size_6]: 14:8
5982 prim_subreg #(
5983 .DW (7),
5984 .SwAccess(prim_subreg_pkg::SwAccessRW),
5985 .RESVAL (7'h0),
5986 .Mubi (1'b0)
5987 ) u_configin_6_size_6 (
5988 .clk_i (clk_i),
5989 .rst_ni (rst_ni),
5990
5991 // from register interface
5992 .we (configin_6_we),
5993 .wd (configin_6_size_6_wd),
5994
5995 // from internal hardware
5996 .de (1'b0),
5997 .d ('0),
5998
5999 // to internal hardware
6000 .qe (),
6001 .q (reg2hw.configin[6].size.q),
6002 .ds (),
6003
6004 // to register interface (read)
6005 .qs (configin_6_size_6_qs)
6006 );
6007
6008 // F[sending_6]: 29:29
6009 prim_subreg #(
6010 .DW (1),
6011 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6012 .RESVAL (1'h0),
6013 .Mubi (1'b0)
6014 ) u_configin_6_sending_6 (
6015 .clk_i (clk_i),
6016 .rst_ni (rst_ni),
6017
6018 // from register interface
6019 .we (configin_6_we),
6020 .wd (configin_6_sending_6_wd),
6021
6022 // from internal hardware
6023 .de (hw2reg.configin[6].sending.de),
6024 .d (hw2reg.configin[6].sending.d),
6025
6026 // to internal hardware
6027 .qe (),
6028 .q (),
6029 .ds (),
6030
6031 // to register interface (read)
6032 .qs (configin_6_sending_6_qs)
6033 );
6034
6035 // F[pend_6]: 30:30
6036 prim_subreg #(
6037 .DW (1),
6038 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6039 .RESVAL (1'h0),
6040 .Mubi (1'b0)
6041 ) u_configin_6_pend_6 (
6042 .clk_i (clk_i),
6043 .rst_ni (rst_ni),
6044
6045 // from register interface
6046 .we (configin_6_we),
6047 .wd (configin_6_pend_6_wd),
6048
6049 // from internal hardware
6050 .de (hw2reg.configin[6].pend.de),
6051 .d (hw2reg.configin[6].pend.d),
6052
6053 // to internal hardware
6054 .qe (),
6055 .q (reg2hw.configin[6].pend.q),
6056 .ds (),
6057
6058 // to register interface (read)
6059 .qs (configin_6_pend_6_qs)
6060 );
6061
6062 // F[rdy_6]: 31:31
6063 prim_subreg #(
6064 .DW (1),
6065 .SwAccess(prim_subreg_pkg::SwAccessRW),
6066 .RESVAL (1'h0),
6067 .Mubi (1'b0)
6068 ) u_configin_6_rdy_6 (
6069 .clk_i (clk_i),
6070 .rst_ni (rst_ni),
6071
6072 // from register interface
6073 .we (configin_6_we),
6074 .wd (configin_6_rdy_6_wd),
6075
6076 // from internal hardware
6077 .de (hw2reg.configin[6].rdy.de),
6078 .d (hw2reg.configin[6].rdy.d),
6079
6080 // to internal hardware
6081 .qe (),
6082 .q (reg2hw.configin[6].rdy.q),
6083 .ds (),
6084
6085 // to register interface (read)
6086 .qs (configin_6_rdy_6_qs)
6087 );
6088
6089
6090 // Subregister 7 of Multireg configin
6091 // R[configin_7]: V(False)
6092 // F[buffer_7]: 4:0
6093 prim_subreg #(
6094 .DW (5),
6095 .SwAccess(prim_subreg_pkg::SwAccessRW),
6096 .RESVAL (5'h0),
6097 .Mubi (1'b0)
6098 ) u_configin_7_buffer_7 (
6099 .clk_i (clk_i),
6100 .rst_ni (rst_ni),
6101
6102 // from register interface
6103 .we (configin_7_we),
6104 .wd (configin_7_buffer_7_wd),
6105
6106 // from internal hardware
6107 .de (1'b0),
6108 .d ('0),
6109
6110 // to internal hardware
6111 .qe (),
6112 .q (reg2hw.configin[7].buffer.q),
6113 .ds (),
6114
6115 // to register interface (read)
6116 .qs (configin_7_buffer_7_qs)
6117 );
6118
6119 // F[size_7]: 14:8
6120 prim_subreg #(
6121 .DW (7),
6122 .SwAccess(prim_subreg_pkg::SwAccessRW),
6123 .RESVAL (7'h0),
6124 .Mubi (1'b0)
6125 ) u_configin_7_size_7 (
6126 .clk_i (clk_i),
6127 .rst_ni (rst_ni),
6128
6129 // from register interface
6130 .we (configin_7_we),
6131 .wd (configin_7_size_7_wd),
6132
6133 // from internal hardware
6134 .de (1'b0),
6135 .d ('0),
6136
6137 // to internal hardware
6138 .qe (),
6139 .q (reg2hw.configin[7].size.q),
6140 .ds (),
6141
6142 // to register interface (read)
6143 .qs (configin_7_size_7_qs)
6144 );
6145
6146 // F[sending_7]: 29:29
6147 prim_subreg #(
6148 .DW (1),
6149 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6150 .RESVAL (1'h0),
6151 .Mubi (1'b0)
6152 ) u_configin_7_sending_7 (
6153 .clk_i (clk_i),
6154 .rst_ni (rst_ni),
6155
6156 // from register interface
6157 .we (configin_7_we),
6158 .wd (configin_7_sending_7_wd),
6159
6160 // from internal hardware
6161 .de (hw2reg.configin[7].sending.de),
6162 .d (hw2reg.configin[7].sending.d),
6163
6164 // to internal hardware
6165 .qe (),
6166 .q (),
6167 .ds (),
6168
6169 // to register interface (read)
6170 .qs (configin_7_sending_7_qs)
6171 );
6172
6173 // F[pend_7]: 30:30
6174 prim_subreg #(
6175 .DW (1),
6176 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6177 .RESVAL (1'h0),
6178 .Mubi (1'b0)
6179 ) u_configin_7_pend_7 (
6180 .clk_i (clk_i),
6181 .rst_ni (rst_ni),
6182
6183 // from register interface
6184 .we (configin_7_we),
6185 .wd (configin_7_pend_7_wd),
6186
6187 // from internal hardware
6188 .de (hw2reg.configin[7].pend.de),
6189 .d (hw2reg.configin[7].pend.d),
6190
6191 // to internal hardware
6192 .qe (),
6193 .q (reg2hw.configin[7].pend.q),
6194 .ds (),
6195
6196 // to register interface (read)
6197 .qs (configin_7_pend_7_qs)
6198 );
6199
6200 // F[rdy_7]: 31:31
6201 prim_subreg #(
6202 .DW (1),
6203 .SwAccess(prim_subreg_pkg::SwAccessRW),
6204 .RESVAL (1'h0),
6205 .Mubi (1'b0)
6206 ) u_configin_7_rdy_7 (
6207 .clk_i (clk_i),
6208 .rst_ni (rst_ni),
6209
6210 // from register interface
6211 .we (configin_7_we),
6212 .wd (configin_7_rdy_7_wd),
6213
6214 // from internal hardware
6215 .de (hw2reg.configin[7].rdy.de),
6216 .d (hw2reg.configin[7].rdy.d),
6217
6218 // to internal hardware
6219 .qe (),
6220 .q (reg2hw.configin[7].rdy.q),
6221 .ds (),
6222
6223 // to register interface (read)
6224 .qs (configin_7_rdy_7_qs)
6225 );
6226
6227
6228 // Subregister 8 of Multireg configin
6229 // R[configin_8]: V(False)
6230 // F[buffer_8]: 4:0
6231 prim_subreg #(
6232 .DW (5),
6233 .SwAccess(prim_subreg_pkg::SwAccessRW),
6234 .RESVAL (5'h0),
6235 .Mubi (1'b0)
6236 ) u_configin_8_buffer_8 (
6237 .clk_i (clk_i),
6238 .rst_ni (rst_ni),
6239
6240 // from register interface
6241 .we (configin_8_we),
6242 .wd (configin_8_buffer_8_wd),
6243
6244 // from internal hardware
6245 .de (1'b0),
6246 .d ('0),
6247
6248 // to internal hardware
6249 .qe (),
6250 .q (reg2hw.configin[8].buffer.q),
6251 .ds (),
6252
6253 // to register interface (read)
6254 .qs (configin_8_buffer_8_qs)
6255 );
6256
6257 // F[size_8]: 14:8
6258 prim_subreg #(
6259 .DW (7),
6260 .SwAccess(prim_subreg_pkg::SwAccessRW),
6261 .RESVAL (7'h0),
6262 .Mubi (1'b0)
6263 ) u_configin_8_size_8 (
6264 .clk_i (clk_i),
6265 .rst_ni (rst_ni),
6266
6267 // from register interface
6268 .we (configin_8_we),
6269 .wd (configin_8_size_8_wd),
6270
6271 // from internal hardware
6272 .de (1'b0),
6273 .d ('0),
6274
6275 // to internal hardware
6276 .qe (),
6277 .q (reg2hw.configin[8].size.q),
6278 .ds (),
6279
6280 // to register interface (read)
6281 .qs (configin_8_size_8_qs)
6282 );
6283
6284 // F[sending_8]: 29:29
6285 prim_subreg #(
6286 .DW (1),
6287 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6288 .RESVAL (1'h0),
6289 .Mubi (1'b0)
6290 ) u_configin_8_sending_8 (
6291 .clk_i (clk_i),
6292 .rst_ni (rst_ni),
6293
6294 // from register interface
6295 .we (configin_8_we),
6296 .wd (configin_8_sending_8_wd),
6297
6298 // from internal hardware
6299 .de (hw2reg.configin[8].sending.de),
6300 .d (hw2reg.configin[8].sending.d),
6301
6302 // to internal hardware
6303 .qe (),
6304 .q (),
6305 .ds (),
6306
6307 // to register interface (read)
6308 .qs (configin_8_sending_8_qs)
6309 );
6310
6311 // F[pend_8]: 30:30
6312 prim_subreg #(
6313 .DW (1),
6314 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6315 .RESVAL (1'h0),
6316 .Mubi (1'b0)
6317 ) u_configin_8_pend_8 (
6318 .clk_i (clk_i),
6319 .rst_ni (rst_ni),
6320
6321 // from register interface
6322 .we (configin_8_we),
6323 .wd (configin_8_pend_8_wd),
6324
6325 // from internal hardware
6326 .de (hw2reg.configin[8].pend.de),
6327 .d (hw2reg.configin[8].pend.d),
6328
6329 // to internal hardware
6330 .qe (),
6331 .q (reg2hw.configin[8].pend.q),
6332 .ds (),
6333
6334 // to register interface (read)
6335 .qs (configin_8_pend_8_qs)
6336 );
6337
6338 // F[rdy_8]: 31:31
6339 prim_subreg #(
6340 .DW (1),
6341 .SwAccess(prim_subreg_pkg::SwAccessRW),
6342 .RESVAL (1'h0),
6343 .Mubi (1'b0)
6344 ) u_configin_8_rdy_8 (
6345 .clk_i (clk_i),
6346 .rst_ni (rst_ni),
6347
6348 // from register interface
6349 .we (configin_8_we),
6350 .wd (configin_8_rdy_8_wd),
6351
6352 // from internal hardware
6353 .de (hw2reg.configin[8].rdy.de),
6354 .d (hw2reg.configin[8].rdy.d),
6355
6356 // to internal hardware
6357 .qe (),
6358 .q (reg2hw.configin[8].rdy.q),
6359 .ds (),
6360
6361 // to register interface (read)
6362 .qs (configin_8_rdy_8_qs)
6363 );
6364
6365
6366 // Subregister 9 of Multireg configin
6367 // R[configin_9]: V(False)
6368 // F[buffer_9]: 4:0
6369 prim_subreg #(
6370 .DW (5),
6371 .SwAccess(prim_subreg_pkg::SwAccessRW),
6372 .RESVAL (5'h0),
6373 .Mubi (1'b0)
6374 ) u_configin_9_buffer_9 (
6375 .clk_i (clk_i),
6376 .rst_ni (rst_ni),
6377
6378 // from register interface
6379 .we (configin_9_we),
6380 .wd (configin_9_buffer_9_wd),
6381
6382 // from internal hardware
6383 .de (1'b0),
6384 .d ('0),
6385
6386 // to internal hardware
6387 .qe (),
6388 .q (reg2hw.configin[9].buffer.q),
6389 .ds (),
6390
6391 // to register interface (read)
6392 .qs (configin_9_buffer_9_qs)
6393 );
6394
6395 // F[size_9]: 14:8
6396 prim_subreg #(
6397 .DW (7),
6398 .SwAccess(prim_subreg_pkg::SwAccessRW),
6399 .RESVAL (7'h0),
6400 .Mubi (1'b0)
6401 ) u_configin_9_size_9 (
6402 .clk_i (clk_i),
6403 .rst_ni (rst_ni),
6404
6405 // from register interface
6406 .we (configin_9_we),
6407 .wd (configin_9_size_9_wd),
6408
6409 // from internal hardware
6410 .de (1'b0),
6411 .d ('0),
6412
6413 // to internal hardware
6414 .qe (),
6415 .q (reg2hw.configin[9].size.q),
6416 .ds (),
6417
6418 // to register interface (read)
6419 .qs (configin_9_size_9_qs)
6420 );
6421
6422 // F[sending_9]: 29:29
6423 prim_subreg #(
6424 .DW (1),
6425 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6426 .RESVAL (1'h0),
6427 .Mubi (1'b0)
6428 ) u_configin_9_sending_9 (
6429 .clk_i (clk_i),
6430 .rst_ni (rst_ni),
6431
6432 // from register interface
6433 .we (configin_9_we),
6434 .wd (configin_9_sending_9_wd),
6435
6436 // from internal hardware
6437 .de (hw2reg.configin[9].sending.de),
6438 .d (hw2reg.configin[9].sending.d),
6439
6440 // to internal hardware
6441 .qe (),
6442 .q (),
6443 .ds (),
6444
6445 // to register interface (read)
6446 .qs (configin_9_sending_9_qs)
6447 );
6448
6449 // F[pend_9]: 30:30
6450 prim_subreg #(
6451 .DW (1),
6452 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6453 .RESVAL (1'h0),
6454 .Mubi (1'b0)
6455 ) u_configin_9_pend_9 (
6456 .clk_i (clk_i),
6457 .rst_ni (rst_ni),
6458
6459 // from register interface
6460 .we (configin_9_we),
6461 .wd (configin_9_pend_9_wd),
6462
6463 // from internal hardware
6464 .de (hw2reg.configin[9].pend.de),
6465 .d (hw2reg.configin[9].pend.d),
6466
6467 // to internal hardware
6468 .qe (),
6469 .q (reg2hw.configin[9].pend.q),
6470 .ds (),
6471
6472 // to register interface (read)
6473 .qs (configin_9_pend_9_qs)
6474 );
6475
6476 // F[rdy_9]: 31:31
6477 prim_subreg #(
6478 .DW (1),
6479 .SwAccess(prim_subreg_pkg::SwAccessRW),
6480 .RESVAL (1'h0),
6481 .Mubi (1'b0)
6482 ) u_configin_9_rdy_9 (
6483 .clk_i (clk_i),
6484 .rst_ni (rst_ni),
6485
6486 // from register interface
6487 .we (configin_9_we),
6488 .wd (configin_9_rdy_9_wd),
6489
6490 // from internal hardware
6491 .de (hw2reg.configin[9].rdy.de),
6492 .d (hw2reg.configin[9].rdy.d),
6493
6494 // to internal hardware
6495 .qe (),
6496 .q (reg2hw.configin[9].rdy.q),
6497 .ds (),
6498
6499 // to register interface (read)
6500 .qs (configin_9_rdy_9_qs)
6501 );
6502
6503
6504 // Subregister 10 of Multireg configin
6505 // R[configin_10]: V(False)
6506 // F[buffer_10]: 4:0
6507 prim_subreg #(
6508 .DW (5),
6509 .SwAccess(prim_subreg_pkg::SwAccessRW),
6510 .RESVAL (5'h0),
6511 .Mubi (1'b0)
6512 ) u_configin_10_buffer_10 (
6513 .clk_i (clk_i),
6514 .rst_ni (rst_ni),
6515
6516 // from register interface
6517 .we (configin_10_we),
6518 .wd (configin_10_buffer_10_wd),
6519
6520 // from internal hardware
6521 .de (1'b0),
6522 .d ('0),
6523
6524 // to internal hardware
6525 .qe (),
6526 .q (reg2hw.configin[10].buffer.q),
6527 .ds (),
6528
6529 // to register interface (read)
6530 .qs (configin_10_buffer_10_qs)
6531 );
6532
6533 // F[size_10]: 14:8
6534 prim_subreg #(
6535 .DW (7),
6536 .SwAccess(prim_subreg_pkg::SwAccessRW),
6537 .RESVAL (7'h0),
6538 .Mubi (1'b0)
6539 ) u_configin_10_size_10 (
6540 .clk_i (clk_i),
6541 .rst_ni (rst_ni),
6542
6543 // from register interface
6544 .we (configin_10_we),
6545 .wd (configin_10_size_10_wd),
6546
6547 // from internal hardware
6548 .de (1'b0),
6549 .d ('0),
6550
6551 // to internal hardware
6552 .qe (),
6553 .q (reg2hw.configin[10].size.q),
6554 .ds (),
6555
6556 // to register interface (read)
6557 .qs (configin_10_size_10_qs)
6558 );
6559
6560 // F[sending_10]: 29:29
6561 prim_subreg #(
6562 .DW (1),
6563 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6564 .RESVAL (1'h0),
6565 .Mubi (1'b0)
6566 ) u_configin_10_sending_10 (
6567 .clk_i (clk_i),
6568 .rst_ni (rst_ni),
6569
6570 // from register interface
6571 .we (configin_10_we),
6572 .wd (configin_10_sending_10_wd),
6573
6574 // from internal hardware
6575 .de (hw2reg.configin[10].sending.de),
6576 .d (hw2reg.configin[10].sending.d),
6577
6578 // to internal hardware
6579 .qe (),
6580 .q (),
6581 .ds (),
6582
6583 // to register interface (read)
6584 .qs (configin_10_sending_10_qs)
6585 );
6586
6587 // F[pend_10]: 30:30
6588 prim_subreg #(
6589 .DW (1),
6590 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6591 .RESVAL (1'h0),
6592 .Mubi (1'b0)
6593 ) u_configin_10_pend_10 (
6594 .clk_i (clk_i),
6595 .rst_ni (rst_ni),
6596
6597 // from register interface
6598 .we (configin_10_we),
6599 .wd (configin_10_pend_10_wd),
6600
6601 // from internal hardware
6602 .de (hw2reg.configin[10].pend.de),
6603 .d (hw2reg.configin[10].pend.d),
6604
6605 // to internal hardware
6606 .qe (),
6607 .q (reg2hw.configin[10].pend.q),
6608 .ds (),
6609
6610 // to register interface (read)
6611 .qs (configin_10_pend_10_qs)
6612 );
6613
6614 // F[rdy_10]: 31:31
6615 prim_subreg #(
6616 .DW (1),
6617 .SwAccess(prim_subreg_pkg::SwAccessRW),
6618 .RESVAL (1'h0),
6619 .Mubi (1'b0)
6620 ) u_configin_10_rdy_10 (
6621 .clk_i (clk_i),
6622 .rst_ni (rst_ni),
6623
6624 // from register interface
6625 .we (configin_10_we),
6626 .wd (configin_10_rdy_10_wd),
6627
6628 // from internal hardware
6629 .de (hw2reg.configin[10].rdy.de),
6630 .d (hw2reg.configin[10].rdy.d),
6631
6632 // to internal hardware
6633 .qe (),
6634 .q (reg2hw.configin[10].rdy.q),
6635 .ds (),
6636
6637 // to register interface (read)
6638 .qs (configin_10_rdy_10_qs)
6639 );
6640
6641
6642 // Subregister 11 of Multireg configin
6643 // R[configin_11]: V(False)
6644 // F[buffer_11]: 4:0
6645 prim_subreg #(
6646 .DW (5),
6647 .SwAccess(prim_subreg_pkg::SwAccessRW),
6648 .RESVAL (5'h0),
6649 .Mubi (1'b0)
6650 ) u_configin_11_buffer_11 (
6651 .clk_i (clk_i),
6652 .rst_ni (rst_ni),
6653
6654 // from register interface
6655 .we (configin_11_we),
6656 .wd (configin_11_buffer_11_wd),
6657
6658 // from internal hardware
6659 .de (1'b0),
6660 .d ('0),
6661
6662 // to internal hardware
6663 .qe (),
6664 .q (reg2hw.configin[11].buffer.q),
6665 .ds (),
6666
6667 // to register interface (read)
6668 .qs (configin_11_buffer_11_qs)
6669 );
6670
6671 // F[size_11]: 14:8
6672 prim_subreg #(
6673 .DW (7),
6674 .SwAccess(prim_subreg_pkg::SwAccessRW),
6675 .RESVAL (7'h0),
6676 .Mubi (1'b0)
6677 ) u_configin_11_size_11 (
6678 .clk_i (clk_i),
6679 .rst_ni (rst_ni),
6680
6681 // from register interface
6682 .we (configin_11_we),
6683 .wd (configin_11_size_11_wd),
6684
6685 // from internal hardware
6686 .de (1'b0),
6687 .d ('0),
6688
6689 // to internal hardware
6690 .qe (),
6691 .q (reg2hw.configin[11].size.q),
6692 .ds (),
6693
6694 // to register interface (read)
6695 .qs (configin_11_size_11_qs)
6696 );
6697
6698 // F[sending_11]: 29:29
6699 prim_subreg #(
6700 .DW (1),
6701 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6702 .RESVAL (1'h0),
6703 .Mubi (1'b0)
6704 ) u_configin_11_sending_11 (
6705 .clk_i (clk_i),
6706 .rst_ni (rst_ni),
6707
6708 // from register interface
6709 .we (configin_11_we),
6710 .wd (configin_11_sending_11_wd),
6711
6712 // from internal hardware
6713 .de (hw2reg.configin[11].sending.de),
6714 .d (hw2reg.configin[11].sending.d),
6715
6716 // to internal hardware
6717 .qe (),
6718 .q (),
6719 .ds (),
6720
6721 // to register interface (read)
6722 .qs (configin_11_sending_11_qs)
6723 );
6724
6725 // F[pend_11]: 30:30
6726 prim_subreg #(
6727 .DW (1),
6728 .SwAccess(prim_subreg_pkg::SwAccessW1C),
6729 .RESVAL (1'h0),
6730 .Mubi (1'b0)
6731 ) u_configin_11_pend_11 (
6732 .clk_i (clk_i),
6733 .rst_ni (rst_ni),
6734
6735 // from register interface
6736 .we (configin_11_we),
6737 .wd (configin_11_pend_11_wd),
6738
6739 // from internal hardware
6740 .de (hw2reg.configin[11].pend.de),
6741 .d (hw2reg.configin[11].pend.d),
6742
6743 // to internal hardware
6744 .qe (),
6745 .q (reg2hw.configin[11].pend.q),
6746 .ds (),
6747
6748 // to register interface (read)
6749 .qs (configin_11_pend_11_qs)
6750 );
6751
6752 // F[rdy_11]: 31:31
6753 prim_subreg #(
6754 .DW (1),
6755 .SwAccess(prim_subreg_pkg::SwAccessRW),
6756 .RESVAL (1'h0),
6757 .Mubi (1'b0)
6758 ) u_configin_11_rdy_11 (
6759 .clk_i (clk_i),
6760 .rst_ni (rst_ni),
6761
6762 // from register interface
6763 .we (configin_11_we),
6764 .wd (configin_11_rdy_11_wd),
6765
6766 // from internal hardware
6767 .de (hw2reg.configin[11].rdy.de),
6768 .d (hw2reg.configin[11].rdy.d),
6769
6770 // to internal hardware
6771 .qe (),
6772 .q (reg2hw.configin[11].rdy.q),
6773 .ds (),
6774
6775 // to register interface (read)
6776 .qs (configin_11_rdy_11_qs)
6777 );
6778
6779
6780 // Subregister 0 of Multireg out_iso
6781 // R[out_iso]: V(False)
6782 // F[iso_0]: 0:0
6783 prim_subreg #(
6784 .DW (1),
6785 .SwAccess(prim_subreg_pkg::SwAccessRW),
6786 .RESVAL (1'h0),
6787 .Mubi (1'b0)
6788 ) u_out_iso_iso_0 (
6789 .clk_i (clk_i),
6790 .rst_ni (rst_ni),
6791
6792 // from register interface
6793 .we (out_iso_we),
6794 .wd (out_iso_iso_0_wd),
6795
6796 // from internal hardware
6797 .de (1'b0),
6798 .d ('0),
6799
6800 // to internal hardware
6801 .qe (),
6802 .q (reg2hw.out_iso[0].q),
6803 .ds (),
6804
6805 // to register interface (read)
6806 .qs (out_iso_iso_0_qs)
6807 );
6808
6809 // F[iso_1]: 1:1
6810 prim_subreg #(
6811 .DW (1),
6812 .SwAccess(prim_subreg_pkg::SwAccessRW),
6813 .RESVAL (1'h0),
6814 .Mubi (1'b0)
6815 ) u_out_iso_iso_1 (
6816 .clk_i (clk_i),
6817 .rst_ni (rst_ni),
6818
6819 // from register interface
6820 .we (out_iso_we),
6821 .wd (out_iso_iso_1_wd),
6822
6823 // from internal hardware
6824 .de (1'b0),
6825 .d ('0),
6826
6827 // to internal hardware
6828 .qe (),
6829 .q (reg2hw.out_iso[1].q),
6830 .ds (),
6831
6832 // to register interface (read)
6833 .qs (out_iso_iso_1_qs)
6834 );
6835
6836 // F[iso_2]: 2:2
6837 prim_subreg #(
6838 .DW (1),
6839 .SwAccess(prim_subreg_pkg::SwAccessRW),
6840 .RESVAL (1'h0),
6841 .Mubi (1'b0)
6842 ) u_out_iso_iso_2 (
6843 .clk_i (clk_i),
6844 .rst_ni (rst_ni),
6845
6846 // from register interface
6847 .we (out_iso_we),
6848 .wd (out_iso_iso_2_wd),
6849
6850 // from internal hardware
6851 .de (1'b0),
6852 .d ('0),
6853
6854 // to internal hardware
6855 .qe (),
6856 .q (reg2hw.out_iso[2].q),
6857 .ds (),
6858
6859 // to register interface (read)
6860 .qs (out_iso_iso_2_qs)
6861 );
6862
6863 // F[iso_3]: 3:3
6864 prim_subreg #(
6865 .DW (1),
6866 .SwAccess(prim_subreg_pkg::SwAccessRW),
6867 .RESVAL (1'h0),
6868 .Mubi (1'b0)
6869 ) u_out_iso_iso_3 (
6870 .clk_i (clk_i),
6871 .rst_ni (rst_ni),
6872
6873 // from register interface
6874 .we (out_iso_we),
6875 .wd (out_iso_iso_3_wd),
6876
6877 // from internal hardware
6878 .de (1'b0),
6879 .d ('0),
6880
6881 // to internal hardware
6882 .qe (),
6883 .q (reg2hw.out_iso[3].q),
6884 .ds (),
6885
6886 // to register interface (read)
6887 .qs (out_iso_iso_3_qs)
6888 );
6889
6890 // F[iso_4]: 4:4
6891 prim_subreg #(
6892 .DW (1),
6893 .SwAccess(prim_subreg_pkg::SwAccessRW),
6894 .RESVAL (1'h0),
6895 .Mubi (1'b0)
6896 ) u_out_iso_iso_4 (
6897 .clk_i (clk_i),
6898 .rst_ni (rst_ni),
6899
6900 // from register interface
6901 .we (out_iso_we),
6902 .wd (out_iso_iso_4_wd),
6903
6904 // from internal hardware
6905 .de (1'b0),
6906 .d ('0),
6907
6908 // to internal hardware
6909 .qe (),
6910 .q (reg2hw.out_iso[4].q),
6911 .ds (),
6912
6913 // to register interface (read)
6914 .qs (out_iso_iso_4_qs)
6915 );
6916
6917 // F[iso_5]: 5:5
6918 prim_subreg #(
6919 .DW (1),
6920 .SwAccess(prim_subreg_pkg::SwAccessRW),
6921 .RESVAL (1'h0),
6922 .Mubi (1'b0)
6923 ) u_out_iso_iso_5 (
6924 .clk_i (clk_i),
6925 .rst_ni (rst_ni),
6926
6927 // from register interface
6928 .we (out_iso_we),
6929 .wd (out_iso_iso_5_wd),
6930
6931 // from internal hardware
6932 .de (1'b0),
6933 .d ('0),
6934
6935 // to internal hardware
6936 .qe (),
6937 .q (reg2hw.out_iso[5].q),
6938 .ds (),
6939
6940 // to register interface (read)
6941 .qs (out_iso_iso_5_qs)
6942 );
6943
6944 // F[iso_6]: 6:6
6945 prim_subreg #(
6946 .DW (1),
6947 .SwAccess(prim_subreg_pkg::SwAccessRW),
6948 .RESVAL (1'h0),
6949 .Mubi (1'b0)
6950 ) u_out_iso_iso_6 (
6951 .clk_i (clk_i),
6952 .rst_ni (rst_ni),
6953
6954 // from register interface
6955 .we (out_iso_we),
6956 .wd (out_iso_iso_6_wd),
6957
6958 // from internal hardware
6959 .de (1'b0),
6960 .d ('0),
6961
6962 // to internal hardware
6963 .qe (),
6964 .q (reg2hw.out_iso[6].q),
6965 .ds (),
6966
6967 // to register interface (read)
6968 .qs (out_iso_iso_6_qs)
6969 );
6970
6971 // F[iso_7]: 7:7
6972 prim_subreg #(
6973 .DW (1),
6974 .SwAccess(prim_subreg_pkg::SwAccessRW),
6975 .RESVAL (1'h0),
6976 .Mubi (1'b0)
6977 ) u_out_iso_iso_7 (
6978 .clk_i (clk_i),
6979 .rst_ni (rst_ni),
6980
6981 // from register interface
6982 .we (out_iso_we),
6983 .wd (out_iso_iso_7_wd),
6984
6985 // from internal hardware
6986 .de (1'b0),
6987 .d ('0),
6988
6989 // to internal hardware
6990 .qe (),
6991 .q (reg2hw.out_iso[7].q),
6992 .ds (),
6993
6994 // to register interface (read)
6995 .qs (out_iso_iso_7_qs)
6996 );
6997
6998 // F[iso_8]: 8:8
6999 prim_subreg #(
7000 .DW (1),
7001 .SwAccess(prim_subreg_pkg::SwAccessRW),
7002 .RESVAL (1'h0),
7003 .Mubi (1'b0)
7004 ) u_out_iso_iso_8 (
7005 .clk_i (clk_i),
7006 .rst_ni (rst_ni),
7007
7008 // from register interface
7009 .we (out_iso_we),
7010 .wd (out_iso_iso_8_wd),
7011
7012 // from internal hardware
7013 .de (1'b0),
7014 .d ('0),
7015
7016 // to internal hardware
7017 .qe (),
7018 .q (reg2hw.out_iso[8].q),
7019 .ds (),
7020
7021 // to register interface (read)
7022 .qs (out_iso_iso_8_qs)
7023 );
7024
7025 // F[iso_9]: 9:9
7026 prim_subreg #(
7027 .DW (1),
7028 .SwAccess(prim_subreg_pkg::SwAccessRW),
7029 .RESVAL (1'h0),
7030 .Mubi (1'b0)
7031 ) u_out_iso_iso_9 (
7032 .clk_i (clk_i),
7033 .rst_ni (rst_ni),
7034
7035 // from register interface
7036 .we (out_iso_we),
7037 .wd (out_iso_iso_9_wd),
7038
7039 // from internal hardware
7040 .de (1'b0),
7041 .d ('0),
7042
7043 // to internal hardware
7044 .qe (),
7045 .q (reg2hw.out_iso[9].q),
7046 .ds (),
7047
7048 // to register interface (read)
7049 .qs (out_iso_iso_9_qs)
7050 );
7051
7052 // F[iso_10]: 10:10
7053 prim_subreg #(
7054 .DW (1),
7055 .SwAccess(prim_subreg_pkg::SwAccessRW),
7056 .RESVAL (1'h0),
7057 .Mubi (1'b0)
7058 ) u_out_iso_iso_10 (
7059 .clk_i (clk_i),
7060 .rst_ni (rst_ni),
7061
7062 // from register interface
7063 .we (out_iso_we),
7064 .wd (out_iso_iso_10_wd),
7065
7066 // from internal hardware
7067 .de (1'b0),
7068 .d ('0),
7069
7070 // to internal hardware
7071 .qe (),
7072 .q (reg2hw.out_iso[10].q),
7073 .ds (),
7074
7075 // to register interface (read)
7076 .qs (out_iso_iso_10_qs)
7077 );
7078
7079 // F[iso_11]: 11:11
7080 prim_subreg #(
7081 .DW (1),
7082 .SwAccess(prim_subreg_pkg::SwAccessRW),
7083 .RESVAL (1'h0),
7084 .Mubi (1'b0)
7085 ) u_out_iso_iso_11 (
7086 .clk_i (clk_i),
7087 .rst_ni (rst_ni),
7088
7089 // from register interface
7090 .we (out_iso_we),
7091 .wd (out_iso_iso_11_wd),
7092
7093 // from internal hardware
7094 .de (1'b0),
7095 .d ('0),
7096
7097 // to internal hardware
7098 .qe (),
7099 .q (reg2hw.out_iso[11].q),
7100 .ds (),
7101
7102 // to register interface (read)
7103 .qs (out_iso_iso_11_qs)
7104 );
7105
7106
7107 // Subregister 0 of Multireg in_iso
7108 // R[in_iso]: V(False)
7109 // F[iso_0]: 0:0
7110 prim_subreg #(
7111 .DW (1),
7112 .SwAccess(prim_subreg_pkg::SwAccessRW),
7113 .RESVAL (1'h0),
7114 .Mubi (1'b0)
7115 ) u_in_iso_iso_0 (
7116 .clk_i (clk_i),
7117 .rst_ni (rst_ni),
7118
7119 // from register interface
7120 .we (in_iso_we),
7121 .wd (in_iso_iso_0_wd),
7122
7123 // from internal hardware
7124 .de (1'b0),
7125 .d ('0),
7126
7127 // to internal hardware
7128 .qe (),
7129 .q (reg2hw.in_iso[0].q),
7130 .ds (),
7131
7132 // to register interface (read)
7133 .qs (in_iso_iso_0_qs)
7134 );
7135
7136 // F[iso_1]: 1:1
7137 prim_subreg #(
7138 .DW (1),
7139 .SwAccess(prim_subreg_pkg::SwAccessRW),
7140 .RESVAL (1'h0),
7141 .Mubi (1'b0)
7142 ) u_in_iso_iso_1 (
7143 .clk_i (clk_i),
7144 .rst_ni (rst_ni),
7145
7146 // from register interface
7147 .we (in_iso_we),
7148 .wd (in_iso_iso_1_wd),
7149
7150 // from internal hardware
7151 .de (1'b0),
7152 .d ('0),
7153
7154 // to internal hardware
7155 .qe (),
7156 .q (reg2hw.in_iso[1].q),
7157 .ds (),
7158
7159 // to register interface (read)
7160 .qs (in_iso_iso_1_qs)
7161 );
7162
7163 // F[iso_2]: 2:2
7164 prim_subreg #(
7165 .DW (1),
7166 .SwAccess(prim_subreg_pkg::SwAccessRW),
7167 .RESVAL (1'h0),
7168 .Mubi (1'b0)
7169 ) u_in_iso_iso_2 (
7170 .clk_i (clk_i),
7171 .rst_ni (rst_ni),
7172
7173 // from register interface
7174 .we (in_iso_we),
7175 .wd (in_iso_iso_2_wd),
7176
7177 // from internal hardware
7178 .de (1'b0),
7179 .d ('0),
7180
7181 // to internal hardware
7182 .qe (),
7183 .q (reg2hw.in_iso[2].q),
7184 .ds (),
7185
7186 // to register interface (read)
7187 .qs (in_iso_iso_2_qs)
7188 );
7189
7190 // F[iso_3]: 3:3
7191 prim_subreg #(
7192 .DW (1),
7193 .SwAccess(prim_subreg_pkg::SwAccessRW),
7194 .RESVAL (1'h0),
7195 .Mubi (1'b0)
7196 ) u_in_iso_iso_3 (
7197 .clk_i (clk_i),
7198 .rst_ni (rst_ni),
7199
7200 // from register interface
7201 .we (in_iso_we),
7202 .wd (in_iso_iso_3_wd),
7203
7204 // from internal hardware
7205 .de (1'b0),
7206 .d ('0),
7207
7208 // to internal hardware
7209 .qe (),
7210 .q (reg2hw.in_iso[3].q),
7211 .ds (),
7212
7213 // to register interface (read)
7214 .qs (in_iso_iso_3_qs)
7215 );
7216
7217 // F[iso_4]: 4:4
7218 prim_subreg #(
7219 .DW (1),
7220 .SwAccess(prim_subreg_pkg::SwAccessRW),
7221 .RESVAL (1'h0),
7222 .Mubi (1'b0)
7223 ) u_in_iso_iso_4 (
7224 .clk_i (clk_i),
7225 .rst_ni (rst_ni),
7226
7227 // from register interface
7228 .we (in_iso_we),
7229 .wd (in_iso_iso_4_wd),
7230
7231 // from internal hardware
7232 .de (1'b0),
7233 .d ('0),
7234
7235 // to internal hardware
7236 .qe (),
7237 .q (reg2hw.in_iso[4].q),
7238 .ds (),
7239
7240 // to register interface (read)
7241 .qs (in_iso_iso_4_qs)
7242 );
7243
7244 // F[iso_5]: 5:5
7245 prim_subreg #(
7246 .DW (1),
7247 .SwAccess(prim_subreg_pkg::SwAccessRW),
7248 .RESVAL (1'h0),
7249 .Mubi (1'b0)
7250 ) u_in_iso_iso_5 (
7251 .clk_i (clk_i),
7252 .rst_ni (rst_ni),
7253
7254 // from register interface
7255 .we (in_iso_we),
7256 .wd (in_iso_iso_5_wd),
7257
7258 // from internal hardware
7259 .de (1'b0),
7260 .d ('0),
7261
7262 // to internal hardware
7263 .qe (),
7264 .q (reg2hw.in_iso[5].q),
7265 .ds (),
7266
7267 // to register interface (read)
7268 .qs (in_iso_iso_5_qs)
7269 );
7270
7271 // F[iso_6]: 6:6
7272 prim_subreg #(
7273 .DW (1),
7274 .SwAccess(prim_subreg_pkg::SwAccessRW),
7275 .RESVAL (1'h0),
7276 .Mubi (1'b0)
7277 ) u_in_iso_iso_6 (
7278 .clk_i (clk_i),
7279 .rst_ni (rst_ni),
7280
7281 // from register interface
7282 .we (in_iso_we),
7283 .wd (in_iso_iso_6_wd),
7284
7285 // from internal hardware
7286 .de (1'b0),
7287 .d ('0),
7288
7289 // to internal hardware
7290 .qe (),
7291 .q (reg2hw.in_iso[6].q),
7292 .ds (),
7293
7294 // to register interface (read)
7295 .qs (in_iso_iso_6_qs)
7296 );
7297
7298 // F[iso_7]: 7:7
7299 prim_subreg #(
7300 .DW (1),
7301 .SwAccess(prim_subreg_pkg::SwAccessRW),
7302 .RESVAL (1'h0),
7303 .Mubi (1'b0)
7304 ) u_in_iso_iso_7 (
7305 .clk_i (clk_i),
7306 .rst_ni (rst_ni),
7307
7308 // from register interface
7309 .we (in_iso_we),
7310 .wd (in_iso_iso_7_wd),
7311
7312 // from internal hardware
7313 .de (1'b0),
7314 .d ('0),
7315
7316 // to internal hardware
7317 .qe (),
7318 .q (reg2hw.in_iso[7].q),
7319 .ds (),
7320
7321 // to register interface (read)
7322 .qs (in_iso_iso_7_qs)
7323 );
7324
7325 // F[iso_8]: 8:8
7326 prim_subreg #(
7327 .DW (1),
7328 .SwAccess(prim_subreg_pkg::SwAccessRW),
7329 .RESVAL (1'h0),
7330 .Mubi (1'b0)
7331 ) u_in_iso_iso_8 (
7332 .clk_i (clk_i),
7333 .rst_ni (rst_ni),
7334
7335 // from register interface
7336 .we (in_iso_we),
7337 .wd (in_iso_iso_8_wd),
7338
7339 // from internal hardware
7340 .de (1'b0),
7341 .d ('0),
7342
7343 // to internal hardware
7344 .qe (),
7345 .q (reg2hw.in_iso[8].q),
7346 .ds (),
7347
7348 // to register interface (read)
7349 .qs (in_iso_iso_8_qs)
7350 );
7351
7352 // F[iso_9]: 9:9
7353 prim_subreg #(
7354 .DW (1),
7355 .SwAccess(prim_subreg_pkg::SwAccessRW),
7356 .RESVAL (1'h0),
7357 .Mubi (1'b0)
7358 ) u_in_iso_iso_9 (
7359 .clk_i (clk_i),
7360 .rst_ni (rst_ni),
7361
7362 // from register interface
7363 .we (in_iso_we),
7364 .wd (in_iso_iso_9_wd),
7365
7366 // from internal hardware
7367 .de (1'b0),
7368 .d ('0),
7369
7370 // to internal hardware
7371 .qe (),
7372 .q (reg2hw.in_iso[9].q),
7373 .ds (),
7374
7375 // to register interface (read)
7376 .qs (in_iso_iso_9_qs)
7377 );
7378
7379 // F[iso_10]: 10:10
7380 prim_subreg #(
7381 .DW (1),
7382 .SwAccess(prim_subreg_pkg::SwAccessRW),
7383 .RESVAL (1'h0),
7384 .Mubi (1'b0)
7385 ) u_in_iso_iso_10 (
7386 .clk_i (clk_i),
7387 .rst_ni (rst_ni),
7388
7389 // from register interface
7390 .we (in_iso_we),
7391 .wd (in_iso_iso_10_wd),
7392
7393 // from internal hardware
7394 .de (1'b0),
7395 .d ('0),
7396
7397 // to internal hardware
7398 .qe (),
7399 .q (reg2hw.in_iso[10].q),
7400 .ds (),
7401
7402 // to register interface (read)
7403 .qs (in_iso_iso_10_qs)
7404 );
7405
7406 // F[iso_11]: 11:11
7407 prim_subreg #(
7408 .DW (1),
7409 .SwAccess(prim_subreg_pkg::SwAccessRW),
7410 .RESVAL (1'h0),
7411 .Mubi (1'b0)
7412 ) u_in_iso_iso_11 (
7413 .clk_i (clk_i),
7414 .rst_ni (rst_ni),
7415
7416 // from register interface
7417 .we (in_iso_we),
7418 .wd (in_iso_iso_11_wd),
7419
7420 // from internal hardware
7421 .de (1'b0),
7422 .d ('0),
7423
7424 // to internal hardware
7425 .qe (),
7426 .q (reg2hw.in_iso[11].q),
7427 .ds (),
7428
7429 // to register interface (read)
7430 .qs (in_iso_iso_11_qs)
7431 );
7432
7433
7434 // R[out_data_toggle]: V(True)
7435 logic out_data_toggle_qe;
7436 logic [1:0] out_data_toggle_flds_we;
7437 1/1 assign out_data_toggle_qe = &out_data_toggle_flds_we;
Tests: T29 T30 T32
7438 // F[status]: 11:0
7439 prim_subreg_ext #(
7440 .DW (12)
7441 ) u_out_data_toggle_status (
7442 .re (out_data_toggle_re),
7443 .we (out_data_toggle_we),
7444 .wd (out_data_toggle_status_wd),
7445 .d (hw2reg.out_data_toggle.status.d),
7446 .qre (),
7447 .qe (out_data_toggle_flds_we[0]),
7448 .q (reg2hw.out_data_toggle.status.q),
7449 .ds (),
7450 .qs (out_data_toggle_status_qs)
7451 );
7452 1/1 assign reg2hw.out_data_toggle.status.qe = out_data_toggle_qe;
Tests: T29 T30 T32
7453
7454 // F[mask]: 27:16
7455 prim_subreg_ext #(
7456 .DW (12)
7457 ) u_out_data_toggle_mask (
7458 .re (out_data_toggle_re),
7459 .we (out_data_toggle_we),
7460 .wd (out_data_toggle_mask_wd),
7461 .d (hw2reg.out_data_toggle.mask.d),
7462 .qre (),
7463 .qe (out_data_toggle_flds_we[1]),
7464 .q (reg2hw.out_data_toggle.mask.q),
7465 .ds (),
7466 .qs (out_data_toggle_mask_qs)
7467 );
7468 1/1 assign reg2hw.out_data_toggle.mask.qe = out_data_toggle_qe;
Tests: T29 T30 T32
7469
7470
7471 // R[in_data_toggle]: V(True)
7472 logic in_data_toggle_qe;
7473 logic [1:0] in_data_toggle_flds_we;
7474 1/1 assign in_data_toggle_qe = &in_data_toggle_flds_we;
Tests: T29 T30 T112
7475 // F[status]: 11:0
7476 prim_subreg_ext #(
7477 .DW (12)
7478 ) u_in_data_toggle_status (
7479 .re (in_data_toggle_re),
7480 .we (in_data_toggle_we),
7481 .wd (in_data_toggle_status_wd),
7482 .d (hw2reg.in_data_toggle.status.d),
7483 .qre (),
7484 .qe (in_data_toggle_flds_we[0]),
7485 .q (reg2hw.in_data_toggle.status.q),
7486 .ds (),
7487 .qs (in_data_toggle_status_qs)
7488 );
7489 1/1 assign reg2hw.in_data_toggle.status.qe = in_data_toggle_qe;
Tests: T29 T30 T112
7490
7491 // F[mask]: 27:16
7492 prim_subreg_ext #(
7493 .DW (12)
7494 ) u_in_data_toggle_mask (
7495 .re (in_data_toggle_re),
7496 .we (in_data_toggle_we),
7497 .wd (in_data_toggle_mask_wd),
7498 .d (hw2reg.in_data_toggle.mask.d),
7499 .qre (),
7500 .qe (in_data_toggle_flds_we[1]),
7501 .q (reg2hw.in_data_toggle.mask.q),
7502 .ds (),
7503 .qs (in_data_toggle_mask_qs)
7504 );
7505 1/1 assign reg2hw.in_data_toggle.mask.qe = in_data_toggle_qe;
Tests: T29 T30 T112
7506
7507
7508 // R[phy_pins_sense]: V(True)
7509 // F[rx_dp_i]: 0:0
7510 prim_subreg_ext #(
7511 .DW (1)
7512 ) u_phy_pins_sense_rx_dp_i (
7513 .re (phy_pins_sense_re),
7514 .we (1'b0),
7515 .wd ('0),
7516 .d (hw2reg.phy_pins_sense.rx_dp_i.d),
7517 .qre (),
7518 .qe (),
7519 .q (),
7520 .ds (),
7521 .qs (phy_pins_sense_rx_dp_i_qs)
7522 );
7523
7524 // F[rx_dn_i]: 1:1
7525 prim_subreg_ext #(
7526 .DW (1)
7527 ) u_phy_pins_sense_rx_dn_i (
7528 .re (phy_pins_sense_re),
7529 .we (1'b0),
7530 .wd ('0),
7531 .d (hw2reg.phy_pins_sense.rx_dn_i.d),
7532 .qre (),
7533 .qe (),
7534 .q (),
7535 .ds (),
7536 .qs (phy_pins_sense_rx_dn_i_qs)
7537 );
7538
7539 // F[rx_d_i]: 2:2
7540 prim_subreg_ext #(
7541 .DW (1)
7542 ) u_phy_pins_sense_rx_d_i (
7543 .re (phy_pins_sense_re),
7544 .we (1'b0),
7545 .wd ('0),
7546 .d (hw2reg.phy_pins_sense.rx_d_i.d),
7547 .qre (),
7548 .qe (),
7549 .q (),
7550 .ds (),
7551 .qs (phy_pins_sense_rx_d_i_qs)
7552 );
7553
7554 // F[tx_dp_o]: 8:8
7555 prim_subreg_ext #(
7556 .DW (1)
7557 ) u_phy_pins_sense_tx_dp_o (
7558 .re (phy_pins_sense_re),
7559 .we (1'b0),
7560 .wd ('0),
7561 .d (hw2reg.phy_pins_sense.tx_dp_o.d),
7562 .qre (),
7563 .qe (),
7564 .q (),
7565 .ds (),
7566 .qs (phy_pins_sense_tx_dp_o_qs)
7567 );
7568
7569 // F[tx_dn_o]: 9:9
7570 prim_subreg_ext #(
7571 .DW (1)
7572 ) u_phy_pins_sense_tx_dn_o (
7573 .re (phy_pins_sense_re),
7574 .we (1'b0),
7575 .wd ('0),
7576 .d (hw2reg.phy_pins_sense.tx_dn_o.d),
7577 .qre (),
7578 .qe (),
7579 .q (),
7580 .ds (),
7581 .qs (phy_pins_sense_tx_dn_o_qs)
7582 );
7583
7584 // F[tx_d_o]: 10:10
7585 prim_subreg_ext #(
7586 .DW (1)
7587 ) u_phy_pins_sense_tx_d_o (
7588 .re (phy_pins_sense_re),
7589 .we (1'b0),
7590 .wd ('0),
7591 .d (hw2reg.phy_pins_sense.tx_d_o.d),
7592 .qre (),
7593 .qe (),
7594 .q (),
7595 .ds (),
7596 .qs (phy_pins_sense_tx_d_o_qs)
7597 );
7598
7599 // F[tx_se0_o]: 11:11
7600 prim_subreg_ext #(
7601 .DW (1)
7602 ) u_phy_pins_sense_tx_se0_o (
7603 .re (phy_pins_sense_re),
7604 .we (1'b0),
7605 .wd ('0),
7606 .d (hw2reg.phy_pins_sense.tx_se0_o.d),
7607 .qre (),
7608 .qe (),
7609 .q (),
7610 .ds (),
7611 .qs (phy_pins_sense_tx_se0_o_qs)
7612 );
7613
7614 // F[tx_oe_o]: 12:12
7615 prim_subreg_ext #(
7616 .DW (1)
7617 ) u_phy_pins_sense_tx_oe_o (
7618 .re (phy_pins_sense_re),
7619 .we (1'b0),
7620 .wd ('0),
7621 .d (hw2reg.phy_pins_sense.tx_oe_o.d),
7622 .qre (),
7623 .qe (),
7624 .q (),
7625 .ds (),
7626 .qs (phy_pins_sense_tx_oe_o_qs)
7627 );
7628
7629 // F[pwr_sense]: 16:16
7630 prim_subreg_ext #(
7631 .DW (1)
7632 ) u_phy_pins_sense_pwr_sense (
7633 .re (phy_pins_sense_re),
7634 .we (1'b0),
7635 .wd ('0),
7636 .d (hw2reg.phy_pins_sense.pwr_sense.d),
7637 .qre (),
7638 .qe (),
7639 .q (),
7640 .ds (),
7641 .qs (phy_pins_sense_pwr_sense_qs)
7642 );
7643
7644
7645 // R[phy_pins_drive]: V(False)
7646 // F[dp_o]: 0:0
7647 prim_subreg #(
7648 .DW (1),
7649 .SwAccess(prim_subreg_pkg::SwAccessRW),
7650 .RESVAL (1'h0),
7651 .Mubi (1'b0)
7652 ) u_phy_pins_drive_dp_o (
7653 .clk_i (clk_i),
7654 .rst_ni (rst_ni),
7655
7656 // from register interface
7657 .we (phy_pins_drive_we),
7658 .wd (phy_pins_drive_dp_o_wd),
7659
7660 // from internal hardware
7661 .de (1'b0),
7662 .d ('0),
7663
7664 // to internal hardware
7665 .qe (),
7666 .q (reg2hw.phy_pins_drive.dp_o.q),
7667 .ds (),
7668
7669 // to register interface (read)
7670 .qs (phy_pins_drive_dp_o_qs)
7671 );
7672
7673 // F[dn_o]: 1:1
7674 prim_subreg #(
7675 .DW (1),
7676 .SwAccess(prim_subreg_pkg::SwAccessRW),
7677 .RESVAL (1'h0),
7678 .Mubi (1'b0)
7679 ) u_phy_pins_drive_dn_o (
7680 .clk_i (clk_i),
7681 .rst_ni (rst_ni),
7682
7683 // from register interface
7684 .we (phy_pins_drive_we),
7685 .wd (phy_pins_drive_dn_o_wd),
7686
7687 // from internal hardware
7688 .de (1'b0),
7689 .d ('0),
7690
7691 // to internal hardware
7692 .qe (),
7693 .q (reg2hw.phy_pins_drive.dn_o.q),
7694 .ds (),
7695
7696 // to register interface (read)
7697 .qs (phy_pins_drive_dn_o_qs)
7698 );
7699
7700 // F[d_o]: 2:2
7701 prim_subreg #(
7702 .DW (1),
7703 .SwAccess(prim_subreg_pkg::SwAccessRW),
7704 .RESVAL (1'h0),
7705 .Mubi (1'b0)
7706 ) u_phy_pins_drive_d_o (
7707 .clk_i (clk_i),
7708 .rst_ni (rst_ni),
7709
7710 // from register interface
7711 .we (phy_pins_drive_we),
7712 .wd (phy_pins_drive_d_o_wd),
7713
7714 // from internal hardware
7715 .de (1'b0),
7716 .d ('0),
7717
7718 // to internal hardware
7719 .qe (),
7720 .q (reg2hw.phy_pins_drive.d_o.q),
7721 .ds (),
7722
7723 // to register interface (read)
7724 .qs (phy_pins_drive_d_o_qs)
7725 );
7726
7727 // F[se0_o]: 3:3
7728 prim_subreg #(
7729 .DW (1),
7730 .SwAccess(prim_subreg_pkg::SwAccessRW),
7731 .RESVAL (1'h0),
7732 .Mubi (1'b0)
7733 ) u_phy_pins_drive_se0_o (
7734 .clk_i (clk_i),
7735 .rst_ni (rst_ni),
7736
7737 // from register interface
7738 .we (phy_pins_drive_we),
7739 .wd (phy_pins_drive_se0_o_wd),
7740
7741 // from internal hardware
7742 .de (1'b0),
7743 .d ('0),
7744
7745 // to internal hardware
7746 .qe (),
7747 .q (reg2hw.phy_pins_drive.se0_o.q),
7748 .ds (),
7749
7750 // to register interface (read)
7751 .qs (phy_pins_drive_se0_o_qs)
7752 );
7753
7754 // F[oe_o]: 4:4
7755 prim_subreg #(
7756 .DW (1),
7757 .SwAccess(prim_subreg_pkg::SwAccessRW),
7758 .RESVAL (1'h0),
7759 .Mubi (1'b0)
7760 ) u_phy_pins_drive_oe_o (
7761 .clk_i (clk_i),
7762 .rst_ni (rst_ni),
7763
7764 // from register interface
7765 .we (phy_pins_drive_we),
7766 .wd (phy_pins_drive_oe_o_wd),
7767
7768 // from internal hardware
7769 .de (1'b0),
7770 .d ('0),
7771
7772 // to internal hardware
7773 .qe (),
7774 .q (reg2hw.phy_pins_drive.oe_o.q),
7775 .ds (),
7776
7777 // to register interface (read)
7778 .qs (phy_pins_drive_oe_o_qs)
7779 );
7780
7781 // F[rx_enable_o]: 5:5
7782 prim_subreg #(
7783 .DW (1),
7784 .SwAccess(prim_subreg_pkg::SwAccessRW),
7785 .RESVAL (1'h0),
7786 .Mubi (1'b0)
7787 ) u_phy_pins_drive_rx_enable_o (
7788 .clk_i (clk_i),
7789 .rst_ni (rst_ni),
7790
7791 // from register interface
7792 .we (phy_pins_drive_we),
7793 .wd (phy_pins_drive_rx_enable_o_wd),
7794
7795 // from internal hardware
7796 .de (1'b0),
7797 .d ('0),
7798
7799 // to internal hardware
7800 .qe (),
7801 .q (reg2hw.phy_pins_drive.rx_enable_o.q),
7802 .ds (),
7803
7804 // to register interface (read)
7805 .qs (phy_pins_drive_rx_enable_o_qs)
7806 );
7807
7808 // F[dp_pullup_en_o]: 6:6
7809 prim_subreg #(
7810 .DW (1),
7811 .SwAccess(prim_subreg_pkg::SwAccessRW),
7812 .RESVAL (1'h0),
7813 .Mubi (1'b0)
7814 ) u_phy_pins_drive_dp_pullup_en_o (
7815 .clk_i (clk_i),
7816 .rst_ni (rst_ni),
7817
7818 // from register interface
7819 .we (phy_pins_drive_we),
7820 .wd (phy_pins_drive_dp_pullup_en_o_wd),
7821
7822 // from internal hardware
7823 .de (1'b0),
7824 .d ('0),
7825
7826 // to internal hardware
7827 .qe (),
7828 .q (reg2hw.phy_pins_drive.dp_pullup_en_o.q),
7829 .ds (),
7830
7831 // to register interface (read)
7832 .qs (phy_pins_drive_dp_pullup_en_o_qs)
7833 );
7834
7835 // F[dn_pullup_en_o]: 7:7
7836 prim_subreg #(
7837 .DW (1),
7838 .SwAccess(prim_subreg_pkg::SwAccessRW),
7839 .RESVAL (1'h0),
7840 .Mubi (1'b0)
7841 ) u_phy_pins_drive_dn_pullup_en_o (
7842 .clk_i (clk_i),
7843 .rst_ni (rst_ni),
7844
7845 // from register interface
7846 .we (phy_pins_drive_we),
7847 .wd (phy_pins_drive_dn_pullup_en_o_wd),
7848
7849 // from internal hardware
7850 .de (1'b0),
7851 .d ('0),
7852
7853 // to internal hardware
7854 .qe (),
7855 .q (reg2hw.phy_pins_drive.dn_pullup_en_o.q),
7856 .ds (),
7857
7858 // to register interface (read)
7859 .qs (phy_pins_drive_dn_pullup_en_o_qs)
7860 );
7861
7862 // F[en]: 16:16
7863 prim_subreg #(
7864 .DW (1),
7865 .SwAccess(prim_subreg_pkg::SwAccessRW),
7866 .RESVAL (1'h0),
7867 .Mubi (1'b0)
7868 ) u_phy_pins_drive_en (
7869 .clk_i (clk_i),
7870 .rst_ni (rst_ni),
7871
7872 // from register interface
7873 .we (phy_pins_drive_we),
7874 .wd (phy_pins_drive_en_wd),
7875
7876 // from internal hardware
7877 .de (1'b0),
7878 .d ('0),
7879
7880 // to internal hardware
7881 .qe (),
7882 .q (reg2hw.phy_pins_drive.en.q),
7883 .ds (),
7884
7885 // to register interface (read)
7886 .qs (phy_pins_drive_en_qs)
7887 );
7888
7889
7890 // R[phy_config]: V(False)
7891 // F[use_diff_rcvr]: 0:0
7892 prim_subreg #(
7893 .DW (1),
7894 .SwAccess(prim_subreg_pkg::SwAccessRW),
7895 .RESVAL (1'h0),
7896 .Mubi (1'b0)
7897 ) u_phy_config_use_diff_rcvr (
7898 .clk_i (clk_i),
7899 .rst_ni (rst_ni),
7900
7901 // from register interface
7902 .we (phy_config_we),
7903 .wd (phy_config_use_diff_rcvr_wd),
7904
7905 // from internal hardware
7906 .de (1'b0),
7907 .d ('0),
7908
7909 // to internal hardware
7910 .qe (),
7911 .q (reg2hw.phy_config.use_diff_rcvr.q),
7912 .ds (),
7913
7914 // to register interface (read)
7915 .qs (phy_config_use_diff_rcvr_qs)
7916 );
7917
7918 // F[tx_use_d_se0]: 1:1
7919 prim_subreg #(
7920 .DW (1),
7921 .SwAccess(prim_subreg_pkg::SwAccessRW),
7922 .RESVAL (1'h0),
7923 .Mubi (1'b0)
7924 ) u_phy_config_tx_use_d_se0 (
7925 .clk_i (clk_i),
7926 .rst_ni (rst_ni),
7927
7928 // from register interface
7929 .we (phy_config_we),
7930 .wd (phy_config_tx_use_d_se0_wd),
7931
7932 // from internal hardware
7933 .de (1'b0),
7934 .d ('0),
7935
7936 // to internal hardware
7937 .qe (),
7938 .q (reg2hw.phy_config.tx_use_d_se0.q),
7939 .ds (),
7940
7941 // to register interface (read)
7942 .qs (phy_config_tx_use_d_se0_qs)
7943 );
7944
7945 // F[eop_single_bit]: 2:2
7946 prim_subreg #(
7947 .DW (1),
7948 .SwAccess(prim_subreg_pkg::SwAccessRW),
7949 .RESVAL (1'h1),
7950 .Mubi (1'b0)
7951 ) u_phy_config_eop_single_bit (
7952 .clk_i (clk_i),
7953 .rst_ni (rst_ni),
7954
7955 // from register interface
7956 .we (phy_config_we),
7957 .wd (phy_config_eop_single_bit_wd),
7958
7959 // from internal hardware
7960 .de (1'b0),
7961 .d ('0),
7962
7963 // to internal hardware
7964 .qe (),
7965 .q (reg2hw.phy_config.eop_single_bit.q),
7966 .ds (),
7967
7968 // to register interface (read)
7969 .qs (phy_config_eop_single_bit_qs)
7970 );
7971
7972 // F[pinflip]: 5:5
7973 prim_subreg #(
7974 .DW (1),
7975 .SwAccess(prim_subreg_pkg::SwAccessRW),
7976 .RESVAL (1'h0),
7977 .Mubi (1'b0)
7978 ) u_phy_config_pinflip (
7979 .clk_i (clk_i),
7980 .rst_ni (rst_ni),
7981
7982 // from register interface
7983 .we (phy_config_we),
7984 .wd (phy_config_pinflip_wd),
7985
7986 // from internal hardware
7987 .de (1'b0),
7988 .d ('0),
7989
7990 // to internal hardware
7991 .qe (),
7992 .q (reg2hw.phy_config.pinflip.q),
7993 .ds (),
7994
7995 // to register interface (read)
7996 .qs (phy_config_pinflip_qs)
7997 );
7998
7999 // F[usb_ref_disable]: 6:6
8000 prim_subreg #(
8001 .DW (1),
8002 .SwAccess(prim_subreg_pkg::SwAccessRW),
8003 .RESVAL (1'h0),
8004 .Mubi (1'b0)
8005 ) u_phy_config_usb_ref_disable (
8006 .clk_i (clk_i),
8007 .rst_ni (rst_ni),
8008
8009 // from register interface
8010 .we (phy_config_we),
8011 .wd (phy_config_usb_ref_disable_wd),
8012
8013 // from internal hardware
8014 .de (1'b0),
8015 .d ('0),
8016
8017 // to internal hardware
8018 .qe (),
8019 .q (reg2hw.phy_config.usb_ref_disable.q),
8020 .ds (),
8021
8022 // to register interface (read)
8023 .qs (phy_config_usb_ref_disable_qs)
8024 );
8025
8026 // F[tx_osc_test_mode]: 7:7
8027 prim_subreg #(
8028 .DW (1),
8029 .SwAccess(prim_subreg_pkg::SwAccessRW),
8030 .RESVAL (1'h0),
8031 .Mubi (1'b0)
8032 ) u_phy_config_tx_osc_test_mode (
8033 .clk_i (clk_i),
8034 .rst_ni (rst_ni),
8035
8036 // from register interface
8037 .we (phy_config_we),
8038 .wd (phy_config_tx_osc_test_mode_wd),
8039
8040 // from internal hardware
8041 .de (1'b0),
8042 .d ('0),
8043
8044 // to internal hardware
8045 .qe (),
8046 .q (reg2hw.phy_config.tx_osc_test_mode.q),
8047 .ds (),
8048
8049 // to register interface (read)
8050 .qs (phy_config_tx_osc_test_mode_qs)
8051 );
8052
8053
8054 // R[wake_control]: V(True)
8055 logic wake_control_qe;
8056 logic [1:0] wake_control_flds_we;
8057 1/1 assign wake_control_qe = &wake_control_flds_we;
Tests: T7 T8 T9
8058 // F[suspend_req]: 0:0
8059 prim_subreg_ext #(
8060 .DW (1)
8061 ) u_wake_control_suspend_req (
8062 .re (1'b0),
8063 .we (aon_wake_control_we),
8064 .wd (aon_wake_control_wdata[0]),
8065 .d ('0),
8066 .qre (),
8067 .qe (wake_control_flds_we[0]),
8068 .q (reg2hw.wake_control.suspend_req.q),
8069 .ds (),
8070 .qs ()
8071 );
8072 1/1 assign reg2hw.wake_control.suspend_req.qe = wake_control_qe;
Tests: T7 T8 T9
8073
8074 // F[wake_ack]: 1:1
8075 prim_subreg_ext #(
8076 .DW (1)
8077 ) u_wake_control_wake_ack (
8078 .re (1'b0),
8079 .we (aon_wake_control_we),
8080 .wd (aon_wake_control_wdata[1]),
8081 .d ('0),
8082 .qre (),
8083 .qe (wake_control_flds_we[1]),
8084 .q (reg2hw.wake_control.wake_ack.q),
8085 .ds (),
8086 .qs ()
8087 );
8088 1/1 assign reg2hw.wake_control.wake_ack.qe = wake_control_qe;
Tests: T7 T8 T9
8089
8090
8091 // R[wake_events]: V(False)
8092 logic [3:0] wake_events_flds_we;
8093 0/1 ==> assign aon_wake_events_qe = |wake_events_flds_we;
8094 // F[module_active]: 0:0
8095 prim_subreg #(
8096 .DW (1),
8097 .SwAccess(prim_subreg_pkg::SwAccessRO),
8098 .RESVAL (1'h0),
8099 .Mubi (1'b0)
8100 ) u_wake_events_module_active (
8101 .clk_i (clk_aon_i),
8102 .rst_ni (rst_aon_ni),
8103
8104 // from register interface
8105 .we (1'b0),
8106 .wd ('0),
8107
8108 // from internal hardware
8109 .de (hw2reg.wake_events.module_active.de),
8110 .d (hw2reg.wake_events.module_active.d),
8111
8112 // to internal hardware
8113 .qe (wake_events_flds_we[0]),
8114 .q (),
8115 .ds (aon_wake_events_module_active_ds_int),
8116
8117 // to register interface (read)
8118 .qs (aon_wake_events_module_active_qs_int)
8119 );
8120
8121 // F[disconnected]: 8:8
8122 prim_subreg #(
8123 .DW (1),
8124 .SwAccess(prim_subreg_pkg::SwAccessRO),
8125 .RESVAL (1'h0),
8126 .Mubi (1'b0)
8127 ) u_wake_events_disconnected (
8128 .clk_i (clk_aon_i),
8129 .rst_ni (rst_aon_ni),
8130
8131 // from register interface
8132 .we (1'b0),
8133 .wd ('0),
8134
8135 // from internal hardware
8136 .de (hw2reg.wake_events.disconnected.de),
8137 .d (hw2reg.wake_events.disconnected.d),
8138
8139 // to internal hardware
8140 .qe (wake_events_flds_we[1]),
8141 .q (),
8142 .ds (aon_wake_events_disconnected_ds_int),
8143
8144 // to register interface (read)
8145 .qs (aon_wake_events_disconnected_qs_int)
8146 );
8147
8148 // F[bus_reset]: 9:9
8149 prim_subreg #(
8150 .DW (1),
8151 .SwAccess(prim_subreg_pkg::SwAccessRO),
8152 .RESVAL (1'h0),
8153 .Mubi (1'b0)
8154 ) u_wake_events_bus_reset (
8155 .clk_i (clk_aon_i),
8156 .rst_ni (rst_aon_ni),
8157
8158 // from register interface
8159 .we (1'b0),
8160 .wd ('0),
8161
8162 // from internal hardware
8163 .de (hw2reg.wake_events.bus_reset.de),
8164 .d (hw2reg.wake_events.bus_reset.d),
8165
8166 // to internal hardware
8167 .qe (wake_events_flds_we[2]),
8168 .q (),
8169 .ds (aon_wake_events_bus_reset_ds_int),
8170
8171 // to register interface (read)
8172 .qs (aon_wake_events_bus_reset_qs_int)
8173 );
8174
8175 // F[bus_not_idle]: 10:10
8176 prim_subreg #(
8177 .DW (1),
8178 .SwAccess(prim_subreg_pkg::SwAccessRO),
8179 .RESVAL (1'h0),
8180 .Mubi (1'b0)
8181 ) u_wake_events_bus_not_idle (
8182 .clk_i (clk_aon_i),
8183 .rst_ni (rst_aon_ni),
8184
8185 // from register interface
8186 .we (1'b0),
8187 .wd ('0),
8188
8189 // from internal hardware
8190 .de (hw2reg.wake_events.bus_not_idle.de),
8191 .d (hw2reg.wake_events.bus_not_idle.d),
8192
8193 // to internal hardware
8194 .qe (wake_events_flds_we[3]),
8195 .q (),
8196 .ds (aon_wake_events_bus_not_idle_ds_int),
8197
8198 // to register interface (read)
8199 .qs (aon_wake_events_bus_not_idle_qs_int)
8200 );
8201
8202
8203 // R[fifo_ctrl]: V(False)
8204 logic fifo_ctrl_qe;
8205 logic [2:0] fifo_ctrl_flds_we;
8206 prim_flop #(
8207 .Width(1),
8208 .ResetValue(0)
8209 ) u_fifo_ctrl0_qe (
8210 .clk_i(clk_i),
8211 .rst_ni(rst_ni),
8212 .d_i(&fifo_ctrl_flds_we),
8213 .q_o(fifo_ctrl_qe)
8214 );
8215 // F[avout_rst]: 0:0
8216 prim_subreg #(
8217 .DW (1),
8218 .SwAccess(prim_subreg_pkg::SwAccessWO),
8219 .RESVAL (1'h0),
8220 .Mubi (1'b0)
8221 ) u_fifo_ctrl_avout_rst (
8222 .clk_i (clk_i),
8223 .rst_ni (rst_ni),
8224
8225 // from register interface
8226 .we (fifo_ctrl_we),
8227 .wd (fifo_ctrl_avout_rst_wd),
8228
8229 // from internal hardware
8230 .de (1'b0),
8231 .d ('0),
8232
8233 // to internal hardware
8234 .qe (fifo_ctrl_flds_we[0]),
8235 .q (reg2hw.fifo_ctrl.avout_rst.q),
8236 .ds (),
8237
8238 // to register interface (read)
8239 .qs ()
8240 );
8241 1/1 assign reg2hw.fifo_ctrl.avout_rst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
8242
8243 // F[avsetup_rst]: 1:1
8244 prim_subreg #(
8245 .DW (1),
8246 .SwAccess(prim_subreg_pkg::SwAccessWO),
8247 .RESVAL (1'h0),
8248 .Mubi (1'b0)
8249 ) u_fifo_ctrl_avsetup_rst (
8250 .clk_i (clk_i),
8251 .rst_ni (rst_ni),
8252
8253 // from register interface
8254 .we (fifo_ctrl_we),
8255 .wd (fifo_ctrl_avsetup_rst_wd),
8256
8257 // from internal hardware
8258 .de (1'b0),
8259 .d ('0),
8260
8261 // to internal hardware
8262 .qe (fifo_ctrl_flds_we[1]),
8263 .q (reg2hw.fifo_ctrl.avsetup_rst.q),
8264 .ds (),
8265
8266 // to register interface (read)
8267 .qs ()
8268 );
8269 1/1 assign reg2hw.fifo_ctrl.avsetup_rst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
8270
8271 // F[rx_rst]: 2:2
8272 prim_subreg #(
8273 .DW (1),
8274 .SwAccess(prim_subreg_pkg::SwAccessWO),
8275 .RESVAL (1'h0),
8276 .Mubi (1'b0)
8277 ) u_fifo_ctrl_rx_rst (
8278 .clk_i (clk_i),
8279 .rst_ni (rst_ni),
8280
8281 // from register interface
8282 .we (fifo_ctrl_we),
8283 .wd (fifo_ctrl_rx_rst_wd),
8284
8285 // from internal hardware
8286 .de (1'b0),
8287 .d ('0),
8288
8289 // to internal hardware
8290 .qe (fifo_ctrl_flds_we[2]),
8291 .q (reg2hw.fifo_ctrl.rx_rst.q),
8292 .ds (),
8293
8294 // to register interface (read)
8295 .qs ()
8296 );
8297 1/1 assign reg2hw.fifo_ctrl.rx_rst.qe = fifo_ctrl_qe;
Tests: T1 T2 T3
8298
8299
8300 // R[count_out]: V(True)
8301 logic count_out_qe;
8302 logic [6:0] count_out_flds_we;
8303 // This ignores QEs that are set to constant 0 due to read-only fields.
8304 logic unused_count_out_flds_we;
8305 unreachable assign unused_count_out_flds_we = ^(count_out_flds_we & 7'h1);
8306 1/1 assign count_out_qe = &(count_out_flds_we | 7'h1);
Tests: T261 T270 T271
8307 // F[count]: 7:0
8308 prim_subreg_ext #(
8309 .DW (8)
8310 ) u_count_out_count (
8311 .re (count_out_re),
8312 .we (1'b0),
8313 .wd ('0),
8314 .d (hw2reg.count_out.count.d),
8315 .qre (),
8316 .qe (count_out_flds_we[0]),
8317 .q (),
8318 .ds (),
8319 .qs (count_out_count_qs)
8320 );
8321
8322 // F[datatog_out]: 12:12
8323 prim_subreg_ext #(
8324 .DW (1)
8325 ) u_count_out_datatog_out (
8326 .re (count_out_re),
8327 .we (count_out_we),
8328 .wd (count_out_datatog_out_wd),
8329 .d (hw2reg.count_out.datatog_out.d),
8330 .qre (),
8331 .qe (count_out_flds_we[1]),
8332 .q (reg2hw.count_out.datatog_out.q),
8333 .ds (),
8334 .qs (count_out_datatog_out_qs)
8335 );
8336 1/1 assign reg2hw.count_out.datatog_out.qe = count_out_qe;
Tests: T261 T270 T271
8337
8338 // F[drop_rx]: 13:13
8339 prim_subreg_ext #(
8340 .DW (1)
8341 ) u_count_out_drop_rx (
8342 .re (count_out_re),
8343 .we (count_out_we),
8344 .wd (count_out_drop_rx_wd),
8345 .d (hw2reg.count_out.drop_rx.d),
8346 .qre (),
8347 .qe (count_out_flds_we[2]),
8348 .q (reg2hw.count_out.drop_rx.q),
8349 .ds (),
8350 .qs (count_out_drop_rx_qs)
8351 );
8352 1/1 assign reg2hw.count_out.drop_rx.qe = count_out_qe;
Tests: T261 T270 T271
8353
8354 // F[drop_avout]: 14:14
8355 prim_subreg_ext #(
8356 .DW (1)
8357 ) u_count_out_drop_avout (
8358 .re (count_out_re),
8359 .we (count_out_we),
8360 .wd (count_out_drop_avout_wd),
8361 .d (hw2reg.count_out.drop_avout.d),
8362 .qre (),
8363 .qe (count_out_flds_we[3]),
8364 .q (reg2hw.count_out.drop_avout.q),
8365 .ds (),
8366 .qs (count_out_drop_avout_qs)
8367 );
8368 1/1 assign reg2hw.count_out.drop_avout.qe = count_out_qe;
Tests: T261 T270 T271
8369
8370 // F[ign_avsetup]: 15:15
8371 prim_subreg_ext #(
8372 .DW (1)
8373 ) u_count_out_ign_avsetup (
8374 .re (count_out_re),
8375 .we (count_out_we),
8376 .wd (count_out_ign_avsetup_wd),
8377 .d (hw2reg.count_out.ign_avsetup.d),
8378 .qre (),
8379 .qe (count_out_flds_we[4]),
8380 .q (reg2hw.count_out.ign_avsetup.q),
8381 .ds (),
8382 .qs (count_out_ign_avsetup_qs)
8383 );
8384 1/1 assign reg2hw.count_out.ign_avsetup.qe = count_out_qe;
Tests: T261 T270 T271
8385
8386 // F[endpoints]: 27:16
8387 prim_subreg_ext #(
8388 .DW (12)
8389 ) u_count_out_endpoints (
8390 .re (count_out_re),
8391 .we (count_out_we),
8392 .wd (count_out_endpoints_wd),
8393 .d (hw2reg.count_out.endpoints.d),
8394 .qre (),
8395 .qe (count_out_flds_we[5]),
8396 .q (reg2hw.count_out.endpoints.q),
8397 .ds (),
8398 .qs (count_out_endpoints_qs)
8399 );
8400 1/1 assign reg2hw.count_out.endpoints.qe = count_out_qe;
Tests: T261 T270 T271
8401
8402 // F[rst]: 31:31
8403 prim_subreg_ext #(
8404 .DW (1)
8405 ) u_count_out_rst (
8406 .re (1'b0),
8407 .we (count_out_we),
8408 .wd (count_out_rst_wd),
8409 .d ('0),
8410 .qre (),
8411 .qe (count_out_flds_we[6]),
8412 .q (reg2hw.count_out.rst.q),
8413 .ds (),
8414 .qs ()
8415 );
8416 1/1 assign reg2hw.count_out.rst.qe = count_out_qe;
Tests: T261 T270 T271
8417
8418
8419 // R[count_in]: V(True)
8420 logic count_in_qe;
8421 logic [5:0] count_in_flds_we;
8422 // This ignores QEs that are set to constant 0 due to read-only fields.
8423 logic unused_count_in_flds_we;
8424 unreachable assign unused_count_in_flds_we = ^(count_in_flds_we & 6'h1);
8425 1/1 assign count_in_qe = &(count_in_flds_we | 6'h1);
Tests: T261 T270 T271
8426 // F[count]: 7:0
8427 prim_subreg_ext #(
8428 .DW (8)
8429 ) u_count_in_count (
8430 .re (count_in_re),
8431 .we (1'b0),
8432 .wd ('0),
8433 .d (hw2reg.count_in.count.d),
8434 .qre (),
8435 .qe (count_in_flds_we[0]),
8436 .q (),
8437 .ds (),
8438 .qs (count_in_count_qs)
8439 );
8440
8441 // F[nodata]: 13:13
8442 prim_subreg_ext #(
8443 .DW (1)
8444 ) u_count_in_nodata (
8445 .re (count_in_re),
8446 .we (count_in_we),
8447 .wd (count_in_nodata_wd),
8448 .d (hw2reg.count_in.nodata.d),
8449 .qre (),
8450 .qe (count_in_flds_we[1]),
8451 .q (reg2hw.count_in.nodata.q),
8452 .ds (),
8453 .qs (count_in_nodata_qs)
8454 );
8455 1/1 assign reg2hw.count_in.nodata.qe = count_in_qe;
Tests: T261 T270 T271
8456
8457 // F[nak]: 14:14
8458 prim_subreg_ext #(
8459 .DW (1)
8460 ) u_count_in_nak (
8461 .re (count_in_re),
8462 .we (count_in_we),
8463 .wd (count_in_nak_wd),
8464 .d (hw2reg.count_in.nak.d),
8465 .qre (),
8466 .qe (count_in_flds_we[2]),
8467 .q (reg2hw.count_in.nak.q),
8468 .ds (),
8469 .qs (count_in_nak_qs)
8470 );
8471 1/1 assign reg2hw.count_in.nak.qe = count_in_qe;
Tests: T261 T270 T271
8472
8473 // F[timeout]: 15:15
8474 prim_subreg_ext #(
8475 .DW (1)
8476 ) u_count_in_timeout (
8477 .re (count_in_re),
8478 .we (count_in_we),
8479 .wd (count_in_timeout_wd),
8480 .d (hw2reg.count_in.timeout.d),
8481 .qre (),
8482 .qe (count_in_flds_we[3]),
8483 .q (reg2hw.count_in.timeout.q),
8484 .ds (),
8485 .qs (count_in_timeout_qs)
8486 );
8487 1/1 assign reg2hw.count_in.timeout.qe = count_in_qe;
Tests: T261 T270 T271
8488
8489 // F[endpoints]: 27:16
8490 prim_subreg_ext #(
8491 .DW (12)
8492 ) u_count_in_endpoints (
8493 .re (count_in_re),
8494 .we (count_in_we),
8495 .wd (count_in_endpoints_wd),
8496 .d (hw2reg.count_in.endpoints.d),
8497 .qre (),
8498 .qe (count_in_flds_we[4]),
8499 .q (reg2hw.count_in.endpoints.q),
8500 .ds (),
8501 .qs (count_in_endpoints_qs)
8502 );
8503 1/1 assign reg2hw.count_in.endpoints.qe = count_in_qe;
Tests: T261 T270 T271
8504
8505 // F[rst]: 31:31
8506 prim_subreg_ext #(
8507 .DW (1)
8508 ) u_count_in_rst (
8509 .re (1'b0),
8510 .we (count_in_we),
8511 .wd (count_in_rst_wd),
8512 .d ('0),
8513 .qre (),
8514 .qe (count_in_flds_we[5]),
8515 .q (reg2hw.count_in.rst.q),
8516 .ds (),
8517 .qs ()
8518 );
8519 1/1 assign reg2hw.count_in.rst.qe = count_in_qe;
Tests: T261 T270 T271
8520
8521
8522 // R[count_nodata_in]: V(True)
8523 logic count_nodata_in_qe;
8524 logic [2:0] count_nodata_in_flds_we;
8525 // This ignores QEs that are set to constant 0 due to read-only fields.
8526 logic unused_count_nodata_in_flds_we;
8527 unreachable assign unused_count_nodata_in_flds_we = ^(count_nodata_in_flds_we & 3'h1);
8528 1/1 assign count_nodata_in_qe = &(count_nodata_in_flds_we | 3'h1);
Tests: T261 T270 T271
8529 // F[count]: 7:0
8530 prim_subreg_ext #(
8531 .DW (8)
8532 ) u_count_nodata_in_count (
8533 .re (count_nodata_in_re),
8534 .we (1'b0),
8535 .wd ('0),
8536 .d (hw2reg.count_nodata_in.count.d),
8537 .qre (),
8538 .qe (count_nodata_in_flds_we[0]),
8539 .q (),
8540 .ds (),
8541 .qs (count_nodata_in_count_qs)
8542 );
8543
8544 // F[endpoints]: 27:16
8545 prim_subreg_ext #(
8546 .DW (12)
8547 ) u_count_nodata_in_endpoints (
8548 .re (count_nodata_in_re),
8549 .we (count_nodata_in_we),
8550 .wd (count_nodata_in_endpoints_wd),
8551 .d (hw2reg.count_nodata_in.endpoints.d),
8552 .qre (),
8553 .qe (count_nodata_in_flds_we[1]),
8554 .q (reg2hw.count_nodata_in.endpoints.q),
8555 .ds (),
8556 .qs (count_nodata_in_endpoints_qs)
8557 );
8558 1/1 assign reg2hw.count_nodata_in.endpoints.qe = count_nodata_in_qe;
Tests: T261 T270 T271
8559
8560 // F[rst]: 31:31
8561 prim_subreg_ext #(
8562 .DW (1)
8563 ) u_count_nodata_in_rst (
8564 .re (1'b0),
8565 .we (count_nodata_in_we),
8566 .wd (count_nodata_in_rst_wd),
8567 .d ('0),
8568 .qre (),
8569 .qe (count_nodata_in_flds_we[2]),
8570 .q (reg2hw.count_nodata_in.rst.q),
8571 .ds (),
8572 .qs ()
8573 );
8574 1/1 assign reg2hw.count_nodata_in.rst.qe = count_nodata_in_qe;
Tests: T261 T270 T271
8575
8576
8577 // R[count_errors]: V(True)
8578 logic count_errors_qe;
8579 logic [5:0] count_errors_flds_we;
8580 // This ignores QEs that are set to constant 0 due to read-only fields.
8581 logic unused_count_errors_flds_we;
8582 unreachable assign unused_count_errors_flds_we = ^(count_errors_flds_we & 6'h1);
8583 1/1 assign count_errors_qe = &(count_errors_flds_we | 6'h1);
Tests: T261 T270 T271
8584 // F[count]: 7:0
8585 prim_subreg_ext #(
8586 .DW (8)
8587 ) u_count_errors_count (
8588 .re (count_errors_re),
8589 .we (1'b0),
8590 .wd ('0),
8591 .d (hw2reg.count_errors.count.d),
8592 .qre (),
8593 .qe (count_errors_flds_we[0]),
8594 .q (),
8595 .ds (),
8596 .qs (count_errors_count_qs)
8597 );
8598
8599 // F[pid_invalid]: 27:27
8600 prim_subreg_ext #(
8601 .DW (1)
8602 ) u_count_errors_pid_invalid (
8603 .re (count_errors_re),
8604 .we (count_errors_we),
8605 .wd (count_errors_pid_invalid_wd),
8606 .d (hw2reg.count_errors.pid_invalid.d),
8607 .qre (),
8608 .qe (count_errors_flds_we[1]),
8609 .q (reg2hw.count_errors.pid_invalid.q),
8610 .ds (),
8611 .qs (count_errors_pid_invalid_qs)
8612 );
8613 1/1 assign reg2hw.count_errors.pid_invalid.qe = count_errors_qe;
Tests: T261 T270 T271
8614
8615 // F[bitstuff]: 28:28
8616 prim_subreg_ext #(
8617 .DW (1)
8618 ) u_count_errors_bitstuff (
8619 .re (count_errors_re),
8620 .we (count_errors_we),
8621 .wd (count_errors_bitstuff_wd),
8622 .d (hw2reg.count_errors.bitstuff.d),
8623 .qre (),
8624 .qe (count_errors_flds_we[2]),
8625 .q (reg2hw.count_errors.bitstuff.q),
8626 .ds (),
8627 .qs (count_errors_bitstuff_qs)
8628 );
8629 1/1 assign reg2hw.count_errors.bitstuff.qe = count_errors_qe;
Tests: T261 T270 T271
8630
8631 // F[crc16]: 29:29
8632 prim_subreg_ext #(
8633 .DW (1)
8634 ) u_count_errors_crc16 (
8635 .re (count_errors_re),
8636 .we (count_errors_we),
8637 .wd (count_errors_crc16_wd),
8638 .d (hw2reg.count_errors.crc16.d),
8639 .qre (),
8640 .qe (count_errors_flds_we[3]),
8641 .q (reg2hw.count_errors.crc16.q),
8642 .ds (),
8643 .qs (count_errors_crc16_qs)
8644 );
8645 1/1 assign reg2hw.count_errors.crc16.qe = count_errors_qe;
Tests: T261 T270 T271
8646
8647 // F[crc5]: 30:30
8648 prim_subreg_ext #(
8649 .DW (1)
8650 ) u_count_errors_crc5 (
8651 .re (count_errors_re),
8652 .we (count_errors_we),
8653 .wd (count_errors_crc5_wd),
8654 .d (hw2reg.count_errors.crc5.d),
8655 .qre (),
8656 .qe (count_errors_flds_we[4]),
8657 .q (reg2hw.count_errors.crc5.q),
8658 .ds (),
8659 .qs (count_errors_crc5_qs)
8660 );
8661 1/1 assign reg2hw.count_errors.crc5.qe = count_errors_qe;
Tests: T261 T270 T271
8662
8663 // F[rst]: 31:31
8664 prim_subreg_ext #(
8665 .DW (1)
8666 ) u_count_errors_rst (
8667 .re (1'b0),
8668 .we (count_errors_we),
8669 .wd (count_errors_rst_wd),
8670 .d ('0),
8671 .qre (),
8672 .qe (count_errors_flds_we[5]),
8673 .q (reg2hw.count_errors.rst.q),
8674 .ds (),
8675 .qs ()
8676 );
8677 1/1 assign reg2hw.count_errors.rst.qe = count_errors_qe;
Tests: T261 T270 T271
8678
8679
8680
8681 logic [42:0] addr_hit;
8682 always_comb begin
8683 1/1 addr_hit = '0;
Tests: T1 T2 T3
8684 1/1 addr_hit[ 0] = (reg_addr == USBDEV_INTR_STATE_OFFSET);
Tests: T1 T2 T3
8685 1/1 addr_hit[ 1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET);
Tests: T1 T2 T3
8686 1/1 addr_hit[ 2] = (reg_addr == USBDEV_INTR_TEST_OFFSET);
Tests: T1 T2 T3
8687 1/1 addr_hit[ 3] = (reg_addr == USBDEV_ALERT_TEST_OFFSET);
Tests: T1 T2 T3
8688 1/1 addr_hit[ 4] = (reg_addr == USBDEV_USBCTRL_OFFSET);
Tests: T1 T2 T3
8689 1/1 addr_hit[ 5] = (reg_addr == USBDEV_EP_OUT_ENABLE_OFFSET);
Tests: T1 T2 T3
8690 1/1 addr_hit[ 6] = (reg_addr == USBDEV_EP_IN_ENABLE_OFFSET);
Tests: T1 T2 T3
8691 1/1 addr_hit[ 7] = (reg_addr == USBDEV_USBSTAT_OFFSET);
Tests: T1 T2 T3
8692 1/1 addr_hit[ 8] = (reg_addr == USBDEV_AVOUTBUFFER_OFFSET);
Tests: T1 T2 T3
8693 1/1 addr_hit[ 9] = (reg_addr == USBDEV_AVSETUPBUFFER_OFFSET);
Tests: T1 T2 T3
8694 1/1 addr_hit[10] = (reg_addr == USBDEV_RXFIFO_OFFSET);
Tests: T1 T2 T3
8695 1/1 addr_hit[11] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET);
Tests: T1 T2 T3
8696 1/1 addr_hit[12] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET);
Tests: T1 T2 T3
8697 1/1 addr_hit[13] = (reg_addr == USBDEV_SET_NAK_OUT_OFFSET);
Tests: T1 T2 T3
8698 1/1 addr_hit[14] = (reg_addr == USBDEV_IN_SENT_OFFSET);
Tests: T1 T2 T3
8699 1/1 addr_hit[15] = (reg_addr == USBDEV_OUT_STALL_OFFSET);
Tests: T1 T2 T3
8700 1/1 addr_hit[16] = (reg_addr == USBDEV_IN_STALL_OFFSET);
Tests: T1 T2 T3
8701 1/1 addr_hit[17] = (reg_addr == USBDEV_CONFIGIN_0_OFFSET);
Tests: T1 T2 T3
8702 1/1 addr_hit[18] = (reg_addr == USBDEV_CONFIGIN_1_OFFSET);
Tests: T1 T2 T3
8703 1/1 addr_hit[19] = (reg_addr == USBDEV_CONFIGIN_2_OFFSET);
Tests: T1 T2 T3
8704 1/1 addr_hit[20] = (reg_addr == USBDEV_CONFIGIN_3_OFFSET);
Tests: T1 T2 T3
8705 1/1 addr_hit[21] = (reg_addr == USBDEV_CONFIGIN_4_OFFSET);
Tests: T1 T2 T3
8706 1/1 addr_hit[22] = (reg_addr == USBDEV_CONFIGIN_5_OFFSET);
Tests: T1 T2 T3
8707 1/1 addr_hit[23] = (reg_addr == USBDEV_CONFIGIN_6_OFFSET);
Tests: T1 T2 T3
8708 1/1 addr_hit[24] = (reg_addr == USBDEV_CONFIGIN_7_OFFSET);
Tests: T1 T2 T3
8709 1/1 addr_hit[25] = (reg_addr == USBDEV_CONFIGIN_8_OFFSET);
Tests: T1 T2 T3
8710 1/1 addr_hit[26] = (reg_addr == USBDEV_CONFIGIN_9_OFFSET);
Tests: T1 T2 T3
8711 1/1 addr_hit[27] = (reg_addr == USBDEV_CONFIGIN_10_OFFSET);
Tests: T1 T2 T3
8712 1/1 addr_hit[28] = (reg_addr == USBDEV_CONFIGIN_11_OFFSET);
Tests: T1 T2 T3
8713 1/1 addr_hit[29] = (reg_addr == USBDEV_OUT_ISO_OFFSET);
Tests: T1 T2 T3
8714 1/1 addr_hit[30] = (reg_addr == USBDEV_IN_ISO_OFFSET);
Tests: T1 T2 T3
8715 1/1 addr_hit[31] = (reg_addr == USBDEV_OUT_DATA_TOGGLE_OFFSET);
Tests: T1 T2 T3
8716 1/1 addr_hit[32] = (reg_addr == USBDEV_IN_DATA_TOGGLE_OFFSET);
Tests: T1 T2 T3
8717 1/1 addr_hit[33] = (reg_addr == USBDEV_PHY_PINS_SENSE_OFFSET);
Tests: T1 T2 T3
8718 1/1 addr_hit[34] = (reg_addr == USBDEV_PHY_PINS_DRIVE_OFFSET);
Tests: T1 T2 T3
8719 1/1 addr_hit[35] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET);
Tests: T1 T2 T3
8720 1/1 addr_hit[36] = (reg_addr == USBDEV_WAKE_CONTROL_OFFSET);
Tests: T1 T2 T3
8721 1/1 addr_hit[37] = (reg_addr == USBDEV_WAKE_EVENTS_OFFSET);
Tests: T1 T2 T3
8722 1/1 addr_hit[38] = (reg_addr == USBDEV_FIFO_CTRL_OFFSET);
Tests: T1 T2 T3
8723 1/1 addr_hit[39] = (reg_addr == USBDEV_COUNT_OUT_OFFSET);
Tests: T1 T2 T3
8724 1/1 addr_hit[40] = (reg_addr == USBDEV_COUNT_IN_OFFSET);
Tests: T1 T2 T3
8725 1/1 addr_hit[41] = (reg_addr == USBDEV_COUNT_NODATA_IN_OFFSET);
Tests: T1 T2 T3
8726 1/1 addr_hit[42] = (reg_addr == USBDEV_COUNT_ERRORS_OFFSET);
Tests: T1 T2 T3
8727 end
8728
8729 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T1 T2 T3
8730
8731 // Check sub-word write is permitted
8732 always_comb begin
8733 1/1 wr_err = (reg_we &
Tests: T1 T2 T3
8734 ((addr_hit[ 0] & (|(USBDEV_PERMIT[ 0] & ~reg_be))) |
8735 (addr_hit[ 1] & (|(USBDEV_PERMIT[ 1] & ~reg_be))) |
8736 (addr_hit[ 2] & (|(USBDEV_PERMIT[ 2] & ~reg_be))) |
8737 (addr_hit[ 3] & (|(USBDEV_PERMIT[ 3] & ~reg_be))) |
8738 (addr_hit[ 4] & (|(USBDEV_PERMIT[ 4] & ~reg_be))) |
8739 (addr_hit[ 5] & (|(USBDEV_PERMIT[ 5] & ~reg_be))) |
8740 (addr_hit[ 6] & (|(USBDEV_PERMIT[ 6] & ~reg_be))) |
8741 (addr_hit[ 7] & (|(USBDEV_PERMIT[ 7] & ~reg_be))) |
8742 (addr_hit[ 8] & (|(USBDEV_PERMIT[ 8] & ~reg_be))) |
8743 (addr_hit[ 9] & (|(USBDEV_PERMIT[ 9] & ~reg_be))) |
8744 (addr_hit[10] & (|(USBDEV_PERMIT[10] & ~reg_be))) |
8745 (addr_hit[11] & (|(USBDEV_PERMIT[11] & ~reg_be))) |
8746 (addr_hit[12] & (|(USBDEV_PERMIT[12] & ~reg_be))) |
8747 (addr_hit[13] & (|(USBDEV_PERMIT[13] & ~reg_be))) |
8748 (addr_hit[14] & (|(USBDEV_PERMIT[14] & ~reg_be))) |
8749 (addr_hit[15] & (|(USBDEV_PERMIT[15] & ~reg_be))) |
8750 (addr_hit[16] & (|(USBDEV_PERMIT[16] & ~reg_be))) |
8751 (addr_hit[17] & (|(USBDEV_PERMIT[17] & ~reg_be))) |
8752 (addr_hit[18] & (|(USBDEV_PERMIT[18] & ~reg_be))) |
8753 (addr_hit[19] & (|(USBDEV_PERMIT[19] & ~reg_be))) |
8754 (addr_hit[20] & (|(USBDEV_PERMIT[20] & ~reg_be))) |
8755 (addr_hit[21] & (|(USBDEV_PERMIT[21] & ~reg_be))) |
8756 (addr_hit[22] & (|(USBDEV_PERMIT[22] & ~reg_be))) |
8757 (addr_hit[23] & (|(USBDEV_PERMIT[23] & ~reg_be))) |
8758 (addr_hit[24] & (|(USBDEV_PERMIT[24] & ~reg_be))) |
8759 (addr_hit[25] & (|(USBDEV_PERMIT[25] & ~reg_be))) |
8760 (addr_hit[26] & (|(USBDEV_PERMIT[26] & ~reg_be))) |
8761 (addr_hit[27] & (|(USBDEV_PERMIT[27] & ~reg_be))) |
8762 (addr_hit[28] & (|(USBDEV_PERMIT[28] & ~reg_be))) |
8763 (addr_hit[29] & (|(USBDEV_PERMIT[29] & ~reg_be))) |
8764 (addr_hit[30] & (|(USBDEV_PERMIT[30] & ~reg_be))) |
8765 (addr_hit[31] & (|(USBDEV_PERMIT[31] & ~reg_be))) |
8766 (addr_hit[32] & (|(USBDEV_PERMIT[32] & ~reg_be))) |
8767 (addr_hit[33] & (|(USBDEV_PERMIT[33] & ~reg_be))) |
8768 (addr_hit[34] & (|(USBDEV_PERMIT[34] & ~reg_be))) |
8769 (addr_hit[35] & (|(USBDEV_PERMIT[35] & ~reg_be))) |
8770 (addr_hit[36] & (|(USBDEV_PERMIT[36] & ~reg_be))) |
8771 (addr_hit[37] & (|(USBDEV_PERMIT[37] & ~reg_be))) |
8772 (addr_hit[38] & (|(USBDEV_PERMIT[38] & ~reg_be))) |
8773 (addr_hit[39] & (|(USBDEV_PERMIT[39] & ~reg_be))) |
8774 (addr_hit[40] & (|(USBDEV_PERMIT[40] & ~reg_be))) |
8775 (addr_hit[41] & (|(USBDEV_PERMIT[41] & ~reg_be))) |
8776 (addr_hit[42] & (|(USBDEV_PERMIT[42] & ~reg_be)))));
8777 end
8778
8779 // Generate write-enables
8780 1/1 assign intr_state_we = addr_hit[0] & reg_we & !reg_error;
Tests: T1 T2 T3
8781
8782 1/1 assign intr_state_disconnected_wd = reg_wdata[2];
Tests: T1 T2 T3
8783
8784 1/1 assign intr_state_host_lost_wd = reg_wdata[3];
Tests: T1 T2 T3
8785
8786 1/1 assign intr_state_link_reset_wd = reg_wdata[4];
Tests: T1 T2 T3
8787
8788 1/1 assign intr_state_link_suspend_wd = reg_wdata[5];
Tests: T1 T2 T3
8789
8790 1/1 assign intr_state_link_resume_wd = reg_wdata[6];
Tests: T1 T2 T3
8791
8792 1/1 assign intr_state_av_overflow_wd = reg_wdata[9];
Tests: T1 T2 T3
8793
8794 1/1 assign intr_state_link_in_err_wd = reg_wdata[10];
Tests: T1 T2 T3
8795
8796 1/1 assign intr_state_rx_crc_err_wd = reg_wdata[11];
Tests: T1 T2 T3
8797
8798 1/1 assign intr_state_rx_pid_err_wd = reg_wdata[12];
Tests: T1 T2 T3
8799
8800 1/1 assign intr_state_rx_bitstuff_err_wd = reg_wdata[13];
Tests: T1 T2 T3
8801
8802 1/1 assign intr_state_frame_wd = reg_wdata[14];
Tests: T1 T2 T3
8803
8804 1/1 assign intr_state_powered_wd = reg_wdata[15];
Tests: T1 T2 T3
8805
8806 1/1 assign intr_state_link_out_err_wd = reg_wdata[16];
Tests: T1 T2 T3
8807 1/1 assign intr_enable_we = addr_hit[1] & reg_we & !reg_error;
Tests: T1 T2 T3
8808
8809 1/1 assign intr_enable_pkt_received_wd = reg_wdata[0];
Tests: T1 T2 T3
8810
8811 1/1 assign intr_enable_pkt_sent_wd = reg_wdata[1];
Tests: T1 T2 T3
8812
8813 1/1 assign intr_enable_disconnected_wd = reg_wdata[2];
Tests: T1 T2 T3
8814
8815 1/1 assign intr_enable_host_lost_wd = reg_wdata[3];
Tests: T1 T2 T3
8816
8817 1/1 assign intr_enable_link_reset_wd = reg_wdata[4];
Tests: T1 T2 T3
8818
8819 1/1 assign intr_enable_link_suspend_wd = reg_wdata[5];
Tests: T1 T2 T3
8820
8821 1/1 assign intr_enable_link_resume_wd = reg_wdata[6];
Tests: T1 T2 T3
8822
8823 1/1 assign intr_enable_av_out_empty_wd = reg_wdata[7];
Tests: T1 T2 T3
8824
8825 1/1 assign intr_enable_rx_full_wd = reg_wdata[8];
Tests: T1 T2 T3
8826
8827 1/1 assign intr_enable_av_overflow_wd = reg_wdata[9];
Tests: T1 T2 T3
8828
8829 1/1 assign intr_enable_link_in_err_wd = reg_wdata[10];
Tests: T1 T2 T3
8830
8831 1/1 assign intr_enable_rx_crc_err_wd = reg_wdata[11];
Tests: T1 T2 T3
8832
8833 1/1 assign intr_enable_rx_pid_err_wd = reg_wdata[12];
Tests: T1 T2 T3
8834
8835 1/1 assign intr_enable_rx_bitstuff_err_wd = reg_wdata[13];
Tests: T1 T2 T3
8836
8837 1/1 assign intr_enable_frame_wd = reg_wdata[14];
Tests: T1 T2 T3
8838
8839 1/1 assign intr_enable_powered_wd = reg_wdata[15];
Tests: T1 T2 T3
8840
8841 1/1 assign intr_enable_link_out_err_wd = reg_wdata[16];
Tests: T1 T2 T3
8842
8843 1/1 assign intr_enable_av_setup_empty_wd = reg_wdata[17];
Tests: T1 T2 T3
8844 1/1 assign intr_test_we = addr_hit[2] & reg_we & !reg_error;
Tests: T1 T2 T3
8845
8846 1/1 assign intr_test_pkt_received_wd = reg_wdata[0];
Tests: T1 T2 T3
8847
8848 1/1 assign intr_test_pkt_sent_wd = reg_wdata[1];
Tests: T1 T2 T3
8849
8850 1/1 assign intr_test_disconnected_wd = reg_wdata[2];
Tests: T1 T2 T3
8851
8852 1/1 assign intr_test_host_lost_wd = reg_wdata[3];
Tests: T1 T2 T3
8853
8854 1/1 assign intr_test_link_reset_wd = reg_wdata[4];
Tests: T1 T2 T3
8855
8856 1/1 assign intr_test_link_suspend_wd = reg_wdata[5];
Tests: T1 T2 T3
8857
8858 1/1 assign intr_test_link_resume_wd = reg_wdata[6];
Tests: T1 T2 T3
8859
8860 1/1 assign intr_test_av_out_empty_wd = reg_wdata[7];
Tests: T1 T2 T3
8861
8862 1/1 assign intr_test_rx_full_wd = reg_wdata[8];
Tests: T1 T2 T3
8863
8864 1/1 assign intr_test_av_overflow_wd = reg_wdata[9];
Tests: T1 T2 T3
8865
8866 1/1 assign intr_test_link_in_err_wd = reg_wdata[10];
Tests: T1 T2 T3
8867
8868 1/1 assign intr_test_rx_crc_err_wd = reg_wdata[11];
Tests: T1 T2 T3
8869
8870 1/1 assign intr_test_rx_pid_err_wd = reg_wdata[12];
Tests: T1 T2 T3
8871
8872 1/1 assign intr_test_rx_bitstuff_err_wd = reg_wdata[13];
Tests: T1 T2 T3
8873
8874 1/1 assign intr_test_frame_wd = reg_wdata[14];
Tests: T1 T2 T3
8875
8876 1/1 assign intr_test_powered_wd = reg_wdata[15];
Tests: T1 T2 T3
8877
8878 1/1 assign intr_test_link_out_err_wd = reg_wdata[16];
Tests: T1 T2 T3
8879
8880 1/1 assign intr_test_av_setup_empty_wd = reg_wdata[17];
Tests: T1 T2 T3
8881 1/1 assign alert_test_we = addr_hit[3] & reg_we & !reg_error;
Tests: T1 T2 T3
8882
8883 1/1 assign alert_test_wd = reg_wdata[0];
Tests: T1 T2 T3
8884 1/1 assign usbctrl_we = addr_hit[4] & reg_we & !reg_error;
Tests: T1 T2 T3
8885
8886 1/1 assign usbctrl_enable_wd = reg_wdata[0];
Tests: T1 T2 T3
8887
8888 1/1 assign usbctrl_resume_link_active_wd = reg_wdata[1];
Tests: T1 T2 T3
8889
8890 1/1 assign usbctrl_device_address_wd = reg_wdata[22:16];
Tests: T1 T2 T3
8891 1/1 assign ep_out_enable_we = addr_hit[5] & reg_we & !reg_error;
Tests: T1 T2 T3
8892
8893 1/1 assign ep_out_enable_enable_0_wd = reg_wdata[0];
Tests: T1 T2 T3
8894
8895 1/1 assign ep_out_enable_enable_1_wd = reg_wdata[1];
Tests: T1 T2 T3
8896
8897 1/1 assign ep_out_enable_enable_2_wd = reg_wdata[2];
Tests: T1 T2 T3
8898
8899 1/1 assign ep_out_enable_enable_3_wd = reg_wdata[3];
Tests: T1 T2 T3
8900
8901 1/1 assign ep_out_enable_enable_4_wd = reg_wdata[4];
Tests: T1 T2 T3
8902
8903 1/1 assign ep_out_enable_enable_5_wd = reg_wdata[5];
Tests: T1 T2 T3
8904
8905 1/1 assign ep_out_enable_enable_6_wd = reg_wdata[6];
Tests: T1 T2 T3
8906
8907 1/1 assign ep_out_enable_enable_7_wd = reg_wdata[7];
Tests: T1 T2 T3
8908
8909 1/1 assign ep_out_enable_enable_8_wd = reg_wdata[8];
Tests: T1 T2 T3
8910
8911 1/1 assign ep_out_enable_enable_9_wd = reg_wdata[9];
Tests: T1 T2 T3
8912
8913 1/1 assign ep_out_enable_enable_10_wd = reg_wdata[10];
Tests: T1 T2 T3
8914
8915 1/1 assign ep_out_enable_enable_11_wd = reg_wdata[11];
Tests: T1 T2 T3
8916 1/1 assign ep_in_enable_we = addr_hit[6] & reg_we & !reg_error;
Tests: T1 T2 T3
8917
8918 1/1 assign ep_in_enable_enable_0_wd = reg_wdata[0];
Tests: T1 T2 T3
8919
8920 1/1 assign ep_in_enable_enable_1_wd = reg_wdata[1];
Tests: T1 T2 T3
8921
8922 1/1 assign ep_in_enable_enable_2_wd = reg_wdata[2];
Tests: T1 T2 T3
8923
8924 1/1 assign ep_in_enable_enable_3_wd = reg_wdata[3];
Tests: T1 T2 T3
8925
8926 1/1 assign ep_in_enable_enable_4_wd = reg_wdata[4];
Tests: T1 T2 T3
8927
8928 1/1 assign ep_in_enable_enable_5_wd = reg_wdata[5];
Tests: T1 T2 T3
8929
8930 1/1 assign ep_in_enable_enable_6_wd = reg_wdata[6];
Tests: T1 T2 T3
8931
8932 1/1 assign ep_in_enable_enable_7_wd = reg_wdata[7];
Tests: T1 T2 T3
8933
8934 1/1 assign ep_in_enable_enable_8_wd = reg_wdata[8];
Tests: T1 T2 T3
8935
8936 1/1 assign ep_in_enable_enable_9_wd = reg_wdata[9];
Tests: T1 T2 T3
8937
8938 1/1 assign ep_in_enable_enable_10_wd = reg_wdata[10];
Tests: T1 T2 T3
8939
8940 1/1 assign ep_in_enable_enable_11_wd = reg_wdata[11];
Tests: T1 T2 T3
8941 1/1 assign usbstat_re = addr_hit[7] & reg_re & !reg_error;
Tests: T1 T2 T3
8942 1/1 assign avoutbuffer_we = addr_hit[8] & reg_we & !reg_error;
Tests: T1 T2 T3
8943
8944 1/1 assign avoutbuffer_wd = reg_wdata[4:0];
Tests: T1 T2 T3
8945 1/1 assign avsetupbuffer_we = addr_hit[9] & reg_we & !reg_error;
Tests: T1 T2 T3
8946
8947 1/1 assign avsetupbuffer_wd = reg_wdata[4:0];
Tests: T1 T2 T3
8948 1/1 assign rxfifo_re = addr_hit[10] & reg_re & !reg_error;
Tests: T1 T2 T3
8949 1/1 assign rxenable_setup_we = addr_hit[11] & reg_we & !reg_error;
Tests: T1 T2 T3
8950
8951 1/1 assign rxenable_setup_setup_0_wd = reg_wdata[0];
Tests: T1 T2 T3
8952
8953 1/1 assign rxenable_setup_setup_1_wd = reg_wdata[1];
Tests: T1 T2 T3
8954
8955 1/1 assign rxenable_setup_setup_2_wd = reg_wdata[2];
Tests: T1 T2 T3
8956
8957 1/1 assign rxenable_setup_setup_3_wd = reg_wdata[3];
Tests: T1 T2 T3
8958
8959 1/1 assign rxenable_setup_setup_4_wd = reg_wdata[4];
Tests: T1 T2 T3
8960
8961 1/1 assign rxenable_setup_setup_5_wd = reg_wdata[5];
Tests: T1 T2 T3
8962
8963 1/1 assign rxenable_setup_setup_6_wd = reg_wdata[6];
Tests: T1 T2 T3
8964
8965 1/1 assign rxenable_setup_setup_7_wd = reg_wdata[7];
Tests: T1 T2 T3
8966
8967 1/1 assign rxenable_setup_setup_8_wd = reg_wdata[8];
Tests: T1 T2 T3
8968
8969 1/1 assign rxenable_setup_setup_9_wd = reg_wdata[9];
Tests: T1 T2 T3
8970
8971 1/1 assign rxenable_setup_setup_10_wd = reg_wdata[10];
Tests: T1 T2 T3
8972
8973 1/1 assign rxenable_setup_setup_11_wd = reg_wdata[11];
Tests: T1 T2 T3
8974 1/1 assign rxenable_out_we = addr_hit[12] & reg_we & !reg_error;
Tests: T1 T2 T3
8975
8976 1/1 assign rxenable_out_out_0_wd = reg_wdata[0];
Tests: T1 T2 T3
8977
8978 1/1 assign rxenable_out_out_1_wd = reg_wdata[1];
Tests: T1 T2 T3
8979
8980 1/1 assign rxenable_out_out_2_wd = reg_wdata[2];
Tests: T1 T2 T3
8981
8982 1/1 assign rxenable_out_out_3_wd = reg_wdata[3];
Tests: T1 T2 T3
8983
8984 1/1 assign rxenable_out_out_4_wd = reg_wdata[4];
Tests: T1 T2 T3
8985
8986 1/1 assign rxenable_out_out_5_wd = reg_wdata[5];
Tests: T1 T2 T3
8987
8988 1/1 assign rxenable_out_out_6_wd = reg_wdata[6];
Tests: T1 T2 T3
8989
8990 1/1 assign rxenable_out_out_7_wd = reg_wdata[7];
Tests: T1 T2 T3
8991
8992 1/1 assign rxenable_out_out_8_wd = reg_wdata[8];
Tests: T1 T2 T3
8993
8994 1/1 assign rxenable_out_out_9_wd = reg_wdata[9];
Tests: T1 T2 T3
8995
8996 1/1 assign rxenable_out_out_10_wd = reg_wdata[10];
Tests: T1 T2 T3
8997
8998 1/1 assign rxenable_out_out_11_wd = reg_wdata[11];
Tests: T1 T2 T3
8999 1/1 assign set_nak_out_we = addr_hit[13] & reg_we & !reg_error;
Tests: T1 T2 T3
9000
9001 1/1 assign set_nak_out_enable_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9002
9003 1/1 assign set_nak_out_enable_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9004
9005 1/1 assign set_nak_out_enable_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9006
9007 1/1 assign set_nak_out_enable_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9008
9009 1/1 assign set_nak_out_enable_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9010
9011 1/1 assign set_nak_out_enable_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9012
9013 1/1 assign set_nak_out_enable_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9014
9015 1/1 assign set_nak_out_enable_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9016
9017 1/1 assign set_nak_out_enable_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9018
9019 1/1 assign set_nak_out_enable_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9020
9021 1/1 assign set_nak_out_enable_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9022
9023 1/1 assign set_nak_out_enable_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9024 1/1 assign in_sent_we = addr_hit[14] & reg_we & !reg_error;
Tests: T1 T2 T3
9025
9026 1/1 assign in_sent_sent_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9027
9028 1/1 assign in_sent_sent_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9029
9030 1/1 assign in_sent_sent_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9031
9032 1/1 assign in_sent_sent_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9033
9034 1/1 assign in_sent_sent_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9035
9036 1/1 assign in_sent_sent_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9037
9038 1/1 assign in_sent_sent_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9039
9040 1/1 assign in_sent_sent_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9041
9042 1/1 assign in_sent_sent_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9043
9044 1/1 assign in_sent_sent_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9045
9046 1/1 assign in_sent_sent_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9047
9048 1/1 assign in_sent_sent_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9049 1/1 assign out_stall_we = addr_hit[15] & reg_we & !reg_error;
Tests: T1 T2 T3
9050
9051 1/1 assign out_stall_endpoint_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9052
9053 1/1 assign out_stall_endpoint_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9054
9055 1/1 assign out_stall_endpoint_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9056
9057 1/1 assign out_stall_endpoint_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9058
9059 1/1 assign out_stall_endpoint_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9060
9061 1/1 assign out_stall_endpoint_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9062
9063 1/1 assign out_stall_endpoint_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9064
9065 1/1 assign out_stall_endpoint_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9066
9067 1/1 assign out_stall_endpoint_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9068
9069 1/1 assign out_stall_endpoint_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9070
9071 1/1 assign out_stall_endpoint_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9072
9073 1/1 assign out_stall_endpoint_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9074 1/1 assign in_stall_we = addr_hit[16] & reg_we & !reg_error;
Tests: T1 T2 T3
9075
9076 1/1 assign in_stall_endpoint_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9077
9078 1/1 assign in_stall_endpoint_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9079
9080 1/1 assign in_stall_endpoint_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9081
9082 1/1 assign in_stall_endpoint_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9083
9084 1/1 assign in_stall_endpoint_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9085
9086 1/1 assign in_stall_endpoint_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9087
9088 1/1 assign in_stall_endpoint_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9089
9090 1/1 assign in_stall_endpoint_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9091
9092 1/1 assign in_stall_endpoint_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9093
9094 1/1 assign in_stall_endpoint_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9095
9096 1/1 assign in_stall_endpoint_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9097
9098 1/1 assign in_stall_endpoint_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9099 1/1 assign configin_0_we = addr_hit[17] & reg_we & !reg_error;
Tests: T1 T2 T3
9100
9101 1/1 assign configin_0_buffer_0_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9102
9103 1/1 assign configin_0_size_0_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9104
9105 1/1 assign configin_0_sending_0_wd = reg_wdata[29];
Tests: T1 T2 T3
9106
9107 1/1 assign configin_0_pend_0_wd = reg_wdata[30];
Tests: T1 T2 T3
9108
9109 1/1 assign configin_0_rdy_0_wd = reg_wdata[31];
Tests: T1 T2 T3
9110 1/1 assign configin_1_we = addr_hit[18] & reg_we & !reg_error;
Tests: T1 T2 T3
9111
9112 1/1 assign configin_1_buffer_1_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9113
9114 1/1 assign configin_1_size_1_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9115
9116 1/1 assign configin_1_sending_1_wd = reg_wdata[29];
Tests: T1 T2 T3
9117
9118 1/1 assign configin_1_pend_1_wd = reg_wdata[30];
Tests: T1 T2 T3
9119
9120 1/1 assign configin_1_rdy_1_wd = reg_wdata[31];
Tests: T1 T2 T3
9121 1/1 assign configin_2_we = addr_hit[19] & reg_we & !reg_error;
Tests: T1 T2 T3
9122
9123 1/1 assign configin_2_buffer_2_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9124
9125 1/1 assign configin_2_size_2_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9126
9127 1/1 assign configin_2_sending_2_wd = reg_wdata[29];
Tests: T1 T2 T3
9128
9129 1/1 assign configin_2_pend_2_wd = reg_wdata[30];
Tests: T1 T2 T3
9130
9131 1/1 assign configin_2_rdy_2_wd = reg_wdata[31];
Tests: T1 T2 T3
9132 1/1 assign configin_3_we = addr_hit[20] & reg_we & !reg_error;
Tests: T1 T2 T3
9133
9134 1/1 assign configin_3_buffer_3_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9135
9136 1/1 assign configin_3_size_3_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9137
9138 1/1 assign configin_3_sending_3_wd = reg_wdata[29];
Tests: T1 T2 T3
9139
9140 1/1 assign configin_3_pend_3_wd = reg_wdata[30];
Tests: T1 T2 T3
9141
9142 1/1 assign configin_3_rdy_3_wd = reg_wdata[31];
Tests: T1 T2 T3
9143 1/1 assign configin_4_we = addr_hit[21] & reg_we & !reg_error;
Tests: T1 T2 T3
9144
9145 1/1 assign configin_4_buffer_4_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9146
9147 1/1 assign configin_4_size_4_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9148
9149 1/1 assign configin_4_sending_4_wd = reg_wdata[29];
Tests: T1 T2 T3
9150
9151 1/1 assign configin_4_pend_4_wd = reg_wdata[30];
Tests: T1 T2 T3
9152
9153 1/1 assign configin_4_rdy_4_wd = reg_wdata[31];
Tests: T1 T2 T3
9154 1/1 assign configin_5_we = addr_hit[22] & reg_we & !reg_error;
Tests: T1 T2 T3
9155
9156 1/1 assign configin_5_buffer_5_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9157
9158 1/1 assign configin_5_size_5_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9159
9160 1/1 assign configin_5_sending_5_wd = reg_wdata[29];
Tests: T1 T2 T3
9161
9162 1/1 assign configin_5_pend_5_wd = reg_wdata[30];
Tests: T1 T2 T3
9163
9164 1/1 assign configin_5_rdy_5_wd = reg_wdata[31];
Tests: T1 T2 T3
9165 1/1 assign configin_6_we = addr_hit[23] & reg_we & !reg_error;
Tests: T1 T2 T3
9166
9167 1/1 assign configin_6_buffer_6_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9168
9169 1/1 assign configin_6_size_6_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9170
9171 1/1 assign configin_6_sending_6_wd = reg_wdata[29];
Tests: T1 T2 T3
9172
9173 1/1 assign configin_6_pend_6_wd = reg_wdata[30];
Tests: T1 T2 T3
9174
9175 1/1 assign configin_6_rdy_6_wd = reg_wdata[31];
Tests: T1 T2 T3
9176 1/1 assign configin_7_we = addr_hit[24] & reg_we & !reg_error;
Tests: T1 T2 T3
9177
9178 1/1 assign configin_7_buffer_7_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9179
9180 1/1 assign configin_7_size_7_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9181
9182 1/1 assign configin_7_sending_7_wd = reg_wdata[29];
Tests: T1 T2 T3
9183
9184 1/1 assign configin_7_pend_7_wd = reg_wdata[30];
Tests: T1 T2 T3
9185
9186 1/1 assign configin_7_rdy_7_wd = reg_wdata[31];
Tests: T1 T2 T3
9187 1/1 assign configin_8_we = addr_hit[25] & reg_we & !reg_error;
Tests: T1 T2 T3
9188
9189 1/1 assign configin_8_buffer_8_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9190
9191 1/1 assign configin_8_size_8_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9192
9193 1/1 assign configin_8_sending_8_wd = reg_wdata[29];
Tests: T1 T2 T3
9194
9195 1/1 assign configin_8_pend_8_wd = reg_wdata[30];
Tests: T1 T2 T3
9196
9197 1/1 assign configin_8_rdy_8_wd = reg_wdata[31];
Tests: T1 T2 T3
9198 1/1 assign configin_9_we = addr_hit[26] & reg_we & !reg_error;
Tests: T1 T2 T3
9199
9200 1/1 assign configin_9_buffer_9_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9201
9202 1/1 assign configin_9_size_9_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9203
9204 1/1 assign configin_9_sending_9_wd = reg_wdata[29];
Tests: T1 T2 T3
9205
9206 1/1 assign configin_9_pend_9_wd = reg_wdata[30];
Tests: T1 T2 T3
9207
9208 1/1 assign configin_9_rdy_9_wd = reg_wdata[31];
Tests: T1 T2 T3
9209 1/1 assign configin_10_we = addr_hit[27] & reg_we & !reg_error;
Tests: T1 T2 T3
9210
9211 1/1 assign configin_10_buffer_10_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9212
9213 1/1 assign configin_10_size_10_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9214
9215 1/1 assign configin_10_sending_10_wd = reg_wdata[29];
Tests: T1 T2 T3
9216
9217 1/1 assign configin_10_pend_10_wd = reg_wdata[30];
Tests: T1 T2 T3
9218
9219 1/1 assign configin_10_rdy_10_wd = reg_wdata[31];
Tests: T1 T2 T3
9220 1/1 assign configin_11_we = addr_hit[28] & reg_we & !reg_error;
Tests: T1 T2 T3
9221
9222 1/1 assign configin_11_buffer_11_wd = reg_wdata[4:0];
Tests: T1 T2 T3
9223
9224 1/1 assign configin_11_size_11_wd = reg_wdata[14:8];
Tests: T1 T2 T3
9225
9226 1/1 assign configin_11_sending_11_wd = reg_wdata[29];
Tests: T1 T2 T3
9227
9228 1/1 assign configin_11_pend_11_wd = reg_wdata[30];
Tests: T1 T2 T3
9229
9230 1/1 assign configin_11_rdy_11_wd = reg_wdata[31];
Tests: T1 T2 T3
9231 1/1 assign out_iso_we = addr_hit[29] & reg_we & !reg_error;
Tests: T1 T2 T3
9232
9233 1/1 assign out_iso_iso_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9234
9235 1/1 assign out_iso_iso_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9236
9237 1/1 assign out_iso_iso_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9238
9239 1/1 assign out_iso_iso_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9240
9241 1/1 assign out_iso_iso_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9242
9243 1/1 assign out_iso_iso_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9244
9245 1/1 assign out_iso_iso_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9246
9247 1/1 assign out_iso_iso_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9248
9249 1/1 assign out_iso_iso_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9250
9251 1/1 assign out_iso_iso_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9252
9253 1/1 assign out_iso_iso_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9254
9255 1/1 assign out_iso_iso_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9256 1/1 assign in_iso_we = addr_hit[30] & reg_we & !reg_error;
Tests: T1 T2 T3
9257
9258 1/1 assign in_iso_iso_0_wd = reg_wdata[0];
Tests: T1 T2 T3
9259
9260 1/1 assign in_iso_iso_1_wd = reg_wdata[1];
Tests: T1 T2 T3
9261
9262 1/1 assign in_iso_iso_2_wd = reg_wdata[2];
Tests: T1 T2 T3
9263
9264 1/1 assign in_iso_iso_3_wd = reg_wdata[3];
Tests: T1 T2 T3
9265
9266 1/1 assign in_iso_iso_4_wd = reg_wdata[4];
Tests: T1 T2 T3
9267
9268 1/1 assign in_iso_iso_5_wd = reg_wdata[5];
Tests: T1 T2 T3
9269
9270 1/1 assign in_iso_iso_6_wd = reg_wdata[6];
Tests: T1 T2 T3
9271
9272 1/1 assign in_iso_iso_7_wd = reg_wdata[7];
Tests: T1 T2 T3
9273
9274 1/1 assign in_iso_iso_8_wd = reg_wdata[8];
Tests: T1 T2 T3
9275
9276 1/1 assign in_iso_iso_9_wd = reg_wdata[9];
Tests: T1 T2 T3
9277
9278 1/1 assign in_iso_iso_10_wd = reg_wdata[10];
Tests: T1 T2 T3
9279
9280 1/1 assign in_iso_iso_11_wd = reg_wdata[11];
Tests: T1 T2 T3
9281 1/1 assign out_data_toggle_re = addr_hit[31] & reg_re & !reg_error;
Tests: T1 T2 T3
9282 1/1 assign out_data_toggle_we = addr_hit[31] & reg_we & !reg_error;
Tests: T1 T2 T3
9283
9284 1/1 assign out_data_toggle_status_wd = reg_wdata[11:0];
Tests: T1 T2 T3
9285
9286 1/1 assign out_data_toggle_mask_wd = reg_wdata[27:16];
Tests: T1 T2 T3
9287 1/1 assign in_data_toggle_re = addr_hit[32] & reg_re & !reg_error;
Tests: T1 T2 T3
9288 1/1 assign in_data_toggle_we = addr_hit[32] & reg_we & !reg_error;
Tests: T1 T2 T3
9289
9290 1/1 assign in_data_toggle_status_wd = reg_wdata[11:0];
Tests: T1 T2 T3
9291
9292 1/1 assign in_data_toggle_mask_wd = reg_wdata[27:16];
Tests: T1 T2 T3
9293 1/1 assign phy_pins_sense_re = addr_hit[33] & reg_re & !reg_error;
Tests: T1 T2 T3
9294 1/1 assign phy_pins_drive_we = addr_hit[34] & reg_we & !reg_error;
Tests: T1 T2 T3
9295
9296 1/1 assign phy_pins_drive_dp_o_wd = reg_wdata[0];
Tests: T1 T2 T3
9297
9298 1/1 assign phy_pins_drive_dn_o_wd = reg_wdata[1];
Tests: T1 T2 T3
9299
9300 1/1 assign phy_pins_drive_d_o_wd = reg_wdata[2];
Tests: T1 T2 T3
9301
9302 1/1 assign phy_pins_drive_se0_o_wd = reg_wdata[3];
Tests: T1 T2 T3
9303
9304 1/1 assign phy_pins_drive_oe_o_wd = reg_wdata[4];
Tests: T1 T2 T3
9305
9306 1/1 assign phy_pins_drive_rx_enable_o_wd = reg_wdata[5];
Tests: T1 T2 T3
9307
9308 1/1 assign phy_pins_drive_dp_pullup_en_o_wd = reg_wdata[6];
Tests: T1 T2 T3
9309
9310 1/1 assign phy_pins_drive_dn_pullup_en_o_wd = reg_wdata[7];
Tests: T1 T2 T3
9311
9312 1/1 assign phy_pins_drive_en_wd = reg_wdata[16];
Tests: T1 T2 T3
9313 1/1 assign phy_config_we = addr_hit[35] & reg_we & !reg_error;
Tests: T1 T2 T3
9314
9315 1/1 assign phy_config_use_diff_rcvr_wd = reg_wdata[0];
Tests: T1 T2 T3
9316
9317 1/1 assign phy_config_tx_use_d_se0_wd = reg_wdata[1];
Tests: T1 T2 T3
9318
9319 1/1 assign phy_config_eop_single_bit_wd = reg_wdata[2];
Tests: T1 T2 T3
9320
9321 1/1 assign phy_config_pinflip_wd = reg_wdata[5];
Tests: T1 T2 T3
9322
9323 1/1 assign phy_config_usb_ref_disable_wd = reg_wdata[6];
Tests: T1 T2 T3
9324
9325 1/1 assign phy_config_tx_osc_test_mode_wd = reg_wdata[7];
Tests: T1 T2 T3
9326 1/1 assign wake_control_we = addr_hit[36] & reg_we & !reg_error;
Tests: T1 T2 T3
9327
9328
9329 1/1 assign fifo_ctrl_we = addr_hit[38] & reg_we & !reg_error;
Tests: T1 T2 T3
9330
9331 1/1 assign fifo_ctrl_avout_rst_wd = reg_wdata[0];
Tests: T1 T2 T3
9332
9333 1/1 assign fifo_ctrl_avsetup_rst_wd = reg_wdata[1];
Tests: T1 T2 T3
9334
9335 1/1 assign fifo_ctrl_rx_rst_wd = reg_wdata[2];
Tests: T1 T2 T3
9336 1/1 assign count_out_re = addr_hit[39] & reg_re & !reg_error;
Tests: T1 T2 T3
9337 1/1 assign count_out_we = addr_hit[39] & reg_we & !reg_error;
Tests: T1 T2 T3
9338
9339 1/1 assign count_out_datatog_out_wd = reg_wdata[12];
Tests: T1 T2 T3
9340
9341 1/1 assign count_out_drop_rx_wd = reg_wdata[13];
Tests: T1 T2 T3
9342
9343 1/1 assign count_out_drop_avout_wd = reg_wdata[14];
Tests: T1 T2 T3
9344
9345 1/1 assign count_out_ign_avsetup_wd = reg_wdata[15];
Tests: T1 T2 T3
9346
9347 1/1 assign count_out_endpoints_wd = reg_wdata[27:16];
Tests: T1 T2 T3
9348
9349 1/1 assign count_out_rst_wd = reg_wdata[31];
Tests: T1 T2 T3
9350 1/1 assign count_in_re = addr_hit[40] & reg_re & !reg_error;
Tests: T1 T2 T3
9351 1/1 assign count_in_we = addr_hit[40] & reg_we & !reg_error;
Tests: T1 T2 T3
9352
9353 1/1 assign count_in_nodata_wd = reg_wdata[13];
Tests: T1 T2 T3
9354
9355 1/1 assign count_in_nak_wd = reg_wdata[14];
Tests: T1 T2 T3
9356
9357 1/1 assign count_in_timeout_wd = reg_wdata[15];
Tests: T1 T2 T3
9358
9359 1/1 assign count_in_endpoints_wd = reg_wdata[27:16];
Tests: T1 T2 T3
9360
9361 1/1 assign count_in_rst_wd = reg_wdata[31];
Tests: T1 T2 T3
9362 1/1 assign count_nodata_in_re = addr_hit[41] & reg_re & !reg_error;
Tests: T1 T2 T3
9363 1/1 assign count_nodata_in_we = addr_hit[41] & reg_we & !reg_error;
Tests: T1 T2 T3
9364
9365 1/1 assign count_nodata_in_endpoints_wd = reg_wdata[27:16];
Tests: T1 T2 T3
9366
9367 1/1 assign count_nodata_in_rst_wd = reg_wdata[31];
Tests: T1 T2 T3
9368 1/1 assign count_errors_re = addr_hit[42] & reg_re & !reg_error;
Tests: T1 T2 T3
9369 1/1 assign count_errors_we = addr_hit[42] & reg_we & !reg_error;
Tests: T1 T2 T3
9370
9371 1/1 assign count_errors_pid_invalid_wd = reg_wdata[27];
Tests: T1 T2 T3
9372
9373 1/1 assign count_errors_bitstuff_wd = reg_wdata[28];
Tests: T1 T2 T3
9374
9375 1/1 assign count_errors_crc16_wd = reg_wdata[29];
Tests: T1 T2 T3
9376
9377 1/1 assign count_errors_crc5_wd = reg_wdata[30];
Tests: T1 T2 T3
9378
9379 1/1 assign count_errors_rst_wd = reg_wdata[31];
Tests: T1 T2 T3
9380
9381 // Assign write-enables to checker logic vector.
9382 always_comb begin
9383 1/1 reg_we_check = '0;
Tests: T1 T2 T3
9384 1/1 reg_we_check[0] = intr_state_we;
Tests: T1 T2 T3
9385 1/1 reg_we_check[1] = intr_enable_we;
Tests: T1 T2 T3
9386 1/1 reg_we_check[2] = intr_test_we;
Tests: T1 T2 T3
9387 1/1 reg_we_check[3] = alert_test_we;
Tests: T1 T2 T3
9388 1/1 reg_we_check[4] = usbctrl_we;
Tests: T1 T2 T3
9389 1/1 reg_we_check[5] = ep_out_enable_we;
Tests: T1 T2 T3
9390 1/1 reg_we_check[6] = ep_in_enable_we;
Tests: T1 T2 T3
9391 1/1 reg_we_check[7] = 1'b0;
Tests: T1 T2 T3
9392 1/1 reg_we_check[8] = avoutbuffer_we;
Tests: T1 T2 T3
9393 1/1 reg_we_check[9] = avsetupbuffer_we;
Tests: T1 T2 T3
9394 1/1 reg_we_check[10] = 1'b0;
Tests: T1 T2 T3
9395 1/1 reg_we_check[11] = rxenable_setup_we;
Tests: T1 T2 T3
9396 1/1 reg_we_check[12] = rxenable_out_we;
Tests: T1 T2 T3
9397 1/1 reg_we_check[13] = set_nak_out_we;
Tests: T1 T2 T3
9398 1/1 reg_we_check[14] = in_sent_we;
Tests: T1 T2 T3
9399 1/1 reg_we_check[15] = out_stall_we;
Tests: T1 T2 T3
9400 1/1 reg_we_check[16] = in_stall_we;
Tests: T1 T2 T3
9401 1/1 reg_we_check[17] = configin_0_we;
Tests: T1 T2 T3
9402 1/1 reg_we_check[18] = configin_1_we;
Tests: T1 T2 T3
9403 1/1 reg_we_check[19] = configin_2_we;
Tests: T1 T2 T3
9404 1/1 reg_we_check[20] = configin_3_we;
Tests: T1 T2 T3
9405 1/1 reg_we_check[21] = configin_4_we;
Tests: T1 T2 T3
9406 1/1 reg_we_check[22] = configin_5_we;
Tests: T1 T2 T3
9407 1/1 reg_we_check[23] = configin_6_we;
Tests: T1 T2 T3
9408 1/1 reg_we_check[24] = configin_7_we;
Tests: T1 T2 T3
9409 1/1 reg_we_check[25] = configin_8_we;
Tests: T1 T2 T3
9410 1/1 reg_we_check[26] = configin_9_we;
Tests: T1 T2 T3
9411 1/1 reg_we_check[27] = configin_10_we;
Tests: T1 T2 T3
9412 1/1 reg_we_check[28] = configin_11_we;
Tests: T1 T2 T3
9413 1/1 reg_we_check[29] = out_iso_we;
Tests: T1 T2 T3
9414 1/1 reg_we_check[30] = in_iso_we;
Tests: T1 T2 T3
9415 1/1 reg_we_check[31] = out_data_toggle_we;
Tests: T1 T2 T3
9416 1/1 reg_we_check[32] = in_data_toggle_we;
Tests: T1 T2 T3
9417 1/1 reg_we_check[33] = 1'b0;
Tests: T1 T2 T3
9418 1/1 reg_we_check[34] = phy_pins_drive_we;
Tests: T1 T2 T3
9419 1/1 reg_we_check[35] = phy_config_we;
Tests: T1 T2 T3
9420 1/1 reg_we_check[36] = wake_control_we;
Tests: T1 T2 T3
9421 1/1 reg_we_check[37] = 1'b0;
Tests: T1 T2 T3
9422 1/1 reg_we_check[38] = fifo_ctrl_we;
Tests: T1 T2 T3
9423 1/1 reg_we_check[39] = count_out_we;
Tests: T1 T2 T3
9424 1/1 reg_we_check[40] = count_in_we;
Tests: T1 T2 T3
9425 1/1 reg_we_check[41] = count_nodata_in_we;
Tests: T1 T2 T3
9426 1/1 reg_we_check[42] = count_errors_we;
Tests: T1 T2 T3
9427 end
9428
9429 // Read data return
9430 always_comb begin
9431 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
9432 1/1 unique case (1'b1)
Tests: T1 T2 T3
9433 addr_hit[0]: begin
9434 1/1 reg_rdata_next[0] = intr_state_pkt_received_qs;
Tests: T1 T2 T3
9435 1/1 reg_rdata_next[1] = intr_state_pkt_sent_qs;
Tests: T1 T2 T3
9436 1/1 reg_rdata_next[2] = intr_state_disconnected_qs;
Tests: T1 T2 T3
9437 1/1 reg_rdata_next[3] = intr_state_host_lost_qs;
Tests: T1 T2 T3
9438 1/1 reg_rdata_next[4] = intr_state_link_reset_qs;
Tests: T1 T2 T3
9439 1/1 reg_rdata_next[5] = intr_state_link_suspend_qs;
Tests: T1 T2 T3
9440 1/1 reg_rdata_next[6] = intr_state_link_resume_qs;
Tests: T1 T2 T3
9441 1/1 reg_rdata_next[7] = intr_state_av_out_empty_qs;
Tests: T1 T2 T3
9442 1/1 reg_rdata_next[8] = intr_state_rx_full_qs;
Tests: T1 T2 T3
9443 1/1 reg_rdata_next[9] = intr_state_av_overflow_qs;
Tests: T1 T2 T3
9444 1/1 reg_rdata_next[10] = intr_state_link_in_err_qs;
Tests: T1 T2 T3
9445 1/1 reg_rdata_next[11] = intr_state_rx_crc_err_qs;
Tests: T1 T2 T3
9446 1/1 reg_rdata_next[12] = intr_state_rx_pid_err_qs;
Tests: T1 T2 T3
9447 1/1 reg_rdata_next[13] = intr_state_rx_bitstuff_err_qs;
Tests: T1 T2 T3
9448 1/1 reg_rdata_next[14] = intr_state_frame_qs;
Tests: T1 T2 T3
9449 1/1 reg_rdata_next[15] = intr_state_powered_qs;
Tests: T1 T2 T3
9450 1/1 reg_rdata_next[16] = intr_state_link_out_err_qs;
Tests: T1 T2 T3
9451 1/1 reg_rdata_next[17] = intr_state_av_setup_empty_qs;
Tests: T1 T2 T3
9452 end
9453
9454 addr_hit[1]: begin
9455 1/1 reg_rdata_next[0] = intr_enable_pkt_received_qs;
Tests: T2 T3 T28
9456 1/1 reg_rdata_next[1] = intr_enable_pkt_sent_qs;
Tests: T2 T3 T28
9457 1/1 reg_rdata_next[2] = intr_enable_disconnected_qs;
Tests: T2 T3 T28
9458 1/1 reg_rdata_next[3] = intr_enable_host_lost_qs;
Tests: T2 T3 T28
9459 1/1 reg_rdata_next[4] = intr_enable_link_reset_qs;
Tests: T2 T3 T28
9460 1/1 reg_rdata_next[5] = intr_enable_link_suspend_qs;
Tests: T2 T3 T28
9461 1/1 reg_rdata_next[6] = intr_enable_link_resume_qs;
Tests: T2 T3 T28
9462 1/1 reg_rdata_next[7] = intr_enable_av_out_empty_qs;
Tests: T2 T3 T28
9463 1/1 reg_rdata_next[8] = intr_enable_rx_full_qs;
Tests: T2 T3 T28
9464 1/1 reg_rdata_next[9] = intr_enable_av_overflow_qs;
Tests: T2 T3 T28
9465 1/1 reg_rdata_next[10] = intr_enable_link_in_err_qs;
Tests: T2 T3 T28
9466 1/1 reg_rdata_next[11] = intr_enable_rx_crc_err_qs;
Tests: T2 T3 T28
9467 1/1 reg_rdata_next[12] = intr_enable_rx_pid_err_qs;
Tests: T2 T3 T28
9468 1/1 reg_rdata_next[13] = intr_enable_rx_bitstuff_err_qs;
Tests: T2 T3 T28
9469 1/1 reg_rdata_next[14] = intr_enable_frame_qs;
Tests: T2 T3 T28
9470 1/1 reg_rdata_next[15] = intr_enable_powered_qs;
Tests: T2 T3 T28
9471 1/1 reg_rdata_next[16] = intr_enable_link_out_err_qs;
Tests: T2 T3 T28
9472 1/1 reg_rdata_next[17] = intr_enable_av_setup_empty_qs;
Tests: T2 T3 T28
9473 end
9474
9475 addr_hit[2]: begin
9476 1/1 reg_rdata_next[0] = '0;
Tests: T2 T28 T30
9477 1/1 reg_rdata_next[1] = '0;
Tests: T2 T28 T30
9478 1/1 reg_rdata_next[2] = '0;
Tests: T2 T28 T30
9479 1/1 reg_rdata_next[3] = '0;
Tests: T2 T28 T30
9480 1/1 reg_rdata_next[4] = '0;
Tests: T2 T28 T30
9481 1/1 reg_rdata_next[5] = '0;
Tests: T2 T28 T30
9482 1/1 reg_rdata_next[6] = '0;
Tests: T2 T28 T30
9483 1/1 reg_rdata_next[7] = '0;
Tests: T2 T28 T30
9484 1/1 reg_rdata_next[8] = '0;
Tests: T2 T28 T30
9485 1/1 reg_rdata_next[9] = '0;
Tests: T2 T28 T30
9486 1/1 reg_rdata_next[10] = '0;
Tests: T2 T28 T30
9487 1/1 reg_rdata_next[11] = '0;
Tests: T2 T28 T30
9488 1/1 reg_rdata_next[12] = '0;
Tests: T2 T28 T30
9489 1/1 reg_rdata_next[13] = '0;
Tests: T2 T28 T30
9490 1/1 reg_rdata_next[14] = '0;
Tests: T2 T28 T30
9491 1/1 reg_rdata_next[15] = '0;
Tests: T2 T28 T30
9492 1/1 reg_rdata_next[16] = '0;
Tests: T2 T28 T30
9493 1/1 reg_rdata_next[17] = '0;
Tests: T2 T28 T30
9494 end
9495
9496 addr_hit[3]: begin
9497 1/1 reg_rdata_next[0] = '0;
Tests: T2 T28 T30
9498 end
9499
9500 addr_hit[4]: begin
9501 1/1 reg_rdata_next[0] = usbctrl_enable_qs;
Tests: T1 T2 T3
9502 1/1 reg_rdata_next[1] = '0;
Tests: T1 T2 T3
9503 1/1 reg_rdata_next[22:16] = usbctrl_device_address_qs;
Tests: T1 T2 T3
9504 end
9505
9506 addr_hit[5]: begin
9507 1/1 reg_rdata_next[0] = ep_out_enable_enable_0_qs;
Tests: T1 T2 T3
9508 1/1 reg_rdata_next[1] = ep_out_enable_enable_1_qs;
Tests: T1 T2 T3
9509 1/1 reg_rdata_next[2] = ep_out_enable_enable_2_qs;
Tests: T1 T2 T3
9510 1/1 reg_rdata_next[3] = ep_out_enable_enable_3_qs;
Tests: T1 T2 T3
9511 1/1 reg_rdata_next[4] = ep_out_enable_enable_4_qs;
Tests: T1 T2 T3
9512 1/1 reg_rdata_next[5] = ep_out_enable_enable_5_qs;
Tests: T1 T2 T3
9513 1/1 reg_rdata_next[6] = ep_out_enable_enable_6_qs;
Tests: T1 T2 T3
9514 1/1 reg_rdata_next[7] = ep_out_enable_enable_7_qs;
Tests: T1 T2 T3
9515 1/1 reg_rdata_next[8] = ep_out_enable_enable_8_qs;
Tests: T1 T2 T3
9516 1/1 reg_rdata_next[9] = ep_out_enable_enable_9_qs;
Tests: T1 T2 T3
9517 1/1 reg_rdata_next[10] = ep_out_enable_enable_10_qs;
Tests: T1 T2 T3
9518 1/1 reg_rdata_next[11] = ep_out_enable_enable_11_qs;
Tests: T1 T2 T3
9519 end
9520
9521 addr_hit[6]: begin
9522 1/1 reg_rdata_next[0] = ep_in_enable_enable_0_qs;
Tests: T2 T28 T29
9523 1/1 reg_rdata_next[1] = ep_in_enable_enable_1_qs;
Tests: T2 T28 T29
9524 1/1 reg_rdata_next[2] = ep_in_enable_enable_2_qs;
Tests: T2 T28 T29
9525 1/1 reg_rdata_next[3] = ep_in_enable_enable_3_qs;
Tests: T2 T28 T29
9526 1/1 reg_rdata_next[4] = ep_in_enable_enable_4_qs;
Tests: T2 T28 T29
9527 1/1 reg_rdata_next[5] = ep_in_enable_enable_5_qs;
Tests: T2 T28 T29
9528 1/1 reg_rdata_next[6] = ep_in_enable_enable_6_qs;
Tests: T2 T28 T29
9529 1/1 reg_rdata_next[7] = ep_in_enable_enable_7_qs;
Tests: T2 T28 T29
9530 1/1 reg_rdata_next[8] = ep_in_enable_enable_8_qs;
Tests: T2 T28 T29
9531 1/1 reg_rdata_next[9] = ep_in_enable_enable_9_qs;
Tests: T2 T28 T29
9532 1/1 reg_rdata_next[10] = ep_in_enable_enable_10_qs;
Tests: T2 T28 T29
9533 1/1 reg_rdata_next[11] = ep_in_enable_enable_11_qs;
Tests: T2 T28 T29
9534 end
9535
9536 addr_hit[7]: begin
9537 1/1 reg_rdata_next[10:0] = usbstat_frame_qs;
Tests: T2 T28 T30
9538 1/1 reg_rdata_next[11] = usbstat_host_lost_qs;
Tests: T2 T28 T30
9539 1/1 reg_rdata_next[14:12] = usbstat_link_state_qs;
Tests: T2 T28 T30
9540 1/1 reg_rdata_next[15] = usbstat_sense_qs;
Tests: T2 T28 T30
9541 1/1 reg_rdata_next[19:16] = usbstat_av_out_depth_qs;
Tests: T2 T28 T30
9542 1/1 reg_rdata_next[22:20] = usbstat_av_setup_depth_qs;
Tests: T2 T28 T30
9543 1/1 reg_rdata_next[23] = usbstat_av_out_full_qs;
Tests: T2 T28 T30
9544 1/1 reg_rdata_next[27:24] = usbstat_rx_depth_qs;
Tests: T2 T28 T30
9545 1/1 reg_rdata_next[30] = usbstat_av_setup_full_qs;
Tests: T2 T28 T30
9546 1/1 reg_rdata_next[31] = usbstat_rx_empty_qs;
Tests: T2 T28 T30
9547 end
9548
9549 addr_hit[8]: begin
9550 1/1 reg_rdata_next[4:0] = '0;
Tests: T2 T3 T28
9551 end
9552
9553 addr_hit[9]: begin
9554 1/1 reg_rdata_next[4:0] = '0;
Tests: T1 T2 T28
9555 end
9556
9557 addr_hit[10]: begin
9558 1/1 reg_rdata_next[4:0] = rxfifo_buffer_qs;
Tests: T1 T2 T28
9559 1/1 reg_rdata_next[14:8] = rxfifo_size_qs;
Tests: T1 T2 T28
9560 1/1 reg_rdata_next[19] = rxfifo_setup_qs;
Tests: T1 T2 T28
9561 1/1 reg_rdata_next[23:20] = rxfifo_ep_qs;
Tests: T1 T2 T28
9562 end
9563
9564 addr_hit[11]: begin
9565 1/1 reg_rdata_next[0] = rxenable_setup_setup_0_qs;
Tests: T1 T2 T28
9566 1/1 reg_rdata_next[1] = rxenable_setup_setup_1_qs;
Tests: T1 T2 T28
9567 1/1 reg_rdata_next[2] = rxenable_setup_setup_2_qs;
Tests: T1 T2 T28
9568 1/1 reg_rdata_next[3] = rxenable_setup_setup_3_qs;
Tests: T1 T2 T28
9569 1/1 reg_rdata_next[4] = rxenable_setup_setup_4_qs;
Tests: T1 T2 T28
9570 1/1 reg_rdata_next[5] = rxenable_setup_setup_5_qs;
Tests: T1 T2 T28
9571 1/1 reg_rdata_next[6] = rxenable_setup_setup_6_qs;
Tests: T1 T2 T28
9572 1/1 reg_rdata_next[7] = rxenable_setup_setup_7_qs;
Tests: T1 T2 T28
9573 1/1 reg_rdata_next[8] = rxenable_setup_setup_8_qs;
Tests: T1 T2 T28
9574 1/1 reg_rdata_next[9] = rxenable_setup_setup_9_qs;
Tests: T1 T2 T28
9575 1/1 reg_rdata_next[10] = rxenable_setup_setup_10_qs;
Tests: T1 T2 T28
9576 1/1 reg_rdata_next[11] = rxenable_setup_setup_11_qs;
Tests: T1 T2 T28
9577 end
9578
9579 addr_hit[12]: begin
9580 1/1 reg_rdata_next[0] = rxenable_out_out_0_qs;
Tests: T2 T3 T28
9581 1/1 reg_rdata_next[1] = rxenable_out_out_1_qs;
Tests: T2 T3 T28
9582 1/1 reg_rdata_next[2] = rxenable_out_out_2_qs;
Tests: T2 T3 T28
9583 1/1 reg_rdata_next[3] = rxenable_out_out_3_qs;
Tests: T2 T3 T28
9584 1/1 reg_rdata_next[4] = rxenable_out_out_4_qs;
Tests: T2 T3 T28
9585 1/1 reg_rdata_next[5] = rxenable_out_out_5_qs;
Tests: T2 T3 T28
9586 1/1 reg_rdata_next[6] = rxenable_out_out_6_qs;
Tests: T2 T3 T28
9587 1/1 reg_rdata_next[7] = rxenable_out_out_7_qs;
Tests: T2 T3 T28
9588 1/1 reg_rdata_next[8] = rxenable_out_out_8_qs;
Tests: T2 T3 T28
9589 1/1 reg_rdata_next[9] = rxenable_out_out_9_qs;
Tests: T2 T3 T28
9590 1/1 reg_rdata_next[10] = rxenable_out_out_10_qs;
Tests: T2 T3 T28
9591 1/1 reg_rdata_next[11] = rxenable_out_out_11_qs;
Tests: T2 T3 T28
9592 end
9593
9594 addr_hit[13]: begin
9595 1/1 reg_rdata_next[0] = set_nak_out_enable_0_qs;
Tests: T2 T28 T30
9596 1/1 reg_rdata_next[1] = set_nak_out_enable_1_qs;
Tests: T2 T28 T30
9597 1/1 reg_rdata_next[2] = set_nak_out_enable_2_qs;
Tests: T2 T28 T30
9598 1/1 reg_rdata_next[3] = set_nak_out_enable_3_qs;
Tests: T2 T28 T30
9599 1/1 reg_rdata_next[4] = set_nak_out_enable_4_qs;
Tests: T2 T28 T30
9600 1/1 reg_rdata_next[5] = set_nak_out_enable_5_qs;
Tests: T2 T28 T30
9601 1/1 reg_rdata_next[6] = set_nak_out_enable_6_qs;
Tests: T2 T28 T30
9602 1/1 reg_rdata_next[7] = set_nak_out_enable_7_qs;
Tests: T2 T28 T30
9603 1/1 reg_rdata_next[8] = set_nak_out_enable_8_qs;
Tests: T2 T28 T30
9604 1/1 reg_rdata_next[9] = set_nak_out_enable_9_qs;
Tests: T2 T28 T30
9605 1/1 reg_rdata_next[10] = set_nak_out_enable_10_qs;
Tests: T2 T28 T30
9606 1/1 reg_rdata_next[11] = set_nak_out_enable_11_qs;
Tests: T2 T28 T30
9607 end
9608
9609 addr_hit[14]: begin
9610 1/1 reg_rdata_next[0] = in_sent_sent_0_qs;
Tests: T2 T28 T30
9611 1/1 reg_rdata_next[1] = in_sent_sent_1_qs;
Tests: T2 T28 T30
9612 1/1 reg_rdata_next[2] = in_sent_sent_2_qs;
Tests: T2 T28 T30
9613 1/1 reg_rdata_next[3] = in_sent_sent_3_qs;
Tests: T2 T28 T30
9614 1/1 reg_rdata_next[4] = in_sent_sent_4_qs;
Tests: T2 T28 T30
9615 1/1 reg_rdata_next[5] = in_sent_sent_5_qs;
Tests: T2 T28 T30
9616 1/1 reg_rdata_next[6] = in_sent_sent_6_qs;
Tests: T2 T28 T30
9617 1/1 reg_rdata_next[7] = in_sent_sent_7_qs;
Tests: T2 T28 T30
9618 1/1 reg_rdata_next[8] = in_sent_sent_8_qs;
Tests: T2 T28 T30
9619 1/1 reg_rdata_next[9] = in_sent_sent_9_qs;
Tests: T2 T28 T30
9620 1/1 reg_rdata_next[10] = in_sent_sent_10_qs;
Tests: T2 T28 T30
9621 1/1 reg_rdata_next[11] = in_sent_sent_11_qs;
Tests: T2 T28 T30
9622 end
9623
9624 addr_hit[15]: begin
9625 1/1 reg_rdata_next[0] = out_stall_endpoint_0_qs;
Tests: T2 T28 T30
9626 1/1 reg_rdata_next[1] = out_stall_endpoint_1_qs;
Tests: T2 T28 T30
9627 1/1 reg_rdata_next[2] = out_stall_endpoint_2_qs;
Tests: T2 T28 T30
9628 1/1 reg_rdata_next[3] = out_stall_endpoint_3_qs;
Tests: T2 T28 T30
9629 1/1 reg_rdata_next[4] = out_stall_endpoint_4_qs;
Tests: T2 T28 T30
9630 1/1 reg_rdata_next[5] = out_stall_endpoint_5_qs;
Tests: T2 T28 T30
9631 1/1 reg_rdata_next[6] = out_stall_endpoint_6_qs;
Tests: T2 T28 T30
9632 1/1 reg_rdata_next[7] = out_stall_endpoint_7_qs;
Tests: T2 T28 T30
9633 1/1 reg_rdata_next[8] = out_stall_endpoint_8_qs;
Tests: T2 T28 T30
9634 1/1 reg_rdata_next[9] = out_stall_endpoint_9_qs;
Tests: T2 T28 T30
9635 1/1 reg_rdata_next[10] = out_stall_endpoint_10_qs;
Tests: T2 T28 T30
9636 1/1 reg_rdata_next[11] = out_stall_endpoint_11_qs;
Tests: T2 T28 T30
9637 end
9638
9639 addr_hit[16]: begin
9640 1/1 reg_rdata_next[0] = in_stall_endpoint_0_qs;
Tests: T2 T28 T30
9641 1/1 reg_rdata_next[1] = in_stall_endpoint_1_qs;
Tests: T2 T28 T30
9642 1/1 reg_rdata_next[2] = in_stall_endpoint_2_qs;
Tests: T2 T28 T30
9643 1/1 reg_rdata_next[3] = in_stall_endpoint_3_qs;
Tests: T2 T28 T30
9644 1/1 reg_rdata_next[4] = in_stall_endpoint_4_qs;
Tests: T2 T28 T30
9645 1/1 reg_rdata_next[5] = in_stall_endpoint_5_qs;
Tests: T2 T28 T30
9646 1/1 reg_rdata_next[6] = in_stall_endpoint_6_qs;
Tests: T2 T28 T30
9647 1/1 reg_rdata_next[7] = in_stall_endpoint_7_qs;
Tests: T2 T28 T30
9648 1/1 reg_rdata_next[8] = in_stall_endpoint_8_qs;
Tests: T2 T28 T30
9649 1/1 reg_rdata_next[9] = in_stall_endpoint_9_qs;
Tests: T2 T28 T30
9650 1/1 reg_rdata_next[10] = in_stall_endpoint_10_qs;
Tests: T2 T28 T30
9651 1/1 reg_rdata_next[11] = in_stall_endpoint_11_qs;
Tests: T2 T28 T30
9652 end
9653
9654 addr_hit[17]: begin
9655 1/1 reg_rdata_next[4:0] = configin_0_buffer_0_qs;
Tests: T2 T28 T30
9656 1/1 reg_rdata_next[14:8] = configin_0_size_0_qs;
Tests: T2 T28 T30
9657 1/1 reg_rdata_next[29] = configin_0_sending_0_qs;
Tests: T2 T28 T30
9658 1/1 reg_rdata_next[30] = configin_0_pend_0_qs;
Tests: T2 T28 T30
9659 1/1 reg_rdata_next[31] = configin_0_rdy_0_qs;
Tests: T2 T28 T30
9660 end
9661
9662 addr_hit[18]: begin
9663 1/1 reg_rdata_next[4:0] = configin_1_buffer_1_qs;
Tests: T2 T28 T30
9664 1/1 reg_rdata_next[14:8] = configin_1_size_1_qs;
Tests: T2 T28 T30
9665 1/1 reg_rdata_next[29] = configin_1_sending_1_qs;
Tests: T2 T28 T30
9666 1/1 reg_rdata_next[30] = configin_1_pend_1_qs;
Tests: T2 T28 T30
9667 1/1 reg_rdata_next[31] = configin_1_rdy_1_qs;
Tests: T2 T28 T30
9668 end
9669
9670 addr_hit[19]: begin
9671 1/1 reg_rdata_next[4:0] = configin_2_buffer_2_qs;
Tests: T2 T28 T30
9672 1/1 reg_rdata_next[14:8] = configin_2_size_2_qs;
Tests: T2 T28 T30
9673 1/1 reg_rdata_next[29] = configin_2_sending_2_qs;
Tests: T2 T28 T30
9674 1/1 reg_rdata_next[30] = configin_2_pend_2_qs;
Tests: T2 T28 T30
9675 1/1 reg_rdata_next[31] = configin_2_rdy_2_qs;
Tests: T2 T28 T30
9676 end
9677
9678 addr_hit[20]: begin
9679 1/1 reg_rdata_next[4:0] = configin_3_buffer_3_qs;
Tests: T2 T28 T30
9680 1/1 reg_rdata_next[14:8] = configin_3_size_3_qs;
Tests: T2 T28 T30
9681 1/1 reg_rdata_next[29] = configin_3_sending_3_qs;
Tests: T2 T28 T30
9682 1/1 reg_rdata_next[30] = configin_3_pend_3_qs;
Tests: T2 T28 T30
9683 1/1 reg_rdata_next[31] = configin_3_rdy_3_qs;
Tests: T2 T28 T30
9684 end
9685
9686 addr_hit[21]: begin
9687 1/1 reg_rdata_next[4:0] = configin_4_buffer_4_qs;
Tests: T2 T28 T30
9688 1/1 reg_rdata_next[14:8] = configin_4_size_4_qs;
Tests: T2 T28 T30
9689 1/1 reg_rdata_next[29] = configin_4_sending_4_qs;
Tests: T2 T28 T30
9690 1/1 reg_rdata_next[30] = configin_4_pend_4_qs;
Tests: T2 T28 T30
9691 1/1 reg_rdata_next[31] = configin_4_rdy_4_qs;
Tests: T2 T28 T30
9692 end
9693
9694 addr_hit[22]: begin
9695 1/1 reg_rdata_next[4:0] = configin_5_buffer_5_qs;
Tests: T2 T28 T30
9696 1/1 reg_rdata_next[14:8] = configin_5_size_5_qs;
Tests: T2 T28 T30
9697 1/1 reg_rdata_next[29] = configin_5_sending_5_qs;
Tests: T2 T28 T30
9698 1/1 reg_rdata_next[30] = configin_5_pend_5_qs;
Tests: T2 T28 T30
9699 1/1 reg_rdata_next[31] = configin_5_rdy_5_qs;
Tests: T2 T28 T30
9700 end
9701
9702 addr_hit[23]: begin
9703 1/1 reg_rdata_next[4:0] = configin_6_buffer_6_qs;
Tests: T2 T28 T29
9704 1/1 reg_rdata_next[14:8] = configin_6_size_6_qs;
Tests: T2 T28 T29
9705 1/1 reg_rdata_next[29] = configin_6_sending_6_qs;
Tests: T2 T28 T29
9706 1/1 reg_rdata_next[30] = configin_6_pend_6_qs;
Tests: T2 T28 T29
9707 1/1 reg_rdata_next[31] = configin_6_rdy_6_qs;
Tests: T2 T28 T29
9708 end
9709
9710 addr_hit[24]: begin
9711 1/1 reg_rdata_next[4:0] = configin_7_buffer_7_qs;
Tests: T2 T28 T30
9712 1/1 reg_rdata_next[14:8] = configin_7_size_7_qs;
Tests: T2 T28 T30
9713 1/1 reg_rdata_next[29] = configin_7_sending_7_qs;
Tests: T2 T28 T30
9714 1/1 reg_rdata_next[30] = configin_7_pend_7_qs;
Tests: T2 T28 T30
9715 1/1 reg_rdata_next[31] = configin_7_rdy_7_qs;
Tests: T2 T28 T30
9716 end
9717
9718 addr_hit[25]: begin
9719 1/1 reg_rdata_next[4:0] = configin_8_buffer_8_qs;
Tests: T2 T28 T30
9720 1/1 reg_rdata_next[14:8] = configin_8_size_8_qs;
Tests: T2 T28 T30
9721 1/1 reg_rdata_next[29] = configin_8_sending_8_qs;
Tests: T2 T28 T30
9722 1/1 reg_rdata_next[30] = configin_8_pend_8_qs;
Tests: T2 T28 T30
9723 1/1 reg_rdata_next[31] = configin_8_rdy_8_qs;
Tests: T2 T28 T30
9724 end
9725
9726 addr_hit[26]: begin
9727 1/1 reg_rdata_next[4:0] = configin_9_buffer_9_qs;
Tests: T2 T28 T30
9728 1/1 reg_rdata_next[14:8] = configin_9_size_9_qs;
Tests: T2 T28 T30
9729 1/1 reg_rdata_next[29] = configin_9_sending_9_qs;
Tests: T2 T28 T30
9730 1/1 reg_rdata_next[30] = configin_9_pend_9_qs;
Tests: T2 T28 T30
9731 1/1 reg_rdata_next[31] = configin_9_rdy_9_qs;
Tests: T2 T28 T30
9732 end
9733
9734 addr_hit[27]: begin
9735 1/1 reg_rdata_next[4:0] = configin_10_buffer_10_qs;
Tests: T2 T28 T29
9736 1/1 reg_rdata_next[14:8] = configin_10_size_10_qs;
Tests: T2 T28 T29
9737 1/1 reg_rdata_next[29] = configin_10_sending_10_qs;
Tests: T2 T28 T29
9738 1/1 reg_rdata_next[30] = configin_10_pend_10_qs;
Tests: T2 T28 T29
9739 1/1 reg_rdata_next[31] = configin_10_rdy_10_qs;
Tests: T2 T28 T29
9740 end
9741
9742 addr_hit[28]: begin
9743 1/1 reg_rdata_next[4:0] = configin_11_buffer_11_qs;
Tests: T2 T28 T30
9744 1/1 reg_rdata_next[14:8] = configin_11_size_11_qs;
Tests: T2 T28 T30
9745 1/1 reg_rdata_next[29] = configin_11_sending_11_qs;
Tests: T2 T28 T30
9746 1/1 reg_rdata_next[30] = configin_11_pend_11_qs;
Tests: T2 T28 T30
9747 1/1 reg_rdata_next[31] = configin_11_rdy_11_qs;
Tests: T2 T28 T30
9748 end
9749
9750 addr_hit[29]: begin
9751 1/1 reg_rdata_next[0] = out_iso_iso_0_qs;
Tests: T2 T28 T30
9752 1/1 reg_rdata_next[1] = out_iso_iso_1_qs;
Tests: T2 T28 T30
9753 1/1 reg_rdata_next[2] = out_iso_iso_2_qs;
Tests: T2 T28 T30
9754 1/1 reg_rdata_next[3] = out_iso_iso_3_qs;
Tests: T2 T28 T30
9755 1/1 reg_rdata_next[4] = out_iso_iso_4_qs;
Tests: T2 T28 T30
9756 1/1 reg_rdata_next[5] = out_iso_iso_5_qs;
Tests: T2 T28 T30
9757 1/1 reg_rdata_next[6] = out_iso_iso_6_qs;
Tests: T2 T28 T30
9758 1/1 reg_rdata_next[7] = out_iso_iso_7_qs;
Tests: T2 T28 T30
9759 1/1 reg_rdata_next[8] = out_iso_iso_8_qs;
Tests: T2 T28 T30
9760 1/1 reg_rdata_next[9] = out_iso_iso_9_qs;
Tests: T2 T28 T30
9761 1/1 reg_rdata_next[10] = out_iso_iso_10_qs;
Tests: T2 T28 T30
9762 1/1 reg_rdata_next[11] = out_iso_iso_11_qs;
Tests: T2 T28 T30
9763 end
9764
9765 addr_hit[30]: begin
9766 1/1 reg_rdata_next[0] = in_iso_iso_0_qs;
Tests: T2 T28 T30
9767 1/1 reg_rdata_next[1] = in_iso_iso_1_qs;
Tests: T2 T28 T30
9768 1/1 reg_rdata_next[2] = in_iso_iso_2_qs;
Tests: T2 T28 T30
9769 1/1 reg_rdata_next[3] = in_iso_iso_3_qs;
Tests: T2 T28 T30
9770 1/1 reg_rdata_next[4] = in_iso_iso_4_qs;
Tests: T2 T28 T30
9771 1/1 reg_rdata_next[5] = in_iso_iso_5_qs;
Tests: T2 T28 T30
9772 1/1 reg_rdata_next[6] = in_iso_iso_6_qs;
Tests: T2 T28 T30
9773 1/1 reg_rdata_next[7] = in_iso_iso_7_qs;
Tests: T2 T28 T30
9774 1/1 reg_rdata_next[8] = in_iso_iso_8_qs;
Tests: T2 T28 T30
9775 1/1 reg_rdata_next[9] = in_iso_iso_9_qs;
Tests: T2 T28 T30
9776 1/1 reg_rdata_next[10] = in_iso_iso_10_qs;
Tests: T2 T28 T30
9777 1/1 reg_rdata_next[11] = in_iso_iso_11_qs;
Tests: T2 T28 T30
9778 end
9779
9780 addr_hit[31]: begin
9781 1/1 reg_rdata_next[11:0] = out_data_toggle_status_qs;
Tests: T2 T28 T29
9782 1/1 reg_rdata_next[27:16] = out_data_toggle_mask_qs;
Tests: T2 T28 T29
9783 end
9784
9785 addr_hit[32]: begin
9786 1/1 reg_rdata_next[11:0] = in_data_toggle_status_qs;
Tests: T2 T28 T29
9787 1/1 reg_rdata_next[27:16] = in_data_toggle_mask_qs;
Tests: T2 T28 T29
9788 end
9789
9790 addr_hit[33]: begin
9791 1/1 reg_rdata_next[0] = phy_pins_sense_rx_dp_i_qs;
Tests: T2 T28 T30
9792 1/1 reg_rdata_next[1] = phy_pins_sense_rx_dn_i_qs;
Tests: T2 T28 T30
9793 1/1 reg_rdata_next[2] = phy_pins_sense_rx_d_i_qs;
Tests: T2 T28 T30
9794 1/1 reg_rdata_next[8] = phy_pins_sense_tx_dp_o_qs;
Tests: T2 T28 T30
9795 1/1 reg_rdata_next[9] = phy_pins_sense_tx_dn_o_qs;
Tests: T2 T28 T30
9796 1/1 reg_rdata_next[10] = phy_pins_sense_tx_d_o_qs;
Tests: T2 T28 T30
9797 1/1 reg_rdata_next[11] = phy_pins_sense_tx_se0_o_qs;
Tests: T2 T28 T30
9798 1/1 reg_rdata_next[12] = phy_pins_sense_tx_oe_o_qs;
Tests: T2 T28 T30
9799 1/1 reg_rdata_next[16] = phy_pins_sense_pwr_sense_qs;
Tests: T2 T28 T30
9800 end
9801
9802 addr_hit[34]: begin
9803 1/1 reg_rdata_next[0] = phy_pins_drive_dp_o_qs;
Tests: T2 T28 T30
9804 1/1 reg_rdata_next[1] = phy_pins_drive_dn_o_qs;
Tests: T2 T28 T30
9805 1/1 reg_rdata_next[2] = phy_pins_drive_d_o_qs;
Tests: T2 T28 T30
9806 1/1 reg_rdata_next[3] = phy_pins_drive_se0_o_qs;
Tests: T2 T28 T30
9807 1/1 reg_rdata_next[4] = phy_pins_drive_oe_o_qs;
Tests: T2 T28 T30
9808 1/1 reg_rdata_next[5] = phy_pins_drive_rx_enable_o_qs;
Tests: T2 T28 T30
9809 1/1 reg_rdata_next[6] = phy_pins_drive_dp_pullup_en_o_qs;
Tests: T2 T28 T30
9810 1/1 reg_rdata_next[7] = phy_pins_drive_dn_pullup_en_o_qs;
Tests: T2 T28 T30
9811 1/1 reg_rdata_next[16] = phy_pins_drive_en_qs;
Tests: T2 T28 T30
9812 end
9813
9814 addr_hit[35]: begin
9815 1/1 reg_rdata_next[0] = phy_config_use_diff_rcvr_qs;
Tests: T1 T2 T3
9816 1/1 reg_rdata_next[1] = phy_config_tx_use_d_se0_qs;
Tests: T1 T2 T3
9817 1/1 reg_rdata_next[2] = phy_config_eop_single_bit_qs;
Tests: T1 T2 T3
9818 1/1 reg_rdata_next[5] = phy_config_pinflip_qs;
Tests: T1 T2 T3
9819 1/1 reg_rdata_next[6] = phy_config_usb_ref_disable_qs;
Tests: T1 T2 T3
9820 1/1 reg_rdata_next[7] = phy_config_tx_osc_test_mode_qs;
Tests: T1 T2 T3
9821 end
9822
9823 addr_hit[36]: begin
9824 1/1 reg_rdata_next = DW'(wake_control_qs);
Tests: T2 T28 T30
9825 end
9826 addr_hit[37]: begin
9827 1/1 reg_rdata_next = DW'(wake_events_qs);
Tests: T2 T28 T30
9828 end
9829 addr_hit[38]: begin
9830 1/1 reg_rdata_next[0] = '0;
Tests: T2 T28 T30
9831 1/1 reg_rdata_next[1] = '0;
Tests: T2 T28 T30
9832 1/1 reg_rdata_next[2] = '0;
Tests: T2 T28 T30
9833 end
9834
9835 addr_hit[39]: begin
9836 1/1 reg_rdata_next[7:0] = count_out_count_qs;
Tests: T2 T28 T30
9837 1/1 reg_rdata_next[12] = count_out_datatog_out_qs;
Tests: T2 T28 T30
9838 1/1 reg_rdata_next[13] = count_out_drop_rx_qs;
Tests: T2 T28 T30
9839 1/1 reg_rdata_next[14] = count_out_drop_avout_qs;
Tests: T2 T28 T30
9840 1/1 reg_rdata_next[15] = count_out_ign_avsetup_qs;
Tests: T2 T28 T30
9841 1/1 reg_rdata_next[27:16] = count_out_endpoints_qs;
Tests: T2 T28 T30
9842 1/1 reg_rdata_next[31] = '0;
Tests: T2 T28 T30
9843 end
9844
9845 addr_hit[40]: begin
9846 1/1 reg_rdata_next[7:0] = count_in_count_qs;
Tests: T2 T3 T28
9847 1/1 reg_rdata_next[13] = count_in_nodata_qs;
Tests: T2 T3 T28
9848 1/1 reg_rdata_next[14] = count_in_nak_qs;
Tests: T2 T3 T28
9849 1/1 reg_rdata_next[15] = count_in_timeout_qs;
Tests: T2 T3 T28
9850 1/1 reg_rdata_next[27:16] = count_in_endpoints_qs;
Tests: T2 T3 T28
9851 1/1 reg_rdata_next[31] = '0;
Tests: T2 T3 T28
9852 end
9853
9854 addr_hit[41]: begin
9855 1/1 reg_rdata_next[7:0] = count_nodata_in_count_qs;
Tests: T2 T28 T30
9856 1/1 reg_rdata_next[27:16] = count_nodata_in_endpoints_qs;
Tests: T2 T28 T30
9857 1/1 reg_rdata_next[31] = '0;
Tests: T2 T28 T30
9858 end
9859
9860 addr_hit[42]: begin
9861 1/1 reg_rdata_next[7:0] = count_errors_count_qs;
Tests: T2 T28 T30
9862 1/1 reg_rdata_next[27] = count_errors_pid_invalid_qs;
Tests: T2 T28 T30
9863 1/1 reg_rdata_next[28] = count_errors_bitstuff_qs;
Tests: T2 T28 T30
9864 1/1 reg_rdata_next[29] = count_errors_crc16_qs;
Tests: T2 T28 T30
9865 1/1 reg_rdata_next[30] = count_errors_crc5_qs;
Tests: T2 T28 T30
9866 1/1 reg_rdata_next[31] = '0;
Tests: T2 T28 T30
9867 end
9868
9869 default: begin
9870 reg_rdata_next = '1;
9871 end
9872 endcase
9873 end
9874
9875 // shadow busy
9876 logic shadow_busy;
9877 assign shadow_busy = 1'b0;
9878
9879 // register busy
9880 logic reg_busy_sel;
9881 1/1 assign reg_busy = reg_busy_sel | shadow_busy;
Tests: T2 T28 T30
9882 always_comb begin
9883 1/1 reg_busy_sel = '0;
Tests: T1 T2 T3
9884 1/1 unique case (1'b1)
Tests: T1 T2 T3
9885 addr_hit[36]: begin
9886 1/1 reg_busy_sel = wake_control_busy;
Tests: T2 T28 T30
9887 end
9888 addr_hit[37]: begin
9889 1/1 reg_busy_sel = wake_events_busy;
Tests: T2 T28 T30
9890 end
9891 default: begin
9892 reg_busy_sel = '0;
9893 end
9894 endcase
9895 end
9896
9897
9898 // Unused signal tieoff
9899
9900 // wdata / byte enable are not always fully used
9901 // add a blanket unused statement to handle lint waivers
9902 logic unused_wdata;
9903 logic unused_be;
9904 1/1 assign unused_wdata = ^reg_wdata;
Tests: T1 T2 T3
9905 1/1 assign unused_be = ^reg_be;
Tests: T1 T2 T3