Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	171371	1			T1	4		T2	5		T3	3
all_values[1]	171371	1			T1	4		T2	5		T3	3
all_values[2]	171371	1			T1	4		T2	5		T3	3
all_values[3]	171371	1			T1	4		T2	5		T3	3
all_values[4]	171371	1			T1	4		T2	5		T3	3
all_values[5]	171371	1			T1	4		T2	5		T3	3
all_values[6]	171371	1			T1	4		T2	5		T3	3
all_values[7]	171371	1			T1	4		T2	5		T3	3
all_values[8]	171371	1			T1	4		T2	5		T3	3
all_values[9]	171371	1			T1	4		T2	5		T3	3
all_values[10]	171371	1			T1	4		T2	5		T3	3
all_values[11]	171371	1			T1	4		T2	5		T3	3
all_values[12]	171371	1			T1	4		T2	5		T3	3
all_values[13]	171371	1			T1	4		T2	5		T3	3
all_values[14]	171371	1			T1	4		T2	5		T3	3
all_values[15]	171371	1			T1	4		T2	5		T3	3
all_values[16]	171371	1			T1	4		T2	5		T3	3
all_values[17]	171371	1			T1	4		T2	5		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5474203

1

T1

128

T2

158

T3

94

auto[1]

9669

1

T2

2

T3

2

T37

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4699912

1

T1

110

T2

146

T3

85

auto[1]

783960

1

T1

18

T2

14

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142879	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	25195	1			T1	1		T2	2		T31	1
all_values[0]	auto[1]	auto[0]	3186	1			T43	3		T44	3		T45	3
all_values[0]	auto[1]	auto[1]	111	1			T313	1		T314	1		T315	1
all_values[1]	auto[0]	auto[0]	166942	1			T1	4		T2	5		T3	3
all_values[1]	auto[0]	auto[1]	3035	1			T17	2		T18	2		T32	1
all_values[1]	auto[1]	auto[0]	518	1			T7	1		T22	2		T35	2
all_values[1]	auto[1]	auto[1]	876	1			T7	1		T22	12		T35	1
all_values[2]	auto[0]	auto[0]	4229	1			T1	1		T2	4		T3	1
all_values[2]	auto[0]	auto[1]	166878	1			T1	3		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	131	1			T19	1		T59	1		T60	1
all_values[2]	auto[1]	auto[1]	133	1			T19	1		T59	1		T60	1
all_values[3]	auto[0]	auto[0]	169487	1			T1	4		T2	5		T3	3
all_values[3]	auto[0]	auto[1]	311	1			T41	1		T34	1		T61	1
all_values[3]	auto[1]	auto[0]	1495	1			T41	1429		T194	2		T302	1
all_values[3]	auto[1]	auto[1]	78	1			T41	1		T196	2		T194	1
all_values[4]	auto[0]	auto[0]	4182	1			T1	1		T2	4		T3	1
all_values[4]	auto[0]	auto[1]	167008	1			T1	3		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	96	1			T42	1		T196	3		T195	1
all_values[4]	auto[1]	auto[1]	85	1			T42	1		T196	1		T194	2
all_values[5]	auto[0]	auto[0]	170859	1			T1	4		T2	5		T3	3
all_values[5]	auto[0]	auto[1]	343	1			T7	1		T8	1		T9	1
all_values[5]	auto[1]	auto[0]	97	1			T195	2		T302	1		T278	3
all_values[5]	auto[1]	auto[1]	72	1			T194	3		T195	2		T198	3
all_values[6]	auto[0]	auto[0]	170924	1			T1	4		T2	5		T3	3
all_values[6]	auto[0]	auto[1]	237	1			T8	1		T9	1		T62	1
all_values[6]	auto[1]	auto[0]	99	1			T196	3		T194	1		T195	4
all_values[6]	auto[1]	auto[1]	111	1			T63	1		T64	1		T65	1
all_values[7]	auto[0]	auto[0]	115016	1			T3	3		T37	5		T7	2
all_values[7]	auto[0]	auto[1]	56185	1			T1	4		T2	3		T37	2
all_values[7]	auto[1]	auto[0]	110	1			T2	1		T46	1		T196	1
all_values[7]	auto[1]	auto[1]	60	1			T2	1		T46	1		T194	1
all_values[8]	auto[0]	auto[0]	170632	1			T1	4		T2	5		T3	3
all_values[8]	auto[0]	auto[1]	61	1			T194	2		T195	1		T302	1
all_values[8]	auto[1]	auto[0]	603	1			T50	10		T48	10		T51	10
all_values[8]	auto[1]	auto[1]	75	1			T48	1		T51	1		T53	1
all_values[9]	auto[0]	auto[0]	171117	1			T1	4		T2	5		T3	3
all_values[9]	auto[0]	auto[1]	63	1			T194	4		T198	1		T303	3
all_values[9]	auto[1]	auto[0]	115	1			T37	3		T57	3		T58	3
all_values[9]	auto[1]	auto[1]	76	1			T37	2		T57	2		T58	2
all_values[10]	auto[0]	auto[0]	170838	1			T1	4		T2	5		T3	3
all_values[10]	auto[0]	auto[1]	373	1			T18	1		T30	1		T34	1
all_values[10]	auto[1]	auto[0]	94	1			T196	5		T194	3		T195	2
all_values[10]	auto[1]	auto[1]	66	1			T194	1		T195	2		T302	2
all_values[11]	auto[0]	auto[0]	170408	1			T1	4		T2	5		T3	2
all_values[11]	auto[0]	auto[1]	714	1			T3	1		T31	4		T66	4
all_values[11]	auto[1]	auto[0]	144	1			T69	1		T70	1		T71	1
all_values[11]	auto[1]	auto[1]	105	1			T69	1		T70	1		T71	1
all_values[12]	auto[0]	auto[0]	170970	1			T1	4		T2	5		T3	3
all_values[12]	auto[0]	auto[1]	210	1			T74	1		T76	1		T77	1
all_values[12]	auto[1]	auto[0]	106	1			T72	2		T73	2		T75	2
all_values[12]	auto[1]	auto[1]	85	1			T72	1		T73	1		T75	1
all_values[13]	auto[0]	auto[0]	171047	1			T1	4		T2	5		T3	1
all_values[13]	auto[0]	auto[1]	60	1			T74	1		T76	1		T77	1
all_values[13]	auto[1]	auto[0]	149	1			T3	1		T78	1		T79	1
all_values[13]	auto[1]	auto[1]	115	1			T3	1		T78	1		T79	1
all_values[14]	auto[0]	auto[0]	35353	1			T1	4		T2	5		T3	3
all_values[14]	auto[0]	auto[1]	135854	1			T7	2		T8	2		T19	1
all_values[14]	auto[1]	auto[0]	91	1			T196	1		T302	1		T278	3
all_values[14]	auto[1]	auto[1]	73	1			T194	1		T195	1		T198	3
all_values[15]	auto[0]	auto[0]	4253	1			T1	1		T2	4		T3	1
all_values[15]	auto[0]	auto[1]	166959	1			T1	3		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	90	1			T194	1		T195	1		T302	1
all_values[15]	auto[1]	auto[1]	69	1			T194	2		T302	4		T198	1
all_values[16]	auto[0]	auto[0]	170407	1			T1	4		T2	5		T3	3
all_values[16]	auto[0]	auto[1]	775	1			T18	1		T61	1		T68	1
all_values[16]	auto[1]	auto[0]	111	1			T31	4		T66	4		T67	4
all_values[16]	auto[1]	auto[1]	78	1			T31	4		T66	4		T67	4
all_values[17]	auto[0]	auto[0]	113829	1			T7	2		T8	2		T20	2
all_values[17]	auto[0]	auto[1]	57376	1			T1	4		T2	5		T3	3
all_values[17]	auto[1]	auto[0]	111	1			T54	1		T55	1		T56	1
all_values[17]	auto[1]	auto[1]	55	1			T54	1		T55	1		T56	1