Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1954	1			T7	2		T61	8		T98	4
range_16_to_126	151941	1			T17	19		T18	32		T20	25
fifteen	686	1			T61	9		T493	1		T98	1
range_2_to_14	19905	1			T1	1		T2	1		T20	1
seven	2471	1			T61	6		T363	1		T213	1
one	450	1			T61	5		T98	1		T105	5
zero	793	1			T3	1		T61	4		T83	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

11877

1

T18

2

T20

2

T22

2

three

12501

1

T18

2

T22

2

T24

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	141	1			T335	1		T374	1		T494	1
range_127	three	102	1			T495	1		T375	1		T496	2
range_16_to_126	seven	10280	1			T18	2		T20	2		T22	2
range_16_to_126	three	10934	1			T18	2		T22	2		T24	2
fifteen	seven	44	1			T61	1		T105	1		T387	1
fifteen	three	159	1			T497	113		T374	1		T375	1
range_2_to_14	seven	1299	1			T36	2		T61	5		T98	2
range_2_to_14	three	1260	1			T61	3		T147	13		T98	4
seven	seven	152	1			T213	1		T242	31		T376	2
seven	three	166	1			T242	36		T105	1		T374	1
one	seven	74	1			T374	3		T498	1		T375	1
one	three	20	1			T374	1		T495	1		T375	2
zero	seven	39	1			T336	1		T291	3		T369	1
zero	three	26	1			T291	3		T495	1		T375	1