Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109253

1

T1

1

T2

1

T3

1

auto[1]

45288

1

T7

1

T17

11

T18

16

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29638	1			T41	5		T106	2		T80	1
max_len_m1	796	1			T18	1		T41	2		T152	1
max_len_m2	843	1			T18	3		T41	2		T4	2
max_len_m3	781	1			T41	1		T4	2		T45	1
five	1161	1			T22	2		T41	6		T4	2
four	1062	1			T31	1		T146	2		T85	8
three	771	1			T41	2		T5	1		T47	1
one	777	1			T41	2		T66	1		T5	3
zero	11304	1			T3	1		T17	11		T18	11

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	24192	1			T41	5		T106	1		T80	1
max_len	auto[1]	5446	1			T106	1		T5	1		T6	2
max_len_m1	auto[0]	538	1			T18	1		T41	2		T152	1
max_len_m1	auto[1]	258	1			T6	4		T151	1		T150	2
max_len_m2	auto[0]	580	1			T18	2		T41	2		T4	1
max_len_m2	auto[1]	263	1			T18	1		T4	1		T6	1
max_len_m3	auto[0]	532	1			T41	1		T4	1		T45	1
max_len_m3	auto[1]	249	1			T4	1		T6	2		T151	1
five	auto[0]	597	1			T22	1		T41	6		T4	1
five	auto[1]	564	1			T22	1		T4	1		T5	1
four	auto[0]	555	1			T31	1		T146	1		T85	5
four	auto[1]	507	1			T146	1		T85	3		T150	1
three	auto[0]	369	1			T41	2		T5	1		T47	1
three	auto[1]	402	1			T85	3		T242	5		T249	9
one	auto[0]	342	1			T41	2		T66	1		T5	3
one	auto[1]	435	1			T85	2		T242	4		T249	9
zero	auto[0]	533	1			T3	1		T18	1		T41	2
zero	auto[1]	10771	1			T17	11		T18	10		T30	8