Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69158

1

T1

1

T2

1

T7

1

auto[1]

77150

1

T7

2

T17

22

T18

26

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	11809	1			T18	8		T22	3		T61	27
endpoints[0x1]	11718	1			T22	3		T31	11		T61	47
endpoints[0x2]	11389	1			T18	5		T22	3		T4	27
endpoints[0x3]	11432	1			T18	3		T22	3		T66	11
endpoints[0x4]	13525	1			T2	1		T18	6		T22	3
endpoints[0x5]	10977	1			T7	3		T17	30		T18	4
endpoints[0x6]	11483	1			T18	4		T22	3		T61	57
endpoints[0x7]	10367	1			T18	3		T22	3		T36	3
endpoints[0x8]	14958	1			T18	1		T22	3		T30	11
endpoints[0x9]	12874	1			T1	1		T18	2		T22	3
endpoints[0xa]	13123	1			T18	4		T22	3		T34	18
endpoints[0xb]	12653	1			T18	2		T22	3		T35	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	161	1			T18	5		T101	2		T103	7
ack	38010	1			T7	1		T17	11		T18	5
data1	50424	1			T17	5		T18	13		T30	6
data0	57651	1			T1	1		T2	1		T7	2

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	14	1			T18	1		T291	1		T292	1
nak	auto[1]	endpoints[0x1]	11	1			T103	1		T293	3		T294	2
nak	auto[1]	endpoints[0x2]	13	1			T18	1		T101	1		T103	1
nak	auto[1]	endpoints[0x3]	13	1			T18	1		T103	2		T295	2
nak	auto[1]	endpoints[0x4]	15	1			T18	1		T103	1		T296	1
nak	auto[1]	endpoints[0x5]	9	1			T103	1		T291	1		T294	1
nak	auto[1]	endpoints[0x6]	15	1			T101	1		T291	1		T292	1
nak	auto[1]	endpoints[0x7]	13	1			T18	1		T295	1		T297	1
nak	auto[1]	endpoints[0x8]	11	1			T295	1		T298	1		T299	1
nak	auto[1]	endpoints[0x9]	18	1			T295	1		T291	1		T293	1
nak	auto[1]	endpoints[0xa]	17	1			T103	1		T291	1		T300	2
nak	auto[1]	endpoints[0xb]	12	1			T297	1		T301	1		T298	1
ack	auto[1]	endpoints[0x0]	3708	1			T18	2		T22	1		T4	9
ack	auto[1]	endpoints[0x1]	3005	1			T22	1		T61	13		T4	9
ack	auto[1]	endpoints[0x2]	2940	1			T18	1		T22	1		T4	9
ack	auto[1]	endpoints[0x3]	2928	1			T22	1		T61	11		T144	1
ack	auto[1]	endpoints[0x4]	3047	1			T22	1		T5	6		T146	5
ack	auto[1]	endpoints[0x5]	3151	1			T7	1		T17	11		T18	1
ack	auto[1]	endpoints[0x6]	3560	1			T22	1		T61	15		T5	6
ack	auto[1]	endpoints[0x7]	2866	1			T22	1		T43	1		T6	8
ack	auto[1]	endpoints[0x8]	3501	1			T22	1		T30	3		T61	19
ack	auto[1]	endpoints[0x9]	3153	1			T22	1		T61	10		T5	6
ack	auto[1]	endpoints[0xa]	3073	1			T22	1		T34	4		T61	13
ack	auto[1]	endpoints[0xb]	3078	1			T18	1		T22	1		T35	1
data1	auto[0]	endpoints[0x0]	1705	1			T61	15		T4	3		T5	3
data1	auto[0]	endpoints[0x1]	2412	1			T31	5		T4	4		T67	5
data1	auto[0]	endpoints[0x2]	2299	1			T18	1		T4	4		T5	2
data1	auto[0]	endpoints[0x3]	2336	1			T66	5		T61	7		T4	3
data1	auto[0]	endpoints[0x4]	3230	1			T18	1		T5	1		T50	3
data1	auto[0]	endpoints[0x5]	1920	1			T17	2		T18	1		T5	2
data1	auto[0]	endpoints[0x6]	1635	1			T18	2		T61	18		T5	2
data1	auto[0]	endpoints[0x7]	1859	1			T61	11		T5	3		T43	1
data1	auto[0]	endpoints[0x8]	3429	1			T4	3		T6	4		T146	2
data1	auto[0]	endpoints[0x9]	2779	1			T61	13		T5	1		T44	1
data1	auto[0]	endpoints[0xa]	3009	1			T18	1		T4	4		T152	1
data1	auto[0]	endpoints[0xb]	2817	1			T6	1		T85	16		T153	1
data1	auto[1]	endpoints[0x0]	2032	1			T18	2		T4	5		T5	3
data1	auto[1]	endpoints[0x1]	1634	1			T61	8		T4	4		T45	1
data1	auto[1]	endpoints[0x2]	1611	1			T4	4		T5	4		T85	13
data1	auto[1]	endpoints[0x3]	1611	1			T18	1		T61	7		T4	6
data1	auto[1]	endpoints[0x4]	1690	1			T18	1		T5	4		T146	2
data1	auto[1]	endpoints[0x5]	1707	1			T17	3		T5	4		T149	1
data1	auto[1]	endpoints[0x6]	2023	1			T18	1		T61	10		T5	4
data1	auto[1]	endpoints[0x7]	1568	1			T18	1		T43	1		T6	4
data1	auto[1]	endpoints[0x8]	1994	1			T30	6		T61	12		T4	5
data1	auto[1]	endpoints[0x9]	1749	1			T61	8		T5	5		T44	1
data1	auto[1]	endpoints[0xa]	1681	1			T34	5		T61	8		T4	4
data1	auto[1]	endpoints[0xb]	1694	1			T18	1		T6	6		T85	15
data0	auto[0]	endpoints[0x0]	2571	1			T18	1		T22	1		T61	12
data0	auto[0]	endpoints[0x1]	3223	1			T22	1		T31	6		T61	21
data0	auto[0]	endpoints[0x2]	3121	1			T22	1		T4	5		T5	4
data0	auto[0]	endpoints[0x3]	3146	1			T22	1		T66	6		T61	14
data0	auto[0]	endpoints[0x4]	4075	1			T2	1		T18	2		T22	1
data0	auto[0]	endpoints[0x5]	2674	1			T7	1		T17	6		T18	1
data0	auto[0]	endpoints[0x6]	2644	1			T18	1		T22	1		T61	9
data0	auto[0]	endpoints[0x7]	2697	1			T22	1		T36	1		T61	13
data0	auto[0]	endpoints[0x8]	4404	1			T18	1		T22	1		T4	6
data0	auto[0]	endpoints[0x9]	3688	1			T1	1		T18	1		T22	1
data0	auto[0]	endpoints[0xa]	3881	1			T18	3		T22	1		T80	1
data0	auto[0]	endpoints[0xb]	3592	1			T22	1		T35	1		T106	1
data0	auto[1]	endpoints[0x0]	1776	1			T18	2		T22	1		T4	4
data0	auto[1]	endpoints[0x1]	1428	1			T22	1		T61	5		T4	5
data0	auto[1]	endpoints[0x2]	1396	1			T18	2		T22	1		T4	5
data0	auto[1]	endpoints[0x3]	1394	1			T18	1		T22	1		T61	4
data0	auto[1]	endpoints[0x4]	1466	1			T18	1		T22	1		T5	2
data0	auto[1]	endpoints[0x5]	1510	1			T7	1		T17	8		T18	1
data0	auto[1]	endpoints[0x6]	1603	1			T22	1		T61	5		T5	2
data0	auto[1]	endpoints[0x7]	1357	1			T18	1		T22	1		T36	1
data0	auto[1]	endpoints[0x8]	1614	1			T22	1		T30	2		T61	7
data0	auto[1]	endpoints[0x9]	1482	1			T18	1		T22	1		T61	2
data0	auto[1]	endpoints[0xa]	1459	1			T22	1		T34	9		T61	5
data0	auto[1]	endpoints[0xb]	1450	1			T22	1		T35	1		T106	1