Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_in_enable	2	0	2	100.00	100	1	1	2
cp_in_iso	2	0	2	100.00	100	1	1	2
cp_in_stall	2	0	2	100.00	100	1	1	2
cp_pid	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	16	0	16	100.00	100	1	1	0

Summary for Variable cp_in_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7351

1

T20

4

T24

2

T61

82

auto[1]

53873

1

T7

1

T17

11

T18

16

---

Summary for Variable cp_in_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53695

1

T7

1

T17

11

T18

16

auto[1]

7529

1

T24

5

T32

1

T5

61

---

Summary for Variable cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_in_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

55371

1

T7

1

T17

11

T18

16

auto[1]

5853

1

T20

2

T24

3

T33

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

4402

1

T20

2

T24

2

T61

86

pkt_types[PidTypeInToken]

56822

1

T7

1

T17

11

T18

16

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins

cp_pid

cp_in_enable

cp_in_iso

cp_in_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

1246

1

T20

1

T61

21

T98

19

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

654

1

T20

1

T363

2

T105

22

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

80

1

T213

1

T318

2

T505

3

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

17

1

T321

1

T404

1

T329

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

1517

1

T61

43

T98

25

T318

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

787

1

T61

22

T98

5

T105

37

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

83

1

T5

5

T505

1

T388

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

18

1

T24

2

T355

2

T364

1

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[0]

3375

1

T20

2

T24

1

T61

61

pkt_types[PidTypeInToken]

auto[0]

auto[0]

auto[1]

1893

1

T363

5

T98

2

T317

2

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[0]

39

1

T24

1

T452

2

T372

1

pkt_types[PidTypeInToken]

auto[0]

auto[1]

auto[1]

47

1

T452

1

T336

1

T355

2

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[0]

41846

1

T7

1

T17

11

T18

16

pkt_types[PidTypeInToken]

auto[1]

auto[0]

auto[1]

2377

1

T20

1

T33

1

T61

61

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[0]

7185

1

T24

1

T32

1

T5

56

pkt_types[PidTypeInToken]

auto[1]

auto[1]

auto[1]

60

1

T24

1

T369

1

T417

2