Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

Group : usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.46	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	1	10	90.91
Crosses	54	39	15	27.78

Variables for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_avout	3	0	3	100.00	100	1	1	0
cp_avsetup	3	0	3	100.00	100	1	1	0
cp_pid	2	0	2	100.00	100	1	1	0
cp_rx	3	1	2	66.67	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::fifo_lvl_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_fifo_X_pid	54	39	15	27.78	100	1	1	0

Summary for Variable cp_avout

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avout

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20051	1			T4	54		T5	55		T6	51
solo	74141	1			T1	1		T2	1		T3	1
empty	3679	1			T20	1		T24	1		T31	1

---

Summary for Variable cp_avsetup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_avsetup

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
full	20073	1			T4	54		T5	55		T6	51
solo	32161	1			T20	9		T24	8		T61	672
empty	45740	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_pid

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

out

75402

1

T1

1

T2

1

T3

1

setup

22691

1

T20

6

T24

3

T61

345

---

Summary for Variable cp_rx

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_rx

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
full	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

solo

36

1

T31

1

T66

1

T67

1

empty

82628

1

T1

1

T2

1

T3

1

---

Summary for Cross cr_fifo_X_pid

Samples crossed: cp_avsetup cp_avout cp_rx cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	54	39	15	27.78	39

Automatically Generated Cross Bins for cr_fifo_X_pid

Element holes

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[full]	[full , solo]	*	--	--	4
[full]	[solo]	*	*	--	--	6
[full]	[empty]	[full]	*	--	--	2
[solo]	[full]	[full , solo]	*	--	--	4
[solo]	[solo]	[full]	*	--	--	2
[solo]	[empty]	[full]	*	--	--	2
[empty]	[full , solo]	[full , solo]	*	--	--	8
[empty]	[empty]	[full , solo]	*	--	--	4

Uncovered bins

cp_avsetup	cp_avout	cp_rx	cp_pid	COUNT	AT LEAST	NUMBER	STATUS
[full]	[empty]	[solo , empty]	[out]	--	--	2
[solo]	[full]	[empty]	[setup]	0	1	1
[solo]	[empty]	[solo , empty]	[out]	--	--	2
[empty]	[full , solo]	[empty]	[setup]	--	--	2

Covered bins

cp_avsetup

cp_avout

cp_rx

cp_pid

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

full

full

empty

out

15508

1

T4

40

T5

38

T6

45

full

full

empty

setup

4516

1

T4

14

T5

17

T6

6

full

empty

solo

setup

5

1

T51

1

T280

1

T281

1

full

empty

empty

setup

3

1

T281

1

T282

1

T283

1

solo

full

empty

out

5

1

T47

1

T49

1

T52

1

solo

solo

solo

out

5

1

T47

1

T49

1

T52

1

solo

solo

solo

setup

5

1

T47

1

T49

1

T52

1

solo

solo

empty

out

8223

1

T20

3

T24

5

T61

194

solo

solo

empty

setup

8341

1

T20

5

T24

2

T61

177

solo

empty

solo

setup

4

1

T48

1

T284

1

T285

1

solo

empty

empty

setup

2018

1

T20

1

T24

1

T61

2

empty

full

empty

out

4

1

T286

1

T287

1

T288

1

empty

solo

empty

out

43556

1

T1

1

T2

1

T3

1

empty

empty

empty

out

238

1

T31

1

T41

136

T66

1

empty

empty

empty

setup

173

1

T212

1

T289

1

T290

1