Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	171371	1			T1	4		T2	5		T3	3
all_pins[1]	171371	1			T1	4		T2	5		T3	3
all_pins[2]	171371	1			T1	4		T2	5		T3	3
all_pins[3]	171371	1			T1	4		T2	5		T3	3
all_pins[4]	171371	1			T1	4		T2	5		T3	3
all_pins[5]	171371	1			T1	4		T2	5		T3	3
all_pins[6]	171371	1			T1	4		T2	5		T3	3
all_pins[7]	171371	1			T1	4		T2	5		T3	3
all_pins[8]	171371	1			T1	4		T2	5		T3	3
all_pins[9]	171371	1			T1	4		T2	5		T3	3
all_pins[10]	171371	1			T1	4		T2	5		T3	3
all_pins[11]	171371	1			T1	4		T2	5		T3	3
all_pins[12]	171371	1			T1	4		T2	5		T3	3
all_pins[13]	171371	1			T1	4		T2	5		T3	3
all_pins[14]	171371	1			T1	4		T2	5		T3	3
all_pins[15]	171371	1			T1	4		T2	5		T3	3
all_pins[16]	171371	1			T1	4		T2	5		T3	3
all_pins[17]	171371	1			T1	4		T2	5		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	5481549	1			T1	128		T2	159		T3	95
values[0x1]	2323	1			T2	1		T3	1		T37	2
transitions[0x0=>0x1]	2024	1			T2	1		T3	1		T37	2
transitions[0x1=>0x0]	2024	1			T2	1		T3	1		T37	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	171260	1			T1	4		T2	5		T3	3
all_pins[0]	values[0x1]	111	1			T313	1		T314	1		T315	1
all_pins[0]	transitions[0x0=>0x1]	94	1			T313	1		T314	1		T315	1
all_pins[0]	transitions[0x1=>0x0]	859	1			T7	1		T22	12		T35	1
all_pins[1]	values[0x0]	170495	1			T1	4		T2	5		T3	3
all_pins[1]	values[0x1]	876	1			T7	1		T22	12		T35	1
all_pins[1]	transitions[0x0=>0x1]	862	1			T7	1		T22	12		T35	1
all_pins[1]	transitions[0x1=>0x0]	119	1			T19	1		T59	1		T60	1
all_pins[2]	values[0x0]	171238	1			T1	4		T2	5		T3	3
all_pins[2]	values[0x1]	133	1			T19	1		T59	1		T60	1
all_pins[2]	transitions[0x0=>0x1]	108	1			T19	1		T59	1		T60	1
all_pins[2]	transitions[0x1=>0x0]	53	1			T41	1		T196	1		T194	1
all_pins[3]	values[0x0]	171293	1			T1	4		T2	5		T3	3
all_pins[3]	values[0x1]	78	1			T41	1		T196	2		T194	1
all_pins[3]	transitions[0x0=>0x1]	55	1			T41	1		T196	1		T198	3
all_pins[3]	transitions[0x1=>0x0]	62	1			T42	1		T194	1		T195	2
all_pins[4]	values[0x0]	171286	1			T1	4		T2	5		T3	3
all_pins[4]	values[0x1]	85	1			T42	1		T196	1		T194	2
all_pins[4]	transitions[0x0=>0x1]	57	1			T42	1		T196	1		T302	3
all_pins[4]	transitions[0x1=>0x0]	44	1			T194	1		T198	2		T304	1
all_pins[5]	values[0x0]	171299	1			T1	4		T2	5		T3	3
all_pins[5]	values[0x1]	72	1			T194	3		T195	2		T198	3
all_pins[5]	transitions[0x0=>0x1]	51	1			T194	3		T195	2		T198	1
all_pins[5]	transitions[0x1=>0x0]	90	1			T63	1		T64	1		T65	1
all_pins[6]	values[0x0]	171260	1			T1	4		T2	5		T3	3
all_pins[6]	values[0x1]	111	1			T63	1		T64	1		T65	1
all_pins[6]	transitions[0x0=>0x1]	99	1			T63	1		T64	1		T65	1
all_pins[6]	transitions[0x1=>0x0]	48	1			T2	1		T46	1		T194	1
all_pins[7]	values[0x0]	171311	1			T1	4		T2	4		T3	3
all_pins[7]	values[0x1]	60	1			T2	1		T46	1		T194	1
all_pins[7]	transitions[0x0=>0x1]	48	1			T2	1		T46	1		T194	1
all_pins[7]	transitions[0x1=>0x0]	63	1			T48	1		T51	1		T53	1
all_pins[8]	values[0x0]	171296	1			T1	4		T2	5		T3	3
all_pins[8]	values[0x1]	75	1			T48	1		T51	1		T53	1
all_pins[8]	transitions[0x0=>0x1]	65	1			T48	1		T51	1		T53	1
all_pins[8]	transitions[0x1=>0x0]	66	1			T37	2		T57	2		T58	2
all_pins[9]	values[0x0]	171295	1			T1	4		T2	5		T3	3
all_pins[9]	values[0x1]	76	1			T37	2		T57	2		T58	2
all_pins[9]	transitions[0x0=>0x1]	63	1			T37	2		T57	2		T58	2
all_pins[9]	transitions[0x1=>0x0]	53	1			T194	1		T195	2		T302	2
all_pins[10]	values[0x0]	171305	1			T1	4		T2	5		T3	3
all_pins[10]	values[0x1]	66	1			T194	1		T195	2		T302	2
all_pins[10]	transitions[0x0=>0x1]	53	1			T194	1		T195	2		T302	2
all_pins[10]	transitions[0x1=>0x0]	92	1			T69	1		T70	1		T71	1
all_pins[11]	values[0x0]	171266	1			T1	4		T2	5		T3	3
all_pins[11]	values[0x1]	105	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x0=>0x1]	89	1			T69	1		T70	1		T71	1
all_pins[11]	transitions[0x1=>0x0]	69	1			T72	1		T73	1		T75	1
all_pins[12]	values[0x0]	171286	1			T1	4		T2	5		T3	3
all_pins[12]	values[0x1]	85	1			T72	1		T73	1		T75	1
all_pins[12]	transitions[0x0=>0x1]	64	1			T72	1		T73	1		T75	1
all_pins[12]	transitions[0x1=>0x0]	94	1			T3	1		T78	1		T79	1
all_pins[13]	values[0x0]	171256	1			T1	4		T2	5		T3	2
all_pins[13]	values[0x1]	115	1			T3	1		T78	1		T79	1
all_pins[13]	transitions[0x0=>0x1]	95	1			T3	1		T78	1		T79	1
all_pins[13]	transitions[0x1=>0x0]	53	1			T195	1		T198	3		T304	1
all_pins[14]	values[0x0]	171298	1			T1	4		T2	5		T3	3
all_pins[14]	values[0x1]	73	1			T194	1		T195	1		T198	3
all_pins[14]	transitions[0x0=>0x1]	44	1			T195	1		T198	2		T304	1
all_pins[14]	transitions[0x1=>0x0]	40	1			T194	1		T302	4		T304	1
all_pins[15]	values[0x0]	171302	1			T1	4		T2	5		T3	3
all_pins[15]	values[0x1]	69	1			T194	2		T302	4		T198	1
all_pins[15]	transitions[0x0=>0x1]	53	1			T194	1		T302	4		T304	1
all_pins[15]	transitions[0x1=>0x0]	62	1			T31	4		T66	4		T67	4
all_pins[16]	values[0x0]	171293	1			T1	4		T2	5		T3	3
all_pins[16]	values[0x1]	78	1			T31	4		T66	4		T67	4
all_pins[16]	transitions[0x0=>0x1]	69	1			T31	4		T66	4		T67	4
all_pins[16]	transitions[0x1=>0x0]	46	1			T54	1		T55	1		T56	1
all_pins[17]	values[0x0]	171316	1			T1	4		T2	5		T3	3
all_pins[17]	values[0x1]	55	1			T54	1		T55	1		T56	1
all_pins[17]	transitions[0x0=>0x1]	55	1			T54	1		T55	1		T56	1