Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4449	1			T61	93		T104	17		T98	37
invalid_ep[0xd]	4526	1			T61	94		T104	12		T98	28
invalid_ep[0xe]	4490	1			T24	1		T61	93		T104	11
invalid_ep[0xf]	4398	1			T24	1		T61	96		T104	10
endpoints[0x0]	11916	1			T3	1		T18	5		T20	4
endpoints[0x1]	13159	1			T22	2		T24	1		T31	11
endpoints[0x2]	13070	1			T18	3		T20	10		T22	2
endpoints[0x3]	12501	1			T18	2		T22	2		T24	2
endpoints[0x4]	14942	1			T2	1		T18	5		T20	3
endpoints[0x5]	12204	1			T7	2		T17	19		T18	3
endpoints[0x6]	11609	1			T18	4		T22	2		T24	2
endpoints[0x7]	11877	1			T18	2		T20	2		T22	2
endpoints[0x8]	15452	1			T18	1		T20	1		T22	2
endpoints[0x9]	13669	1			T1	1		T18	2		T20	2
endpoints[0xa]	13949	1			T18	4		T20	4		T22	2
endpoints[0xb]	13518	1			T18	1		T22	2		T35	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	22691	1			T20	6		T24	3		T61	345
pkt_types[PidTypeOutToken]	75402	1			T1	1		T2	1		T3	1
pkt_types[PidTypeInToken]	60632	1			T7	1		T17	11		T18	16

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	967	1			T61	20		T98	12		T321	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1017	1			T61	29		T98	8		T321	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1011	1			T61	23		T98	10		T105	19
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	958	1			T24	1		T61	29		T98	6
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1618	1			T24	1		T61	21		T4	3
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1443	1			T61	19		T45	1		T146	3
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1515	1			T20	1		T61	13		T5	2
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1545	1			T24	1		T61	16		T4	6
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1489	1			T20	2		T61	24		T5	3
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1498	1			T61	15		T5	2		T149	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1709	1			T61	25		T5	3		T150	5
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1524	1			T20	1		T61	22		T43	1
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1727	1			T20	1		T61	21		T4	5
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1626	1			T61	22		T5	5		T44	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1507	1			T20	1		T61	27		T152	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1537	1			T61	19		T6	6		T107	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1528	1			T61	28		T104	17		T98	11
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1547	1			T61	19		T104	12		T98	9
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1566	1			T61	27		T104	11		T98	12
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1480	1			T61	17		T104	10		T98	5
pkt_types[PidTypeOutToken]	endpoints[0x0]	4301	1			T3	1		T18	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	5814	1			T22	1		T24	1		T31	11
pkt_types[PidTypeOutToken]	endpoints[0x2]	5532	1			T18	1		T20	2		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	5406	1			T22	1		T66	11		T61	26
pkt_types[PidTypeOutToken]	endpoints[0x4]	7325	1			T2	1		T18	3		T22	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	4749	1			T7	1		T17	8		T18	2
pkt_types[PidTypeOutToken]	endpoints[0x6]	4136	1			T18	3		T22	1		T24	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4648	1			T20	1		T22	1		T36	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	7679	1			T18	1		T22	1		T24	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	6386	1			T1	1		T18	1		T22	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	6910	1			T18	4		T22	1		T80	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	6395	1			T22	1		T35	1		T106	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	963	1			T61	28		T98	7		T105	24
pkt_types[PidTypeInToken]	invalid_ep[0xd]	974	1			T61	21		T98	7		T105	25
pkt_types[PidTypeInToken]	invalid_ep[0xe]	945	1			T61	20		T98	17		T105	24
pkt_types[PidTypeInToken]	invalid_ep[0xf]	928	1			T61	26		T98	8		T105	24
pkt_types[PidTypeInToken]	endpoints[0x0]	4938	1			T18	4		T22	1		T61	17
pkt_types[PidTypeInToken]	endpoints[0x1]	4770	1			T22	1		T61	27		T4	10
pkt_types[PidTypeInToken]	endpoints[0x2]	4927	1			T18	2		T20	2		T22	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4410	1			T18	2		T22	1		T61	21
pkt_types[PidTypeInToken]	endpoints[0x4]	5051	1			T18	2		T20	1		T22	1
pkt_types[PidTypeInToken]	endpoints[0x5]	4874	1			T7	1		T17	11		T18	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4736	1			T18	1		T22	1		T24	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4640	1			T18	2		T22	1		T24	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4964	1			T22	1		T24	1		T30	8
pkt_types[PidTypeInToken]	endpoints[0x9]	4551	1			T18	1		T22	1		T24	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4436	1			T20	1		T22	1		T34	14
pkt_types[PidTypeInToken]	endpoints[0xb]	4525	1			T18	1		T22	1		T35	1