Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1			T196	4		T194	7		T195	4
all_values[1]	284	1			T196	4		T194	7		T195	4
all_values[2]	284	1			T196	4		T194	7		T195	4
all_values[3]	284	1			T196	4		T194	7		T195	4
all_values[4]	284	1			T196	4		T194	7		T195	4
all_values[5]	284	1			T196	4		T194	7		T195	4
all_values[6]	284	1			T196	4		T194	7		T195	4
all_values[7]	284	1			T196	4		T194	7		T195	4
all_values[8]	284	1			T196	4		T194	7		T195	4
all_values[9]	284	1			T196	4		T194	7		T195	4
all_values[10]	284	1			T196	4		T194	7		T195	4
all_values[11]	284	1			T196	4		T194	7		T195	4
all_values[12]	284	1			T196	4		T194	7		T195	4
all_values[13]	284	1			T196	4		T194	7		T195	4
all_values[14]	284	1			T196	4		T194	7		T195	4
all_values[15]	284	1			T196	4		T194	7		T195	4
all_values[16]	284	1			T196	4		T194	7		T195	4
all_values[17]	284	1			T196	4		T194	7		T195	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6828

1

T196

98

T194

180

T195

106

auto[1]

2260

1

T196

30

T194

44

T195

22

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6202

1

T196

87

T194

148

T195

89

auto[1]

2886

1

T196

41

T194

76

T195

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5371

1

T196

70

T194

132

T195

79

auto[1]

3717

1

T196

58

T194

92

T195

49

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	79	1			T194	1		T195	2		T302	1
all_values[0]	auto[0]	auto[1]	auto[0]	85	1			T196	2		T194	2		T302	2
all_values[0]	auto[1]	auto[0]	auto[1]	67	1			T196	2		T194	1		T195	2
all_values[0]	auto[1]	auto[1]	auto[1]	53	1			T194	3		T302	1		T278	1
all_values[1]	auto[0]	auto[0]	auto[0]	99	1			T196	2		T194	2		T302	2
all_values[1]	auto[0]	auto[1]	auto[0]	70	1			T196	2		T194	1		T195	1
all_values[1]	auto[1]	auto[0]	auto[1]	71	1			T194	2		T195	2		T302	1
all_values[1]	auto[1]	auto[1]	auto[1]	44	1			T194	2		T195	1		T278	2
all_values[2]	auto[0]	auto[0]	auto[0]	53	1			T194	1		T302	1		T278	2
all_values[2]	auto[0]	auto[0]	auto[1]	36	1			T194	2		T195	2		T303	1
all_values[2]	auto[0]	auto[1]	auto[0]	36	1			T196	2		T194	1		T302	1
all_values[2]	auto[0]	auto[1]	auto[1]	45	1			T302	1		T304	1		T305	1
all_values[2]	auto[1]	auto[0]	auto[1]	61	1			T194	2		T195	2		T302	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1			T196	2		T194	1		T304	1
all_values[3]	auto[0]	auto[0]	auto[0]	75	1			T194	3		T195	4		T302	1
all_values[3]	auto[0]	auto[0]	auto[1]	33	1			T196	1		T194	1		T302	2
all_values[3]	auto[0]	auto[1]	auto[0]	23	1			T194	1		T304	2		T306	1
all_values[3]	auto[0]	auto[1]	auto[1]	31	1			T198	1		T307	1		T305	2
all_values[3]	auto[1]	auto[0]	auto[1]	69	1			T196	1		T302	1		T278	2
all_values[3]	auto[1]	auto[1]	auto[1]	53	1			T196	2		T194	2		T198	2
all_values[4]	auto[0]	auto[0]	auto[0]	53	1			T194	2		T302	1		T278	1
all_values[4]	auto[0]	auto[0]	auto[1]	25	1			T194	2		T278	1		T303	1
all_values[4]	auto[0]	auto[1]	auto[0]	39	1			T196	1		T308	3		T309	1
all_values[4]	auto[0]	auto[1]	auto[1]	38	1			T195	2		T302	2		T304	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1			T196	2		T194	1		T195	2
all_values[4]	auto[1]	auto[1]	auto[1]	60	1			T196	1		T194	2		T302	1
all_values[5]	auto[0]	auto[0]	auto[0]	69	1			T194	3		T195	2		T302	4
all_values[5]	auto[0]	auto[0]	auto[1]	29	1			T196	2		T303	2		T305	1
all_values[5]	auto[0]	auto[1]	auto[0]	48	1			T278	1		T304	2		T307	2
all_values[5]	auto[0]	auto[1]	auto[1]	29	1			T194	1		T195	1		T198	2
all_values[5]	auto[1]	auto[0]	auto[1]	55	1			T196	2		T194	1		T278	2
all_values[5]	auto[1]	auto[1]	auto[1]	54	1			T194	2		T195	1		T198	1
all_values[6]	auto[0]	auto[0]	auto[0]	62	1			T194	3		T302	1		T278	1
all_values[6]	auto[0]	auto[0]	auto[1]	34	1			T196	1		T194	1		T302	1
all_values[6]	auto[0]	auto[1]	auto[0]	46	1			T196	1		T194	1		T195	3
all_values[6]	auto[0]	auto[1]	auto[1]	26	1			T196	1		T198	1		T305	1
all_values[6]	auto[1]	auto[0]	auto[1]	74	1			T196	1		T194	2		T195	1
all_values[6]	auto[1]	auto[1]	auto[1]	42	1			T278	2		T198	1		T304	2
all_values[7]	auto[0]	auto[0]	auto[0]	86	1			T196	3		T194	3		T195	1
all_values[7]	auto[0]	auto[1]	auto[0]	84	1			T194	2		T195	2		T302	1
all_values[7]	auto[1]	auto[0]	auto[1]	62	1			T196	1		T194	2		T195	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1			T278	1		T198	1		T303	1
all_values[8]	auto[0]	auto[0]	auto[0]	102	1			T194	2		T195	2		T302	3
all_values[8]	auto[0]	auto[1]	auto[0]	69	1			T196	3		T194	2		T198	3
all_values[8]	auto[1]	auto[0]	auto[1]	68	1			T194	3		T195	1		T302	1
all_values[8]	auto[1]	auto[1]	auto[1]	45	1			T196	1		T195	1		T198	1
all_values[9]	auto[0]	auto[0]	auto[0]	64	1			T196	1		T194	1		T302	1
all_values[9]	auto[0]	auto[0]	auto[1]	23	1			T194	1		T303	1		T304	1
all_values[9]	auto[0]	auto[1]	auto[0]	54	1			T196	1		T195	3		T302	2
all_values[9]	auto[0]	auto[1]	auto[1]	28	1			T303	1		T310	1		T304	1
all_values[9]	auto[1]	auto[0]	auto[1]	64	1			T196	1		T194	2		T195	1
all_values[9]	auto[1]	auto[1]	auto[1]	51	1			T196	1		T194	3		T302	1
all_values[10]	auto[0]	auto[0]	auto[0]	63	1			T194	2		T195	1		T198	1
all_values[10]	auto[0]	auto[0]	auto[1]	28	1			T194	1		T302	1		T303	1
all_values[10]	auto[0]	auto[1]	auto[0]	37	1			T196	3		T194	1		T278	2
all_values[10]	auto[0]	auto[1]	auto[1]	29	1			T194	1		T195	1		T302	1
all_values[10]	auto[1]	auto[0]	auto[1]	69	1			T194	1		T302	2		T278	1
all_values[10]	auto[1]	auto[1]	auto[1]	58	1			T196	1		T194	1		T195	2
all_values[11]	auto[0]	auto[0]	auto[0]	60	1			T196	1		T194	1		T302	1
all_values[11]	auto[0]	auto[0]	auto[1]	34	1			T196	1		T194	1		T195	1
all_values[11]	auto[0]	auto[1]	auto[0]	52	1			T194	2		T302	1		T198	3
all_values[11]	auto[0]	auto[1]	auto[1]	25	1			T302	1		T278	2		T303	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1			T196	2		T194	2		T195	3
all_values[11]	auto[1]	auto[1]	auto[1]	44	1			T194	1		T303	1		T304	1
all_values[12]	auto[0]	auto[0]	auto[0]	56	1			T195	3		T302	2		T278	2
all_values[12]	auto[0]	auto[0]	auto[1]	34	1			T196	1		T194	2		T198	1
all_values[12]	auto[0]	auto[1]	auto[0]	44	1			T196	1		T194	2		T195	1
all_values[12]	auto[0]	auto[1]	auto[1]	36	1			T196	1		T278	1		T307	1
all_values[12]	auto[1]	auto[0]	auto[1]	58	1			T196	1		T194	2		T278	1
all_values[12]	auto[1]	auto[1]	auto[1]	56	1			T194	1		T302	1		T307	2
all_values[13]	auto[0]	auto[0]	auto[0]	78	1			T196	2		T194	4		T195	1
all_values[13]	auto[0]	auto[0]	auto[1]	23	1			T311	3		T308	1		T312	2
all_values[13]	auto[0]	auto[1]	auto[0]	45	1			T194	1		T278	2		T304	3
all_values[13]	auto[0]	auto[1]	auto[1]	29	1			T194	1		T195	1		T307	1
all_values[13]	auto[1]	auto[0]	auto[1]	60	1			T194	1		T302	1		T303	1
all_values[13]	auto[1]	auto[1]	auto[1]	49	1			T196	2		T195	2		T278	1
all_values[14]	auto[0]	auto[0]	auto[0]	55	1			T196	1		T194	1		T195	1
all_values[14]	auto[0]	auto[0]	auto[1]	36	1			T194	1		T195	1		T302	2
all_values[14]	auto[0]	auto[1]	auto[0]	40	1			T278	1		T303	2		T304	1
all_values[14]	auto[0]	auto[1]	auto[1]	28	1			T198	1		T311	1		T309	1
all_values[14]	auto[1]	auto[0]	auto[1]	72	1			T196	3		T194	5		T195	2
all_values[14]	auto[1]	auto[1]	auto[1]	53	1			T198	2		T310	1		T304	3
all_values[15]	auto[0]	auto[0]	auto[0]	64	1			T196	1		T194	1		T310	2
all_values[15]	auto[0]	auto[0]	auto[1]	27	1			T194	1		T195	1		T278	1
all_values[15]	auto[0]	auto[1]	auto[0]	43	1			T278	1		T303	2		T311	3
all_values[15]	auto[0]	auto[1]	auto[1]	25	1			T302	3		T308	1		T309	1
all_values[15]	auto[1]	auto[0]	auto[1]	70	1			T196	3		T194	2		T195	3
all_values[15]	auto[1]	auto[1]	auto[1]	55	1			T194	3		T198	1		T304	3
all_values[16]	auto[0]	auto[0]	auto[0]	60	1			T194	1		T195	3		T302	1
all_values[16]	auto[0]	auto[0]	auto[1]	32	1			T196	1		T194	1		T278	1
all_values[16]	auto[0]	auto[1]	auto[0]	53	1			T302	2		T304	2		T306	2
all_values[16]	auto[0]	auto[1]	auto[1]	23	1			T196	1		T307	1		T311	1
all_values[16]	auto[1]	auto[0]	auto[1]	64	1			T196	1		T194	3		T195	1
all_values[16]	auto[1]	auto[1]	auto[1]	52	1			T196	1		T194	2		T302	1
all_values[17]	auto[0]	auto[0]	auto[0]	102	1			T196	4		T194	3		T195	3
all_values[17]	auto[0]	auto[1]	auto[0]	78	1			T302	2		T278	3		T198	1
all_values[17]	auto[1]	auto[0]	auto[1]	56	1			T194	2		T195	1		T302	1
all_values[17]	auto[1]	auto[1]	auto[1]	48	1			T194	2		T302	1		T310	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal