Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	83826	1			T1	3		T2	5		T3	7
all_values[1]	83826	1			T1	3		T2	5		T3	7
all_values[2]	83826	1			T1	3		T2	5		T3	7
all_values[3]	83826	1			T1	3		T2	5		T3	7
all_values[4]	83826	1			T1	3		T2	5		T3	7
all_values[5]	83826	1			T1	3		T2	5		T3	7
all_values[6]	83826	1			T1	3		T2	5		T3	7
all_values[7]	83826	1			T1	3		T2	5		T3	7
all_values[8]	83826	1			T1	3		T2	5		T3	7
all_values[9]	83826	1			T1	3		T2	5		T3	7
all_values[10]	83826	1			T1	3		T2	5		T3	7
all_values[11]	83826	1			T1	3		T2	5		T3	7
all_values[12]	83826	1			T1	3		T2	5		T3	7
all_values[13]	83826	1			T1	3		T2	5		T3	7
all_values[14]	83826	1			T1	3		T2	5		T3	7
all_values[15]	83826	1			T1	3		T2	5		T3	7
all_values[16]	83826	1			T1	3		T2	5		T3	7
all_values[17]	83826	1			T1	3		T2	5		T3	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2672791

1

T1

94

T2

158

T3

219

auto[1]

9641

1

T1

2

T2

2

T3

5

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2232299

1

T1

85

T2

146

T3

210

auto[1]

450133

1

T1

11

T2

14

T3

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55743	1			T1	3		T2	3		T3	7
all_values[0]	auto[0]	auto[1]	24764	1			T2	2		T27	1		T32	3
all_values[0]	auto[1]	auto[0]	3228	1			T50	3		T51	3		T52	3
all_values[0]	auto[1]	auto[1]	91	1			T341	1		T342	1		T343	1
all_values[1]	auto[0]	auto[0]	79399	1			T1	3		T2	5		T3	7
all_values[1]	auto[0]	auto[1]	3030	1			T28	2		T29	2		T32	1
all_values[1]	auto[1]	auto[0]	509	1			T31	2		T33	2		T53	2
all_values[1]	auto[1]	auto[1]	888	1			T31	12		T33	1		T53	1
all_values[2]	auto[0]	auto[0]	4241	1			T1	1		T2	4		T3	6
all_values[2]	auto[0]	auto[1]	79324	1			T1	2		T2	1		T3	1
all_values[2]	auto[1]	auto[0]	130	1			T39	1		T68	1		T69	1
all_values[2]	auto[1]	auto[1]	131	1			T39	1		T68	1		T69	1
all_values[3]	auto[0]	auto[0]	81937	1			T1	3		T2	5		T3	7
all_values[3]	auto[0]	auto[1]	293	1			T49	1		T22	1		T70	1
all_values[3]	auto[1]	auto[0]	1534	1			T49	1428		T217	4		T218	3
all_values[3]	auto[1]	auto[1]	62	1			T49	1		T218	1		T219	2
all_values[4]	auto[0]	auto[0]	4222	1			T1	1		T2	4		T3	6
all_values[4]	auto[0]	auto[1]	79449	1			T1	2		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	88	1			T48	1		T217	2		T218	1
all_values[4]	auto[1]	auto[1]	67	1			T48	1		T217	3		T218	3
all_values[5]	auto[0]	auto[0]	83312	1			T1	3		T2	5		T3	7
all_values[5]	auto[0]	auto[1]	365	1			T64	1		T7	1		T8	1
all_values[5]	auto[1]	auto[0]	102	1			T217	4		T218	1		T219	2
all_values[5]	auto[1]	auto[1]	47	1			T218	5		T219	4		T334	1
all_values[6]	auto[0]	auto[0]	83405	1			T1	3		T2	5		T3	7
all_values[6]	auto[0]	auto[1]	208	1			T9	1		T70	1		T71	1
all_values[6]	auto[1]	auto[0]	108	1			T217	1		T218	2		T219	1
all_values[6]	auto[1]	auto[1]	105	1			T72	1		T73	1		T74	1
all_values[7]	auto[0]	auto[0]	28197	1			T1	3		T3	5		T39	2
all_values[7]	auto[0]	auto[1]	55473	1			T2	3		T3	2		T27	4
all_values[7]	auto[1]	auto[0]	98	1			T2	1		T54	1		T217	1
all_values[7]	auto[1]	auto[1]	58	1			T2	1		T54	1		T218	3
all_values[8]	auto[0]	auto[0]	83087	1			T1	3		T2	5		T3	7
all_values[8]	auto[0]	auto[1]	67	1			T217	1		T218	1		T219	2
all_values[8]	auto[1]	auto[0]	584	1			T19	10		T55	10		T57	10
all_values[8]	auto[1]	auto[1]	88	1			T55	1		T59	1		T60	1
all_values[9]	auto[0]	auto[0]	83569	1			T1	3		T2	5		T3	2
all_values[9]	auto[0]	auto[1]	63	1			T217	2		T219	3		T333	1
all_values[9]	auto[1]	auto[0]	117	1			T3	3		T66	3		T67	3
all_values[9]	auto[1]	auto[1]	77	1			T3	2		T66	2		T67	2
all_values[10]	auto[0]	auto[0]	83296	1			T1	3		T2	5		T3	7
all_values[10]	auto[0]	auto[1]	369	1			T29	1		T35	2		T65	1
all_values[10]	auto[1]	auto[0]	100	1			T217	3		T218	4		T219	2
all_values[10]	auto[1]	auto[1]	61	1			T219	1		T334	3		T335	5
all_values[11]	auto[0]	auto[0]	82917	1			T1	2		T2	5		T3	7
all_values[11]	auto[0]	auto[1]	622	1			T1	1		T34	4		T36	4
all_values[11]	auto[1]	auto[0]	171	1			T17	1		T78	1		T79	1
all_values[11]	auto[1]	auto[1]	116	1			T17	1		T78	1		T79	1
all_values[12]	auto[0]	auto[0]	83428	1			T1	3		T2	5		T3	7
all_values[12]	auto[0]	auto[1]	240	1			T81	1		T83	1		T84	1
all_values[12]	auto[1]	auto[0]	99	1			T18	2		T80	2		T82	2
all_values[12]	auto[1]	auto[1]	59	1			T18	1		T80	1		T82	1
all_values[13]	auto[0]	auto[0]	83498	1			T1	1		T2	5		T3	7
all_values[13]	auto[0]	auto[1]	76	1			T81	1		T83	1		T84	1
all_values[13]	auto[1]	auto[0]	143	1			T1	1		T85	1		T86	1
all_values[13]	auto[1]	auto[1]	109	1			T1	1		T85	1		T86	1
all_values[14]	auto[0]	auto[0]	16693	1			T1	3		T2	5		T3	7
all_values[14]	auto[0]	auto[1]	66981	1			T39	1		T49	1430		T64	2
all_values[14]	auto[1]	auto[0]	98	1			T218	1		T219	6		T333	1
all_values[14]	auto[1]	auto[1]	54	1			T218	2		T335	3		T299	1
all_values[15]	auto[0]	auto[0]	4268	1			T1	1		T2	4		T3	6
all_values[15]	auto[0]	auto[1]	79390	1			T1	2		T2	1		T3	1
all_values[15]	auto[1]	auto[0]	105	1			T217	2		T218	3		T219	4
all_values[15]	auto[1]	auto[1]	63	1			T217	2		T218	3		T219	2
all_values[16]	auto[0]	auto[0]	82894	1			T1	3		T2	5		T3	7
all_values[16]	auto[0]	auto[1]	755	1			T29	1		T76	1		T77	1
all_values[16]	auto[1]	auto[0]	105	1			T34	4		T36	4		T75	4
all_values[16]	auto[1]	auto[1]	72	1			T34	4		T36	4		T75	4
all_values[17]	auto[0]	auto[0]	27187	1			T40	2		T43	2		T64	2
all_values[17]	auto[0]	auto[1]	56465	1			T1	3		T2	5		T3	7
all_values[17]	auto[1]	auto[0]	123	1			T61	1		T62	1		T63	1
all_values[17]	auto[1]	auto[1]	51	1			T61	1		T62	1		T63	1