Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

110886

1

T1

1

T2

1

T27

1

auto[1]

45798

1

T28

4

T29

12

T31

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29027	1			T37	2		T88	1		T49	1
max_len_m1	857	1			T34	1		T21	1		T5	2
max_len_m2	828	1			T34	1		T75	2		T49	2
max_len_m3	872	1			T31	2		T49	4		T7	2
five	1183	1			T49	7		T117	1		T70	2
four	1242	1			T31	2		T75	1		T49	1
three	808	1			T49	5		T176	2		T95	25
one	865	1			T31	2		T49	3		T176	1
zero	11904	1			T1	1		T28	4		T29	4

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23741	1			T37	1		T88	1		T49	1
max_len	auto[1]	5286	1			T37	1		T51	1		T6	2
max_len_m1	auto[0]	581	1			T34	1		T21	1		T5	1
max_len_m1	auto[1]	276	1			T5	1		T164	1		T176	1
max_len_m2	auto[0]	562	1			T34	1		T75	2		T49	2
max_len_m2	auto[1]	266	1			T4	2		T111	1		T5	1
max_len_m3	auto[0]	579	1			T31	1		T49	4		T7	1
max_len_m3	auto[1]	293	1			T31	1		T7	1		T5	1
five	auto[0]	610	1			T49	7		T117	1		T70	1
five	auto[1]	573	1			T70	1		T164	1		T95	12
four	auto[0]	616	1			T31	1		T75	1		T49	1
four	auto[1]	626	1			T31	1		T5	1		T162	1
three	auto[0]	384	1			T49	5		T176	2		T95	11
three	auto[1]	424	1			T95	14		T255	8		T292	1
one	auto[0]	390	1			T31	1		T49	3		T176	1
one	auto[1]	475	1			T31	1		T95	16		T255	8
zero	auto[0]	557	1			T1	1		T38	1		T311	1
zero	auto[1]	11347	1			T28	4		T29	4		T38	1