Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
78.95	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	24	72	75.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	24	72	75.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

69782

1

T2

1

T27

1

T28

9

auto[1]

78233

1

T28

8

T29

19

T31

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	12116	1			T29	3		T31	3		T91	4
endpoints[0x1]	11042	1			T2	1		T29	1		T31	3
endpoints[0x2]	13369	1			T27	1		T29	4		T31	3
endpoints[0x3]	10527	1			T29	6		T31	3		T75	11
endpoints[0x4]	11846	1			T29	4		T31	3		T77	1
endpoints[0x5]	17095	1			T29	1		T31	3		T33	3
endpoints[0x6]	12913	1			T29	5		T31	3		T37	3
endpoints[0x7]	10961	1			T28	17		T29	4		T31	3
endpoints[0x8]	12686	1			T31	3		T34	11		T76	2
endpoints[0x9]	14025	1			T29	1		T31	3		T311	1
endpoints[0xa]	11207	1			T31	3		T38	3		T312	1
endpoints[0xb]	10228	1			T29	2		T31	3		T313	1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	167	1			T29	5		T98	4		T120	3
ack	38559	1			T28	4		T29	2		T31	12
data1	50672	1			T28	1		T29	12		T34	5
data0	58557	1			T2	1		T27	1		T28	12

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	24	72	75.00	24

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Element holes

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	NUMBER	STATUS
[nak , ack]	[auto[0]]	*	--	--	24

Covered bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[1]	endpoints[0x0]	14	1			T314	1		T315	2		T316	1
nak	auto[1]	endpoints[0x1]	13	1			T98	1		T317	1		T318	2
nak	auto[1]	endpoints[0x2]	13	1			T319	1		T315	2		T320	1
nak	auto[1]	endpoints[0x3]	18	1			T29	2		T98	1		T120	1
nak	auto[1]	endpoints[0x4]	12	1			T29	1		T315	1		T320	1
nak	auto[1]	endpoints[0x5]	11	1			T319	2		T317	1		T321	1
nak	auto[1]	endpoints[0x6]	10	1			T120	1		T322	1		T323	1
nak	auto[1]	endpoints[0x7]	17	1			T29	1		T98	1		T319	1
nak	auto[1]	endpoints[0x8]	14	1			T320	1		T322	2		T324	1
nak	auto[1]	endpoints[0x9]	13	1			T98	1		T120	1		T325	1
nak	auto[1]	endpoints[0xa]	13	1			T317	1		T320	1		T326	1
nak	auto[1]	endpoints[0xb]	19	1			T29	1		T321	1		T320	1
ack	auto[1]	endpoints[0x0]	3294	1			T31	1		T91	1		T65	11
ack	auto[1]	endpoints[0x1]	3102	1			T31	1		T22	1		T162	1
ack	auto[1]	endpoints[0x2]	3366	1			T29	1		T31	1		T5	13
ack	auto[1]	endpoints[0x3]	2947	1			T31	1		T162	1		T6	6
ack	auto[1]	endpoints[0x4]	3054	1			T31	1		T22	5		T98	1
ack	auto[1]	endpoints[0x5]	3620	1			T31	1		T33	1		T4	38
ack	auto[1]	endpoints[0x6]	3043	1			T29	1		T31	1		T37	1
ack	auto[1]	endpoints[0x7]	3048	1			T28	4		T31	1		T51	1
ack	auto[1]	endpoints[0x8]	3392	1			T31	1		T52	1		T162	1
ack	auto[1]	endpoints[0x9]	3407	1			T31	1		T163	1		T7	1
ack	auto[1]	endpoints[0xa]	3165	1			T31	1		T38	1		T50	1
ack	auto[1]	endpoints[0xb]	3121	1			T31	1		T22	2		T162	1
data1	auto[0]	endpoints[0x0]	2248	1			T29	3		T91	1		T22	1
data1	auto[0]	endpoints[0x1]	1938	1			T29	1		T20	4		T6	3
data1	auto[0]	endpoints[0x2]	2803	1			T29	1		T5	6		T6	1
data1	auto[0]	endpoints[0x3]	1801	1			T75	5		T6	3		T167	4
data1	auto[0]	endpoints[0x4]	2362	1			T5	6		T6	3		T95	17
data1	auto[0]	endpoints[0x5]	4387	1			T4	10		T22	2		T5	6
data1	auto[0]	endpoints[0x6]	3006	1			T29	1		T22	8		T240	3
data1	auto[0]	endpoints[0x7]	1955	1			T28	1		T36	5		T51	1
data1	auto[0]	endpoints[0x8]	2373	1			T34	5		T76	1		T52	1
data1	auto[0]	endpoints[0x9]	3087	1			T22	4		T111	1		T117	4
data1	auto[0]	endpoints[0xa]	1974	1			T50	1		T111	2		T174	1
data1	auto[0]	endpoints[0xb]	1527	1			T19	3		T164	2		T167	3
data1	auto[1]	endpoints[0x0]	1800	1			T91	1		T65	7		T327	1
data1	auto[1]	endpoints[0x1]	1684	1			T6	3		T95	17		T165	2
data1	auto[1]	endpoints[0x2]	1850	1			T29	1		T5	6		T6	4
data1	auto[1]	endpoints[0x3]	1604	1			T29	1		T98	1		T6	3
data1	auto[1]	endpoints[0x4]	1700	1			T22	4		T5	6		T6	3
data1	auto[1]	endpoints[0x5]	2035	1			T29	1		T4	28		T22	2
data1	auto[1]	endpoints[0x6]	1644	1			T29	1		T70	8		T171	1
data1	auto[1]	endpoints[0x7]	1664	1			T29	1		T51	1		T22	3
data1	auto[1]	endpoints[0x8]	1878	1			T52	1		T173	30		T164	2
data1	auto[1]	endpoints[0x9]	1906	1			T111	1		T116	9		T117	3
data1	auto[1]	endpoints[0xa]	1721	1			T50	1		T111	2		T190	1
data1	auto[1]	endpoints[0xb]	1725	1			T29	1		T22	1		T164	3
data0	auto[0]	endpoints[0x0]	3194	1			T31	1		T91	1		T20	1
data0	auto[0]	endpoints[0x1]	2776	1			T2	1		T31	1		T20	4
data0	auto[0]	endpoints[0x2]	3757	1			T27	1		T29	1		T31	1
data0	auto[0]	endpoints[0x3]	2735	1			T31	1		T75	6		T89	1
data0	auto[0]	endpoints[0x4]	3276	1			T29	2		T31	1		T77	1
data0	auto[0]	endpoints[0x5]	5395	1			T31	1		T33	1		T35	1
data0	auto[0]	endpoints[0x6]	3767	1			T29	1		T31	1		T37	1
data0	auto[0]	endpoints[0x7]	2827	1			T28	8		T29	1		T31	1
data0	auto[0]	endpoints[0x8]	3398	1			T31	1		T34	6		T76	1
data0	auto[0]	endpoints[0x9]	4000	1			T29	1		T31	1		T311	1
data0	auto[0]	endpoints[0xa]	2834	1			T31	1		T38	1		T312	1
data0	auto[0]	endpoints[0xb]	2352	1			T31	1		T313	1		T19	4
data0	auto[1]	endpoints[0x0]	1561	1			T31	1		T65	11		T162	1
data0	auto[1]	endpoints[0x1]	1525	1			T31	1		T22	1		T98	1
data0	auto[1]	endpoints[0x2]	1576	1			T31	1		T5	7		T162	1
data0	auto[1]	endpoints[0x3]	1419	1			T29	3		T31	1		T162	1
data0	auto[1]	endpoints[0x4]	1438	1			T29	1		T31	1		T22	1
data0	auto[1]	endpoints[0x5]	1642	1			T31	1		T33	1		T35	1
data0	auto[1]	endpoints[0x6]	1440	1			T29	1		T31	1		T37	1
data0	auto[1]	endpoints[0x7]	1445	1			T28	4		T29	1		T31	1
data0	auto[1]	endpoints[0x8]	1622	1			T31	1		T162	1		T173	18
data0	auto[1]	endpoints[0x9]	1604	1			T31	1		T163	1		T7	1
data0	auto[1]	endpoints[0xa]	1494	1			T31	1		T38	1		T162	1
data0	auto[1]	endpoints[0xb]	1480	1			T31	1		T22	1		T162	1