Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 8873 1 T40 5 T22 52 T241 11
auto[1] 53858 1 T40 3 T28 4 T29 12


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55290 1 T40 8 T28 4 T29 12
auto[1] 7441 1 T32 1 T121 2 T114 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 55823 1 T40 5 T28 4 T29 12
auto[1] 6908 1 T40 3 T30 1 T22 36


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4446 1 T40 1 T22 32 T241 3
pkt_types[PidTypeInToken] 58285 1 T40 7 T28 4 T29 12


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1351 1 T40 1 T22 10 T241 1
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 912 1 T22 4 T241 2 T123 24
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 83 1 T176 3 T191 1 T346 3
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 14 1 T121 1 T492 1 T401 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1184 1 T22 11 T176 1 T123 32
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 775 1 T22 7 T362 1 T377 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 114 1 T176 5 T191 1 T346 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 13 1 T406 1 T527 1 T396 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 3816 1 T40 4 T22 25 T241 2
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2613 1 T22 13 T241 6 T362 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 46 1 T492 1 T490 1 T353 1
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 38 1 T492 1 T474 1 T505 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42150 1 T28 4 T29 12 T31 12
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2489 1 T40 3 T30 1 T22 12
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7079 1 T32 1 T121 1 T114 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 54 1 T466 1 T392 1 T474 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%