Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.03	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	192	2	190	98.96

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	0	3	100.00	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	2	190	98.96	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17281

1

T1

1

T40

11

T49

142

auto[1]

81006

1

T2

1

T27

1

T28

9

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

95765

1

T1

1

T2

1

T27

1

auto[1]

2522

1

T87

1

T121

3

T225

1

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

84154

1

T1

1

T2

1

T27

1

auto[1]

14133

1

T40

8

T77

1

T50

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	9045	1			T40	2		T22	56		T241	2
pkt_types[PidTypeSetupToken]	19233	1			T40	4		T89	1		T50	1
pkt_types[PidTypeOutToken]	69974	1			T1	1		T2	1		T27	1

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17795

1

T1

1

T40

8

T76

1

auto[1]

80492

1

T2

1

T27

1

T40

3

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68201

1

T1

1

T2

1

T27

1

auto[1]

30086

1

T40

3

T89

1

T50

2

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

97596

1

T1

1

T2

1

T27

1

auto[1]

691

1

T76

2

T344

1

T121

4

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	2	190	98.96	2

Automatically Generated Cross Bins for cr_pid_x_epconfig

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER	STATUS
[pkt_types[PidTypeSetupToken]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[pkt_types[PidTypeOutToken]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

674

1

T176

1

T345

3

T346

5

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

526

1

T40

1

T123

32

T345

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

83

1

T176

8

T191

3

T346

4

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T347

1

T348

1

T349

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T350

1

T351

1

T352

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T353

1

T354

1

T355

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T356

1

T357

1

T358

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T359

1

T360

1

T361

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

431

1

T22

11

T241

1

T123

13

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

541

1

T362

2

T363

19

T183

24

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T350

1

T364

1

T365

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T366

1

T367

1

T368

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T369

1

T370

1

T361

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T371

2

T372

1

T373

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T374

1

T356

1

T355

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T375

1

T376

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

727

1

T22

4

T121

1

T176

2

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

498

1

T241

1

T121

1

T377

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

92

1

T191

3

T346

1

T378

6

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T379

1

T380

1

T376

2

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T381

1

T382

1

T383

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T384

1

T385

1

T386

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T374

1

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T387

1

T388

1

T389

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

477

1

T40

1

T22

7

T362

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

390

1

T363

8

T390

3

T391

15

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

7

1

T392

1

T353

1

T393

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T394

1

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

11

1

T395

2

T396

1

T397

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T398

1

-

-

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T399

1

T400

1

T357

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T347

1

T401

1

T402

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

496

1

T124

12

T183

44

T391

21

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

478

1

T22

7

T123

16

T124

15

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

4

1

T403

1

T404

1

T405

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T406

1

T401

1

T407

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T408

1

T409

1

T410

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T411

1

T380

1

T412

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T351

1

T413

1

T414

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T414

1

T415

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

606

1

T123

11

T346

6

T124

17

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

454

1

T22

4

T391

11

T193

10

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

84

1

T176

4

T191

3

T416

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T417

1

T402

1

T418

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T350

1

T419

1

T361

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T377

1

T420

1

T421

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T422

1

T423

1

T424

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T387

1

T425

1

T426

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

791

1

T22

14

T124

25

T363

22

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T363

1

T391

1

T427

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2

1

T428

1

T376

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

4

1

T429

1

T430

1

T431

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T372

1

T125

1

T383

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T432

1

T433

1

T375

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T434

1

T412

1

T435

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T436

1

T437

1

T438

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1388

1

T22

7

T176

2

T191

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T22

2

T124

4

T363

5

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

74

1

T176

2

T377

1

T346

4

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T439

1

T401

1

T440

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T366

1

T441

2

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T442

1

T407

1

T443

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

2

1

T384

1

T399

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T441

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

834

1

T362

2

T83

1

T345

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

856

1

T40

4

T241

1

T123

53

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T379

1

T444

2

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

11

1

T347

2

T445

1

T446

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

2

1

T447

1

T393

1

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T353

1

T347

1

T448

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

7

1

T396

1

T401

1

T449

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T450

1

T451

1

T407

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

613

1

T22

29

T241

1

T123

27

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

765

1

T362

1

T363

37

T183

27

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T373

1

T403

1

T350

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T429

1

T397

2

T379

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T420

1

T452

1

T453

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

11

1

T373

1

T445

1

T454

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

2

1

T455

1

T456

1

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T377

1

T384

1

T448

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

927

1

T22

10

T121

1

T123

61

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

771

1

T241

1

T391

17

T457

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

8

1

T436

1

T448

1

T449

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T389

1

T399

1

T380

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

11

1

T381

1

T451

1

T411

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T458

1

T459

1

T430

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T447

1

T460

1

T461

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T396

1

T370

1

T376

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

742

1

T22

4

T241

2

T362

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

589

1

T363

11

T390

6

T391

22

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T379

1

T380

1

T394

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T462

1

T394

1

T463

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T370

1

T464

1

T465

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T466

1

T467

1

T468

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T377

1

T366

1

T450

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T371

1

T396

1

T469

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

771

1

T226

1

T309

1

T310

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

746

1

T22

20

T123

16

T124

11

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T445

1

T403

1

T470

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T392

1

T450

1

T436

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

8

1

T449

1

T471

1

T470

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T350

1

T411

1

T472

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T392

2

T436

1

T419

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T385

1

T473

1

T414

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

800

1

T123

25

T81

1

T124

22

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

730

1

T22

11

T391

17

T193

29

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T474

1

T350

1

T434

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T447

2

T369

1

T475

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T476

1

T447

1

T477

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T377

1

T384

2

T447

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T423

1

T478

1

T479

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T423

1

T408

1

T475

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1561

1

T89

1

T20

1

T22

18

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

76

1

T22

1

T61

1

T55

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

7

1

T397

1

T373

1

T445

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T477

1

T369

1

T480

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

15

1

T366

1

T373

1

T385

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T433

1

T418

1

T410

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T481

1

T437

1

T440

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

6140

1

T4

22

T22

19

T229

5

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

1655

1

T50

1

T51

1

T52

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

349

1

T167

7

T176

4

T377

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T429

1

T403

1

T482

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T414

1

T434

2

T483

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T451

1

T397

2

T484

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T121

1

T393

1

T458

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T377

1

T392

1

T474

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1032

1

T1

1

T49

142

T81

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

802

1

T40

3

T362

2

T123

52

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T388

1

T374

1

T423

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T395

1

T354

1

T485

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T447

2

T350

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T396

4

T351

1

T464

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T449

1

T376

1

T361

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T440

2

T486

1

T487

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

641

1

T22

23

T241

1

T123

27

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

783

1

T362

2

T345

1

T363

32

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T373

1

T350

1

T402

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T488

1

T418

1

T489

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

15

1

T406

1

T395

1

T429

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T371

1

T372

1

T413

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T490

1

T356

1

T422

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T403

2

T491

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

990

1

T22

12

T123

39

T81

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

758

1

T241

1

T121

1

T492

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T384

1

T432

1

T477

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T436

1

T379

3

T389

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T451

3

T444

1

T349

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

9

1

T359

1

T447

1

T408

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T439

1

T429

2

T493

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T451

1

T464

1

T383

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

747

1

T40

2

T22

8

T241

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

576

1

T363

16

T390

6

T391

20

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T429

1

T494

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T436

1

T379

1

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T403

1

T495

1

T387

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T466

1

T445

1

T400

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T359

1

T403

1

T387

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T347

1

T462

1

T419

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

808

1

T312

1

T496

1

T497

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

749

1

T22

21

T123

26

T124

18

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

11

1

T347

2

T445

2

T402

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T439

1

T498

1

T387

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

52

1

T76

1

T129

1

T147

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T370

1

T420

1

T472

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T392

2

T490

1

T450

2

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T414

1

T455

1

T412

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50519

1

T2

1

T27

1

T28

9

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

793

1

T77

1

T22

6

T499

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

1010

1

T87

1

T225

1

T167

11

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T396

1

T481

1

T500

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

61

1

T76

1

T121

1

T129

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

54

1

T344

1

T288

1

T501

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

4

1

T394

1

T386

1

T424

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T393

1

T423

1

T502

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1240

1

T22

22

T124

47

T363

34

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T22

1

T503

1

T504

2

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

9

1

T505

1

T481

1

T420

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T429

2

T477

1

T506

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T454

1

T507

1

T508

2

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T434

1

T509

1

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T121

1

T450

1

T393

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

7662

1

T50

1

T51

1

T52

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T21

1

T22

1

T189

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

347

1

T167

13

T176

5

T227

6

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T439

1

T403

1

T350

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T414

1

T434

1

T383

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

8

1

T353

2

T508

1

T510

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T121

1

T439

2

T432

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

8

1

T451

1

T356

2

T441

1