Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	83826	1			T1	3		T2	5		T3	7
all_pins[1]	83826	1			T1	3		T2	5		T3	7
all_pins[2]	83826	1			T1	3		T2	5		T3	7
all_pins[3]	83826	1			T1	3		T2	5		T3	7
all_pins[4]	83826	1			T1	3		T2	5		T3	7
all_pins[5]	83826	1			T1	3		T2	5		T3	7
all_pins[6]	83826	1			T1	3		T2	5		T3	7
all_pins[7]	83826	1			T1	3		T2	5		T3	7
all_pins[8]	83826	1			T1	3		T2	5		T3	7
all_pins[9]	83826	1			T1	3		T2	5		T3	7
all_pins[10]	83826	1			T1	3		T2	5		T3	7
all_pins[11]	83826	1			T1	3		T2	5		T3	7
all_pins[12]	83826	1			T1	3		T2	5		T3	7
all_pins[13]	83826	1			T1	3		T2	5		T3	7
all_pins[14]	83826	1			T1	3		T2	5		T3	7
all_pins[15]	83826	1			T1	3		T2	5		T3	7
all_pins[16]	83826	1			T1	3		T2	5		T3	7
all_pins[17]	83826	1			T1	3		T2	5		T3	7

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2680233	1			T1	95		T2	159		T3	222
values[0x1]	2199	1			T1	1		T2	1		T3	2
transitions[0x0=>0x1]	1963	1			T1	1		T2	1		T3	2
transitions[0x1=>0x0]	1963	1			T1	1		T2	1		T3	2

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	83735	1			T1	3		T2	5		T3	7
all_pins[0]	values[0x1]	91	1			T341	1		T342	1		T343	1
all_pins[0]	transitions[0x0=>0x1]	78	1			T341	1		T342	1		T343	1
all_pins[0]	transitions[0x1=>0x0]	875	1			T31	12		T33	1		T53	1
all_pins[1]	values[0x0]	82938	1			T1	3		T2	5		T3	7
all_pins[1]	values[0x1]	888	1			T31	12		T33	1		T53	1
all_pins[1]	transitions[0x0=>0x1]	870	1			T31	12		T33	1		T53	1
all_pins[1]	transitions[0x1=>0x0]	113	1			T39	1		T68	1		T69	1
all_pins[2]	values[0x0]	83695	1			T1	3		T2	5		T3	7
all_pins[2]	values[0x1]	131	1			T39	1		T68	1		T69	1
all_pins[2]	transitions[0x0=>0x1]	124	1			T39	1		T68	1		T69	1
all_pins[2]	transitions[0x1=>0x0]	55	1			T49	1		T219	2		T335	3
all_pins[3]	values[0x0]	83764	1			T1	3		T2	5		T3	7
all_pins[3]	values[0x1]	62	1			T49	1		T218	1		T219	2
all_pins[3]	transitions[0x0=>0x1]	50	1			T49	1		T219	2		T335	3
all_pins[3]	transitions[0x1=>0x0]	55	1			T48	1		T217	3		T218	2
all_pins[4]	values[0x0]	83759	1			T1	3		T2	5		T3	7
all_pins[4]	values[0x1]	67	1			T48	1		T217	3		T218	3
all_pins[4]	transitions[0x0=>0x1]	50	1			T48	1		T217	3		T218	1
all_pins[4]	transitions[0x1=>0x0]	30	1			T218	3		T219	3		T334	1
all_pins[5]	values[0x0]	83779	1			T1	3		T2	5		T3	7
all_pins[5]	values[0x1]	47	1			T218	5		T219	4		T334	1
all_pins[5]	transitions[0x0=>0x1]	41	1			T218	5		T219	4		T334	1
all_pins[5]	transitions[0x1=>0x0]	99	1			T72	1		T73	1		T74	1
all_pins[6]	values[0x0]	83721	1			T1	3		T2	5		T3	7
all_pins[6]	values[0x1]	105	1			T72	1		T73	1		T74	1
all_pins[6]	transitions[0x0=>0x1]	95	1			T72	1		T73	1		T74	1
all_pins[6]	transitions[0x1=>0x0]	48	1			T2	1		T54	1		T218	3
all_pins[7]	values[0x0]	83768	1			T1	3		T2	4		T3	7
all_pins[7]	values[0x1]	58	1			T2	1		T54	1		T218	3
all_pins[7]	transitions[0x0=>0x1]	45	1			T2	1		T54	1		T218	2
all_pins[7]	transitions[0x1=>0x0]	75	1			T55	1		T59	1		T60	1
all_pins[8]	values[0x0]	83738	1			T1	3		T2	5		T3	7
all_pins[8]	values[0x1]	88	1			T55	1		T59	1		T60	1
all_pins[8]	transitions[0x0=>0x1]	71	1			T55	1		T59	1		T60	1
all_pins[8]	transitions[0x1=>0x0]	60	1			T3	2		T66	2		T67	2
all_pins[9]	values[0x0]	83749	1			T1	3		T2	5		T3	5
all_pins[9]	values[0x1]	77	1			T3	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	56	1			T3	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	40	1			T334	2		T335	3		T339	1
all_pins[10]	values[0x0]	83765	1			T1	3		T2	5		T3	7
all_pins[10]	values[0x1]	61	1			T219	1		T334	3		T335	5
all_pins[10]	transitions[0x0=>0x1]	47	1			T219	1		T334	3		T335	4
all_pins[10]	transitions[0x1=>0x0]	102	1			T17	1		T78	1		T79	1
all_pins[11]	values[0x0]	83710	1			T1	3		T2	5		T3	7
all_pins[11]	values[0x1]	116	1			T17	1		T78	1		T79	1
all_pins[11]	transitions[0x0=>0x1]	93	1			T17	1		T78	1		T79	1
all_pins[11]	transitions[0x1=>0x0]	36	1			T18	1		T80	1		T82	1
all_pins[12]	values[0x0]	83767	1			T1	3		T2	5		T3	7
all_pins[12]	values[0x1]	59	1			T18	1		T80	1		T82	1
all_pins[12]	transitions[0x0=>0x1]	49	1			T18	1		T80	1		T82	1
all_pins[12]	transitions[0x1=>0x0]	99	1			T1	1		T85	1		T86	1
all_pins[13]	values[0x0]	83717	1			T1	2		T2	5		T3	7
all_pins[13]	values[0x1]	109	1			T1	1		T85	1		T86	1
all_pins[13]	transitions[0x0=>0x1]	94	1			T1	1		T85	1		T86	1
all_pins[13]	transitions[0x1=>0x0]	39	1			T218	2		T335	2		T299	1
all_pins[14]	values[0x0]	83772	1			T1	3		T2	5		T3	7
all_pins[14]	values[0x1]	54	1			T218	2		T335	3		T299	1
all_pins[14]	transitions[0x0=>0x1]	39	1			T218	1		T335	2		T339	3
all_pins[14]	transitions[0x1=>0x0]	48	1			T217	2		T218	2		T219	2
all_pins[15]	values[0x0]	83763	1			T1	3		T2	5		T3	7
all_pins[15]	values[0x1]	63	1			T217	2		T218	3		T219	2
all_pins[15]	transitions[0x0=>0x1]	49	1			T217	2		T218	3		T219	2
all_pins[15]	transitions[0x1=>0x0]	58	1			T34	4		T36	4		T75	4
all_pins[16]	values[0x0]	83754	1			T1	3		T2	5		T3	7
all_pins[16]	values[0x1]	72	1			T34	4		T36	4		T75	4
all_pins[16]	transitions[0x0=>0x1]	61	1			T34	4		T36	4		T75	4
all_pins[16]	transitions[0x1=>0x0]	40	1			T61	1		T62	1		T63	1
all_pins[17]	values[0x0]	83775	1			T1	3		T2	5		T3	7
all_pins[17]	values[0x1]	51	1			T61	1		T62	1		T63	1
all_pins[17]	transitions[0x0=>0x1]	51	1			T61	1		T62	1		T63	1