Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	4634	1			T22	37		T168	7		T122	13
invalid_ep[0xd]	4562	1			T22	44		T168	13		T122	11
invalid_ep[0xe]	4516	1			T42	1		T22	31		T121	1
invalid_ep[0xf]	4531	1			T22	43		T121	1		T168	11
endpoints[0x0]	12754	1			T1	1		T29	3		T31	2
endpoints[0x1]	12470	1			T2	1		T29	1		T31	2
endpoints[0x2]	14059	1			T27	1		T29	3		T31	2
endpoints[0x3]	11993	1			T29	4		T31	2		T75	11
endpoints[0x4]	13139	1			T40	5		T29	3		T30	1
endpoints[0x5]	17561	1			T29	1		T31	2		T33	2
endpoints[0x6]	14582	1			T29	4		T31	2		T37	2
endpoints[0x7]	12123	1			T40	6		T28	13		T29	3
endpoints[0x8]	13792	1			T31	2		T34	11		T76	2
endpoints[0x9]	14916	1			T29	1		T31	2		T311	1
endpoints[0xa]	12349	1			T31	2		T38	2		T312	1
endpoints[0xb]	11280	1			T40	8		T29	1		T31	2

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	23287	1			T40	4		T89	1		T50	1
pkt_types[PidTypeOutToken]	75977	1			T1	1		T2	1		T27	1
pkt_types[PidTypeInToken]	62397	1			T40	7		T28	4		T29	12

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1005	1			T22	9		T123	21		T124	17
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1011	1			T22	13		T377	1		T123	22
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1038	1			T22	8		T123	23		T492	1
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1000	1			T22	3		T123	22		T124	22
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1545	1			T91	1		T20	1		T22	7
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1570	1			T22	4		T165	2		T362	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1639	1			T22	10		T23	1		T6	4
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1569	1			T89	1		T22	10		T241	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1661	1			T22	10		T226	1		T61	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1757	1			T4	22		T22	13		T241	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1576	1			T22	9		T171	1		T172	21
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1576	1			T40	2		T51	1		T22	11
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1646	1			T52	1		T21	1		T22	10
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1622	1			T22	10		T111	1		T70	9
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1561	1			T50	1		T22	11		T111	2
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1511	1			T40	2		T22	8		T164	3
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1559	1			T22	5		T168	7		T122	13
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1469	1			T22	6		T168	13		T122	11
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1482	1			T42	1		T22	8		T168	18
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1493	1			T22	13		T121	1		T168	11
pkt_types[PidTypeOutToken]	endpoints[0x0]	5489	1			T1	1		T29	3		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	4687	1			T2	1		T29	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x2]	6458	1			T27	1		T29	2		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x3]	4634	1			T31	1		T75	11		T17	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5715	1			T40	2		T29	2		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x5]	9651	1			T31	1		T33	1		T35	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	6951	1			T29	2		T31	1		T37	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	4814	1			T28	9		T29	1		T31	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5715	1			T31	1		T34	11		T76	2
pkt_types[PidTypeOutToken]	endpoints[0x9]	7159	1			T29	1		T31	1		T311	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	4789	1			T31	1		T38	1		T312	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	3912	1			T40	3		T31	1		T313	1
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1041	1			T22	16		T123	25		T492	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1017	1			T22	14		T123	22		T124	14
pkt_types[PidTypeInToken]	invalid_ep[0xe]	991	1			T22	8		T123	22		T124	11
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1063	1			T22	12		T123	33		T124	16
pkt_types[PidTypeInToken]	endpoints[0x0]	4578	1			T31	1		T91	1		T22	9
pkt_types[PidTypeInToken]	endpoints[0x1]	5122	1			T31	1		T22	4		T98	1
pkt_types[PidTypeInToken]	endpoints[0x2]	4807	1			T29	1		T31	1		T32	1
pkt_types[PidTypeInToken]	endpoints[0x3]	4652	1			T29	4		T31	1		T22	10
pkt_types[PidTypeInToken]	endpoints[0x4]	4672	1			T40	1		T29	1		T30	1
pkt_types[PidTypeInToken]	endpoints[0x5]	5000	1			T29	1		T31	1		T33	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4946	1			T29	2		T31	1		T37	1
pkt_types[PidTypeInToken]	endpoints[0x7]	4656	1			T40	3		T28	4		T29	2
pkt_types[PidTypeInToken]	endpoints[0x8]	5279	1			T31	1		T52	1		T22	5
pkt_types[PidTypeInToken]	endpoints[0x9]	5010	1			T31	1		T163	1		T7	1
pkt_types[PidTypeInToken]	endpoints[0xa]	4859	1			T31	1		T38	1		T50	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4704	1			T40	3		T29	1		T31	1