Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	272	1			T217	4		T218	7		T219	7
all_values[1]	272	1			T217	4		T218	7		T219	7
all_values[2]	272	1			T217	4		T218	7		T219	7
all_values[3]	272	1			T217	4		T218	7		T219	7
all_values[4]	272	1			T217	4		T218	7		T219	7
all_values[5]	272	1			T217	4		T218	7		T219	7
all_values[6]	272	1			T217	4		T218	7		T219	7
all_values[7]	272	1			T217	4		T218	7		T219	7
all_values[8]	272	1			T217	4		T218	7		T219	7
all_values[9]	272	1			T217	4		T218	7		T219	7
all_values[10]	272	1			T217	4		T218	7		T219	7
all_values[11]	272	1			T217	4		T218	7		T219	7
all_values[12]	272	1			T217	4		T218	7		T219	7
all_values[13]	272	1			T217	4		T218	7		T219	7
all_values[14]	272	1			T217	4		T218	7		T219	7
all_values[15]	272	1			T217	4		T218	7		T219	7
all_values[16]	272	1			T217	4		T218	7		T219	7
all_values[17]	272	1			T217	4		T218	7		T219	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6545

1

T217

90

T218

171

T219

157

auto[1]

2159

1

T217

38

T218

53

T219

67

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5986

1

T217

85

T218

154

T219

155

auto[1]

2718

1

T217

43

T218

70

T219

69

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5181

1

T217

79

T218

128

T219

135

auto[1]

3523

1

T217

49

T218

96

T219

89

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	108	1			T217	2		T218	2		T333	3
all_values[0]	auto[0]	auto[1]	auto[0]	70	1			T218	2		T219	5		T334	3
all_values[0]	auto[1]	auto[0]	auto[1]	57	1			T218	2		T333	1		T334	1
all_values[0]	auto[1]	auto[1]	auto[1]	37	1			T217	2		T218	1		T219	2
all_values[1]	auto[0]	auto[0]	auto[0]	106	1			T217	2		T218	1		T219	5
all_values[1]	auto[0]	auto[1]	auto[0]	57	1			T217	1		T218	2		T219	1
all_values[1]	auto[1]	auto[0]	auto[1]	56	1			T218	2		T219	1		T333	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1			T217	1		T218	2		T334	1
all_values[2]	auto[0]	auto[0]	auto[0]	30	1			T219	3		T335	2		T336	1
all_values[2]	auto[0]	auto[0]	auto[1]	48	1			T218	1		T219	1		T333	2
all_values[2]	auto[0]	auto[1]	auto[0]	41	1			T218	2		T219	1		T335	2
all_values[2]	auto[0]	auto[1]	auto[1]	45	1			T217	3		T218	1		T219	1
all_values[2]	auto[1]	auto[0]	auto[1]	70	1			T218	2		T219	1		T333	1
all_values[2]	auto[1]	auto[1]	auto[1]	38	1			T217	1		T218	1		T333	1
all_values[3]	auto[0]	auto[0]	auto[0]	58	1			T218	2		T219	2		T333	3
all_values[3]	auto[0]	auto[0]	auto[1]	22	1			T217	1		T218	1		T334	1
all_values[3]	auto[0]	auto[1]	auto[0]	50	1			T217	2		T218	1		T219	2
all_values[3]	auto[0]	auto[1]	auto[1]	25	1			T219	1		T335	1		T336	2
all_values[3]	auto[1]	auto[0]	auto[1]	71	1			T218	3		T219	1		T334	2
all_values[3]	auto[1]	auto[1]	auto[1]	46	1			T217	1		T219	1		T333	1
all_values[4]	auto[0]	auto[0]	auto[0]	53	1			T219	2		T334	2		T335	2
all_values[4]	auto[0]	auto[0]	auto[1]	31	1			T218	1		T300	1		T337	1
all_values[4]	auto[0]	auto[1]	auto[0]	46	1			T217	1		T338	2		T335	2
all_values[4]	auto[0]	auto[1]	auto[1]	20	1			T217	2		T218	1		T333	1
all_values[4]	auto[1]	auto[0]	auto[1]	65	1			T218	5		T219	4		T333	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1			T217	1		T219	1		T333	1
all_values[5]	auto[0]	auto[0]	auto[0]	57	1			T217	1		T334	3		T335	1
all_values[5]	auto[0]	auto[0]	auto[1]	37	1			T219	2		T333	1		T334	2
all_values[5]	auto[0]	auto[1]	auto[0]	57	1			T217	1		T334	1		T338	4
all_values[5]	auto[0]	auto[1]	auto[1]	21	1			T218	3		T219	3		T300	1
all_values[5]	auto[1]	auto[0]	auto[1]	67	1			T217	1		T218	2		T219	1
all_values[5]	auto[1]	auto[1]	auto[1]	33	1			T217	1		T218	2		T219	1
all_values[6]	auto[0]	auto[0]	auto[0]	67	1			T217	1		T218	4		T219	2
all_values[6]	auto[0]	auto[0]	auto[1]	27	1			T219	2		T333	1		T338	1
all_values[6]	auto[0]	auto[1]	auto[0]	49	1			T217	1		T218	2		T333	2
all_values[6]	auto[0]	auto[1]	auto[1]	24	1			T219	1		T335	1		T336	1
all_values[6]	auto[1]	auto[0]	auto[1]	62	1			T217	1		T219	1		T333	1
all_values[6]	auto[1]	auto[1]	auto[1]	43	1			T217	1		T218	1		T219	1
all_values[7]	auto[0]	auto[0]	auto[0]	98	1			T217	2		T218	1		T333	2
all_values[7]	auto[0]	auto[1]	auto[0]	56	1			T218	1		T219	2		T333	2
all_values[7]	auto[1]	auto[0]	auto[1]	64	1			T217	1		T218	1		T219	2
all_values[7]	auto[1]	auto[1]	auto[1]	54	1			T217	1		T218	4		T219	3
all_values[8]	auto[0]	auto[0]	auto[0]	89	1			T217	1		T218	4		T219	1
all_values[8]	auto[0]	auto[1]	auto[0]	60	1			T217	2		T218	1		T219	2
all_values[8]	auto[1]	auto[0]	auto[1]	72	1			T218	2		T219	3		T333	1
all_values[8]	auto[1]	auto[1]	auto[1]	51	1			T217	1		T219	1		T334	4
all_values[9]	auto[0]	auto[0]	auto[0]	53	1			T218	2		T338	1		T335	1
all_values[9]	auto[0]	auto[0]	auto[1]	26	1			T217	1		T219	1		T333	1
all_values[9]	auto[0]	auto[1]	auto[0]	45	1			T217	1		T219	2		T333	2
all_values[9]	auto[0]	auto[1]	auto[1]	24	1			T218	1		T338	1		T336	2
all_values[9]	auto[1]	auto[0]	auto[1]	62	1			T217	2		T218	1		T219	1
all_values[9]	auto[1]	auto[1]	auto[1]	62	1			T218	3		T219	3		T334	3
all_values[10]	auto[0]	auto[0]	auto[0]	60	1			T218	1		T219	1		T333	2
all_values[10]	auto[0]	auto[0]	auto[1]	28	1			T217	1		T218	1		T219	1
all_values[10]	auto[0]	auto[1]	auto[0]	52	1			T217	1		T218	3		T219	2
all_values[10]	auto[0]	auto[1]	auto[1]	27	1			T334	2		T335	1		T339	1
all_values[10]	auto[1]	auto[0]	auto[1]	58	1			T217	2		T219	1		T333	1
all_values[10]	auto[1]	auto[1]	auto[1]	47	1			T218	2		T219	2		T334	1
all_values[11]	auto[0]	auto[0]	auto[0]	60	1			T218	5		T219	1		T338	2
all_values[11]	auto[0]	auto[0]	auto[1]	24	1			T217	1		T333	1		T334	3
all_values[11]	auto[0]	auto[1]	auto[0]	55	1			T217	2		T218	2		T338	1
all_values[11]	auto[0]	auto[1]	auto[1]	32	1			T219	4		T333	1		T334	2
all_values[11]	auto[1]	auto[0]	auto[1]	45	1			T217	1		T219	1		T333	2
all_values[11]	auto[1]	auto[1]	auto[1]	56	1			T219	1		T334	1		T335	1
all_values[12]	auto[0]	auto[0]	auto[0]	68	1			T217	2		T218	1		T333	4
all_values[12]	auto[0]	auto[0]	auto[1]	29	1			T218	1		T338	1		T336	1
all_values[12]	auto[0]	auto[1]	auto[0]	49	1			T218	1		T219	2		T334	3
all_values[12]	auto[0]	auto[1]	auto[1]	18	1			T218	1		T219	1		T335	1
all_values[12]	auto[1]	auto[0]	auto[1]	56	1			T217	2		T218	3		T219	1
all_values[12]	auto[1]	auto[1]	auto[1]	52	1			T219	3		T334	2		T336	2
all_values[13]	auto[0]	auto[0]	auto[0]	54	1			T218	3		T219	2		T333	1
all_values[13]	auto[0]	auto[0]	auto[1]	33	1			T217	1		T333	1		T336	1
all_values[13]	auto[0]	auto[1]	auto[0]	41	1			T218	1		T219	4		T334	1
all_values[13]	auto[0]	auto[1]	auto[1]	30	1			T217	2		T334	1		T299	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1			T217	1		T218	2		T219	1
all_values[13]	auto[1]	auto[1]	auto[1]	48	1			T218	1		T334	1		T338	1
all_values[14]	auto[0]	auto[0]	auto[0]	70	1			T217	1		T218	1		T333	4
all_values[14]	auto[0]	auto[0]	auto[1]	22	1			T217	1		T218	1		T219	1
all_values[14]	auto[0]	auto[1]	auto[0]	49	1			T218	2		T219	5		T338	2
all_values[14]	auto[0]	auto[1]	auto[1]	20	1			T218	1		T335	1		T339	1
all_values[14]	auto[1]	auto[0]	auto[1]	62	1			T217	2		T218	2		T334	5
all_values[14]	auto[1]	auto[1]	auto[1]	49	1			T219	1		T338	2		T335	2
all_values[15]	auto[0]	auto[0]	auto[0]	65	1			T219	3		T333	1		T338	2
all_values[15]	auto[0]	auto[0]	auto[1]	22	1			T334	1		T338	1		T335	3
all_values[15]	auto[0]	auto[1]	auto[0]	46	1			T217	1		T218	2		T219	1
all_values[15]	auto[0]	auto[1]	auto[1]	29	1			T217	1		T218	1		T219	1
all_values[15]	auto[1]	auto[0]	auto[1]	54	1			T217	1		T218	2		T334	1
all_values[15]	auto[1]	auto[1]	auto[1]	56	1			T217	1		T218	2		T219	2
all_values[16]	auto[0]	auto[0]	auto[0]	46	1			T218	2		T219	2		T334	1
all_values[16]	auto[0]	auto[0]	auto[1]	37	1			T217	1		T218	2		T219	1
all_values[16]	auto[0]	auto[1]	auto[0]	42	1			T219	1		T339	2		T340	2
all_values[16]	auto[0]	auto[1]	auto[1]	23	1			T217	1		T335	2		T336	1
all_values[16]	auto[1]	auto[0]	auto[1]	71	1			T218	2		T219	3		T333	2
all_values[16]	auto[1]	auto[1]	auto[1]	53	1			T217	2		T218	1		T333	1
all_values[17]	auto[0]	auto[0]	auto[0]	88	1			T217	1		T218	3		T219	1
all_values[17]	auto[0]	auto[1]	auto[0]	83	1			T217	3		T218	2		T219	2
all_values[17]	auto[1]	auto[0]	auto[1]	63	1			T218	2		T219	3		T333	1
all_values[17]	auto[1]	auto[1]	auto[1]	38	1			T219	1		T334	1		T335	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal