Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	84232	1			T1	4		T2	6		T3	3
all_values[1]	84232	1			T1	4		T2	6		T3	3
all_values[2]	84232	1			T1	4		T2	6		T3	3
all_values[3]	84232	1			T1	4		T2	6		T3	3
all_values[4]	84232	1			T1	4		T2	6		T3	3
all_values[5]	84232	1			T1	4		T2	6		T3	3
all_values[6]	84232	1			T1	4		T2	6		T3	3
all_values[7]	84232	1			T1	4		T2	6		T3	3
all_values[8]	84232	1			T1	4		T2	6		T3	3
all_values[9]	84232	1			T1	4		T2	6		T3	3
all_values[10]	84232	1			T1	4		T2	6		T3	3
all_values[11]	84232	1			T1	4		T2	6		T3	3
all_values[12]	84232	1			T1	4		T2	6		T3	3
all_values[13]	84232	1			T1	4		T2	6		T3	3
all_values[14]	84232	1			T1	4		T2	6		T3	3
all_values[15]	84232	1			T1	4		T2	6		T3	3
all_values[16]	84232	1			T1	4		T2	6		T3	3
all_values[17]	84232	1			T1	4		T2	6		T3	3

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2685819

1

T1

128

T2

189

T3

96

auto[1]

9605

1

T2

3

T16

5

T17

2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2243400

1

T1

110

T2

177

T3

85

auto[1]

452024

1

T1

18

T2

15

T3

11

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	55778	1			T1	3		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	25119	1			T1	1		T2	3		T23	2
all_values[0]	auto[1]	auto[0]	3230	1			T44	3		T45	3		T46	3
all_values[0]	auto[1]	auto[1]	105	1			T429	1		T430	1		T431	1
all_values[1]	auto[0]	auto[0]	79826	1			T1	4		T2	6		T3	3
all_values[1]	auto[0]	auto[1]	3034	1			T18	2		T21	2		T32	1
all_values[1]	auto[1]	auto[0]	510	1			T28	2		T7	1		T33	2
all_values[1]	auto[1]	auto[1]	862	1			T28	12		T7	1		T33	1
all_values[2]	auto[0]	auto[0]	4397	1			T1	1		T2	5		T3	1
all_values[2]	auto[0]	auto[1]	79582	1			T1	3		T2	1		T3	2
all_values[2]	auto[1]	auto[0]	134	1			T19	1		T62	1		T63	1
all_values[2]	auto[1]	auto[1]	119	1			T19	1		T62	1		T63	1
all_values[3]	auto[0]	auto[0]	82366	1			T1	4		T2	6		T3	3
all_values[3]	auto[0]	auto[1]	303	1			T43	1		T64	1		T65	1
all_values[3]	auto[1]	auto[0]	1494	1			T43	1406		T231	1		T326	4
all_values[3]	auto[1]	auto[1]	69	1			T43	1		T230	1		T232	1
all_values[4]	auto[0]	auto[0]	4363	1			T1	1		T2	5		T3	1
all_values[4]	auto[0]	auto[1]	79688	1			T1	3		T2	1		T3	2
all_values[4]	auto[1]	auto[0]	84	1			T42	1		T233	5		T231	1
all_values[4]	auto[1]	auto[1]	97	1			T42	1		T230	1		T232	3
all_values[5]	auto[0]	auto[0]	83732	1			T1	4		T2	6		T3	2
all_values[5]	auto[0]	auto[1]	350	1			T3	1		T7	1		T58	1
all_values[5]	auto[1]	auto[0]	90	1			T230	1		T232	3		T326	1
all_values[5]	auto[1]	auto[1]	60	1			T233	1		T230	2		T232	4
all_values[6]	auto[0]	auto[0]	83793	1			T1	4		T2	6		T3	3
all_values[6]	auto[0]	auto[1]	214	1			T7	1		T67	1		T65	1
all_values[6]	auto[1]	auto[0]	107	1			T233	3		T230	1		T232	1
all_values[6]	auto[1]	auto[1]	118	1			T66	1		T68	1		T69	1
all_values[7]	auto[0]	auto[0]	28591	1			T2	1		T3	2		T17	3
all_values[7]	auto[0]	auto[1]	55448	1			T1	4		T2	2		T3	1
all_values[7]	auto[1]	auto[0]	134	1			T2	2		T47	2		T48	2
all_values[7]	auto[1]	auto[1]	59	1			T2	1		T47	1		T48	1
all_values[8]	auto[0]	auto[0]	83335	1			T1	4		T2	6		T3	3
all_values[8]	auto[0]	auto[1]	224	1			T23	2		T378	2		T396	2
all_values[8]	auto[1]	auto[0]	604	1			T51	10		T52	10		T53	10
all_values[8]	auto[1]	auto[1]	69	1			T53	1		T54	1		T55	1
all_values[9]	auto[0]	auto[0]	83971	1			T1	4		T2	6		T3	3
all_values[9]	auto[0]	auto[1]	67	1			T233	1		T232	1		T325	4
all_values[9]	auto[1]	auto[0]	116	1			T16	3		T60	3		T61	3
all_values[9]	auto[1]	auto[1]	78	1			T16	2		T60	2		T61	2
all_values[10]	auto[0]	auto[0]	83670	1			T1	4		T2	6		T3	3
all_values[10]	auto[0]	auto[1]	412	1			T21	1		T34	2		T59	1
all_values[10]	auto[1]	auto[0]	88	1			T233	3		T230	3		T231	1
all_values[10]	auto[1]	auto[1]	62	1			T232	1		T326	1		T327	1
all_values[11]	auto[0]	auto[0]	83311	1			T1	4		T2	6		T3	3
all_values[11]	auto[0]	auto[1]	673	1			T17	1		T30	4		T70	4
all_values[11]	auto[1]	auto[0]	152	1			T74	1		T75	1		T76	1
all_values[11]	auto[1]	auto[1]	96	1			T74	1		T75	1		T76	1
all_values[12]	auto[0]	auto[0]	83848	1			T1	4		T2	6		T3	3
all_values[12]	auto[0]	auto[1]	201	1			T79	1		T81	1		T82	1
all_values[12]	auto[1]	auto[0]	121	1			T77	2		T78	2		T80	2
all_values[12]	auto[1]	auto[1]	62	1			T77	1		T78	1		T80	1
all_values[13]	auto[0]	auto[0]	83911	1			T1	4		T2	6		T3	3
all_values[13]	auto[0]	auto[1]	76	1			T79	1		T81	1		T82	1
all_values[13]	auto[1]	auto[0]	136	1			T17	1		T83	1		T84	1
all_values[13]	auto[1]	auto[1]	109	1			T17	1		T83	1		T84	1
all_values[14]	auto[0]	auto[0]	16851	1			T1	4		T2	6		T3	1
all_values[14]	auto[0]	auto[1]	67237	1			T3	2		T19	1		T7	2
all_values[14]	auto[1]	auto[0]	84	1			T233	1		T230	1		T231	2
all_values[14]	auto[1]	auto[1]	60	1			T233	3		T230	3		T231	2
all_values[15]	auto[0]	auto[0]	4422	1			T1	1		T2	5		T3	1
all_values[15]	auto[0]	auto[1]	79647	1			T1	3		T2	1		T3	2
all_values[15]	auto[1]	auto[0]	100	1			T233	1		T230	5		T231	1
all_values[15]	auto[1]	auto[1]	63	1			T232	1		T326	3		T325	2
all_values[16]	auto[0]	auto[0]	83224	1			T1	4		T2	6		T3	3
all_values[16]	auto[0]	auto[1]	838	1			T21	1		T72	1		T73	1
all_values[16]	auto[1]	auto[0]	99	1			T30	4		T70	4		T71	4
all_values[16]	auto[1]	auto[1]	71	1			T30	4		T70	4		T71	4
all_values[17]	auto[0]	auto[0]	27358	1			T3	2		T16	5		T20	2
all_values[17]	auto[0]	auto[1]	56711	1			T1	4		T2	6		T3	1
all_values[17]	auto[1]	auto[0]	122	1			T56	2		T57	2		T233	3
all_values[17]	auto[1]	auto[1]	41	1			T56	1		T57	1		T233	1