Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.40 98.22 96.03 97.44 94.92 98.38 98.17 98.64


Total tests in report: 3905
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
67.89 67.89 84.42 84.42 68.22 68.22 81.66 81.66 49.15 49.15 79.14 79.14 90.85 90.85 21.81 21.81 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3106566934
73.27 5.38 90.14 5.73 74.02 5.80 84.54 2.88 62.71 13.56 84.61 5.47 92.89 2.03 23.98 2.17 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.1655286630
77.86 4.59 92.99 2.84 82.28 8.25 85.82 1.28 64.41 1.69 92.45 7.84 92.89 0.00 34.21 10.23 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.329731943
80.27 2.41 94.07 1.08 84.63 2.35 87.21 1.39 64.41 0.00 94.65 2.20 93.29 0.41 43.62 9.41 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.1304939885
82.37 2.10 94.77 0.70 84.75 0.12 89.13 1.92 64.41 0.00 94.65 0.00 93.29 0.00 55.57 11.95 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.1303679156
83.65 1.28 94.98 0.21 86.49 1.74 89.13 0.00 69.49 5.08 94.86 0.21 93.29 0.00 57.29 1.72 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.1552417782
84.83 1.19 96.11 1.14 87.01 0.52 90.62 1.49 69.49 0.00 94.94 0.08 95.73 2.44 59.91 2.62 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.764553065
85.70 0.87 96.32 0.21 88.18 1.17 91.04 0.43 69.49 0.00 95.69 0.75 95.73 0.00 63.44 3.53 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2598449207
86.43 0.74 96.34 0.02 88.18 0.00 91.04 0.00 74.58 5.08 95.73 0.04 95.73 0.00 63.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.3643581630
86.99 0.55 96.47 0.13 88.23 0.05 91.26 0.21 77.97 3.39 95.81 0.08 95.73 0.00 63.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/5.usbdev_aon_wake_disconnect.2707263722
87.53 0.55 96.64 0.17 88.32 0.10 91.26 0.00 81.36 3.39 95.98 0.17 95.73 0.00 63.44 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2653688923
88.07 0.54 96.64 0.00 88.37 0.05 94.24 2.99 81.36 0.00 95.98 0.00 95.93 0.20 63.98 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2476977434
88.59 0.52 96.99 0.34 88.44 0.07 95.10 0.85 83.05 1.69 96.02 0.04 95.93 0.00 64.62 0.63 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.3922615181
89.06 0.47 97.73 0.74 89.58 1.14 95.31 0.21 83.05 0.00 97.18 1.16 95.93 0.00 64.62 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.902546386
89.52 0.46 97.73 0.00 89.58 0.00 95.74 0.43 83.05 0.00 97.18 0.00 95.93 0.00 67.42 2.81 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.2903964770
89.94 0.42 97.73 0.00 90.34 0.76 95.74 0.00 83.05 0.00 97.22 0.04 96.34 0.41 69.14 1.72 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.389791261
90.34 0.41 97.76 0.04 91.06 0.71 95.74 0.00 84.75 1.69 97.26 0.04 96.34 0.00 69.50 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.527958098
90.63 0.29 97.86 0.09 91.53 0.48 95.74 0.00 84.75 0.00 97.64 0.37 96.34 0.00 70.59 1.09 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.3164149782
90.92 0.29 97.86 0.00 91.72 0.19 95.74 0.00 84.75 0.00 97.72 0.08 96.54 0.20 72.13 1.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.272160079
91.19 0.27 97.86 0.00 91.72 0.00 95.95 0.21 86.44 1.69 97.72 0.00 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/6.usbdev_tx_rx_disruption.1004010163
91.45 0.26 97.88 0.02 91.77 0.05 95.95 0.00 88.14 1.69 97.76 0.04 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.2814024567
91.71 0.25 97.91 0.04 91.77 0.00 95.95 0.00 89.83 1.69 97.80 0.04 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.116166794
91.95 0.25 97.91 0.00 91.79 0.02 95.95 0.00 91.53 1.69 97.80 0.00 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/28.usbdev_tx_rx_disruption.3180755862
92.19 0.24 97.91 0.00 91.79 0.00 95.95 0.00 93.22 1.69 97.80 0.00 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/102.usbdev_tx_rx_disruption.844066269
92.44 0.24 97.91 0.00 91.79 0.00 95.95 0.00 94.92 1.69 97.80 0.00 96.54 0.00 72.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/106.usbdev_tx_rx_disruption.2026676906
92.66 0.23 97.97 0.06 92.89 1.09 95.95 0.00 94.92 0.00 97.88 0.08 96.54 0.00 72.49 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.3561073702
92.87 0.20 97.97 0.00 92.96 0.07 95.95 0.00 94.92 0.00 97.88 0.00 96.54 0.00 73.85 1.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_device_address.3076112469
93.07 0.20 97.97 0.00 92.96 0.00 95.95 0.00 94.92 0.00 97.88 0.00 97.97 1.42 73.85 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.417220915
93.22 0.15 97.97 0.00 93.13 0.17 96.16 0.21 94.92 0.00 97.93 0.04 97.97 0.00 74.48 0.63 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.2239611508
93.36 0.14 97.97 0.00 93.13 0.00 96.16 0.00 94.92 0.00 97.93 0.00 97.97 0.00 75.48 1.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.2789078497
93.51 0.14 97.97 0.00 93.13 0.00 96.16 0.00 94.92 0.00 97.93 0.00 97.97 0.00 76.47 1.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/8.usbdev_device_address.4121035485
93.63 0.13 97.97 0.00 93.13 0.00 96.16 0.00 94.92 0.00 97.93 0.00 97.97 0.00 77.38 0.90 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.2101301976
93.75 0.12 97.97 0.00 93.39 0.26 96.48 0.32 94.92 0.00 98.09 0.17 97.97 0.00 77.47 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.3431528859
93.87 0.12 97.97 0.00 93.39 0.00 96.48 0.00 94.92 0.00 98.09 0.00 97.97 0.00 78.28 0.81 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/195.usbdev_endpoint_types.4221648709
93.99 0.12 97.97 0.00 93.39 0.00 96.48 0.00 94.92 0.00 98.09 0.00 97.97 0.00 79.10 0.81 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/77.usbdev_endpoint_types.1439538529
94.10 0.11 97.97 0.00 93.43 0.05 96.70 0.21 94.92 0.00 98.09 0.00 97.97 0.00 79.64 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.3422587203
94.21 0.10 97.97 0.00 93.43 0.00 96.70 0.00 94.92 0.00 98.09 0.00 97.97 0.00 80.36 0.72 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/45.usbdev_endpoint_types.1446426137
94.31 0.10 97.97 0.00 93.48 0.05 96.91 0.21 94.92 0.00 98.09 0.00 97.97 0.00 80.81 0.45 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3149020043
94.40 0.09 97.97 0.00 93.48 0.00 96.91 0.00 94.92 0.00 98.09 0.00 97.97 0.00 81.45 0.63 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/158.usbdev_endpoint_types.1202444321
94.49 0.09 97.97 0.00 93.48 0.00 96.91 0.00 94.92 0.00 98.09 0.00 97.97 0.00 82.08 0.63 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/61.usbdev_endpoint_types.1288928925
94.58 0.09 97.97 0.00 93.53 0.05 97.12 0.21 94.92 0.00 98.09 0.00 97.97 0.00 82.44 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.1102289346
94.66 0.09 98.01 0.04 93.65 0.12 97.12 0.00 94.92 0.00 98.18 0.08 97.97 0.00 82.81 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.3985214491
94.74 0.08 98.01 0.00 93.65 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 83.35 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/21.usbdev_endpoint_types.66100232
94.82 0.08 98.01 0.00 93.65 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 83.89 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/25.usbdev_data_toggle_restore.641012410
94.90 0.08 98.01 0.00 93.65 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 84.43 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/35.usbdev_endpoint_types.709154663
94.97 0.08 98.01 0.00 93.65 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 84.98 0.54 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/83.usbdev_endpoint_types.3992237339
95.05 0.07 98.01 0.00 93.70 0.05 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 85.43 0.45 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/22.usbdev_device_address.3832964246
95.11 0.07 98.01 0.00 93.82 0.12 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 85.79 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.785631760
95.18 0.07 98.01 0.00 93.84 0.02 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 86.24 0.45 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.2301925368
95.25 0.06 98.01 0.00 93.84 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.00 86.70 0.45 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/117.usbdev_endpoint_types.408304071
95.31 0.06 98.03 0.02 93.86 0.02 97.12 0.00 94.92 0.00 98.22 0.04 97.97 0.00 87.06 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/7.usbdev_fifo_levels.1353933049
95.36 0.05 98.03 0.00 94.03 0.17 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.20 87.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/4.usbdev_stress_usb_traffic.2731127531
95.41 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 87.42 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.2976342737
95.47 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 87.78 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3899546638
95.52 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 88.14 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/13.usbdev_endpoint_types.2508739961
95.57 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 88.51 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/159.usbdev_endpoint_types.1981152916
95.62 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 88.87 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/160.usbdev_endpoint_types.1811956990
95.67 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 89.23 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/191.usbdev_endpoint_types.59699238
95.72 0.05 98.03 0.00 94.03 0.00 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 89.59 0.36 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/46.usbdev_endpoint_types.1012409913
95.78 0.05 98.09 0.06 94.05 0.02 97.12 0.00 94.92 0.00 98.22 0.00 98.17 0.00 89.86 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.3295230125
95.82 0.05 98.14 0.06 94.12 0.07 97.33 0.21 94.92 0.00 98.22 0.00 98.17 0.00 89.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.1940016384
95.87 0.05 98.14 0.00 94.46 0.33 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 89.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.2401912666
95.91 0.04 98.14 0.00 94.48 0.02 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 90.14 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/20.usbdev_device_address.4285825335
95.95 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 90.41 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.4134535709
95.99 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 90.68 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.878050004
96.03 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 90.95 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/122.usbdev_endpoint_types.1429524950
96.07 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 91.22 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/5.usbdev_max_usb_traffic.3491684734
96.11 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 91.49 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/8.usbdev_endpoint_types.498205693
96.15 0.04 98.14 0.00 94.48 0.00 97.33 0.00 94.92 0.00 98.22 0.00 98.17 0.00 91.76 0.27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.1779363052
96.18 0.04 98.20 0.06 94.51 0.02 97.33 0.00 94.92 0.00 98.30 0.08 98.17 0.00 91.86 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/13.usbdev_fifo_levels.1280891447
96.21 0.03 98.20 0.00 94.70 0.19 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 91.86 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.59155813
96.24 0.03 98.20 0.00 94.79 0.10 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 91.95 0.09 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.3834201848
96.26 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 92.13 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.2107509621
96.29 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 92.31 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.831682248
96.31 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 92.49 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2039799697
96.34 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 92.67 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/121.usbdev_endpoint_types.2919670954
96.37 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 92.85 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/131.usbdev_endpoint_types.1242835874
96.39 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.03 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/174.usbdev_endpoint_types.4209334717
96.42 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.21 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/185.usbdev_endpoint_types.3142302406
96.44 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.39 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/23.usbdev_endpoint_types.1505193645
96.47 0.03 98.20 0.00 94.79 0.00 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.57 0.18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_types.2289228101
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97.38 0.01 98.22 0.00 95.88 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/15.usbdev_nak_trans.324316593
97.38 0.01 98.22 0.00 95.91 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/16.usbdev_nak_trans.345334343
97.39 0.01 98.22 0.00 95.93 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/17.usbdev_nak_trans.387338478
97.39 0.01 98.22 0.00 95.96 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/17.usbdev_phy_pins_sense.2545030837
97.39 0.01 98.22 0.00 95.98 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/19.usbdev_nak_trans.2399705322
97.40 0.01 98.22 0.00 96.00 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/20.usbdev_nak_trans.4111162274
97.40 0.01 98.22 0.00 96.03 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.64 0.00 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/27.usbdev_nak_trans.135432797

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.3511082998
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3838216490
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.4053341889
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2557760865
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.1800641551
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.3048794735
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.53950919
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2724846035
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.3503618494
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.3274122303
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3026986938
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3587191141
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.1453259622
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.3645471799
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.4244553685
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.1413390729
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2818743614
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.2038265202
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_intg_err.2523126497
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.474731331
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.769188581
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4233527725
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.752255422
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.775155898
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2080561397
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.2846067351
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.961039038
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.4139895330
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.2080557867
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.731599201
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.4100152963
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2388453763
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.2795934612
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.3394543597
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3485497372
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.2131840314
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.854548138
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3710858670
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.1421500116
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.1899908653
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3739931792
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.2045808398
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.3641085134
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3781635141
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.1523976364
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.3210105765
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.1806923182
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.3709550360
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.386113435
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3158398074
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.1153313363
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.662634363
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1655787374
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.1983099458
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.3165659103
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.4112261658
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.2493454277
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.2359400592
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2106729276
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.571331724
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.2107948121
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.4262908518
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.3862640142
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.1481557685
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3556335840
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.498466872
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.1791255454
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.588996541
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.426915711
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3341404398
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.4208566006
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.2209517734
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.2375939495
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2294849119
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.1181978273
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.393999470
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.3800187642
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.2133116510
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.3950974934
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3535766086
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.4124466092
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.602434025
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.2975409450
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.396366390
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.1839577170
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.3652313023
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.2579744403
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.2581616167
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.509010521
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.3665108302
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.3544199895
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.3069506353
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2716495587
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2324796896
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3726934831
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.1741705125
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.2013935969
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.3598835381
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.3665442272
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1348324673
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.2418494350
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.1004208118
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.1011623585
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.3508513961
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.1343612595
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.2184857888
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.2052883556
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.3702938697
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.3495669260
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.3650203250
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.2641985695
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.4028089286
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1442097771
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1225017785
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.228061296
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.2151117636
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.1243623630
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.4293538752
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.458842853
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.309284723
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.315944776
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.1259864284
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.1453146473
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.787689052
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.1071693487
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.3651880227
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.489383371
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.611336328
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.1061494660
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.694385754
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.2787648953
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.1963228105
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2743523845
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/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.656667803
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Total test records in report: 3905
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.2974423759 Aug 29 03:27:21 AM UTC 24 Aug 29 03:27:24 AM UTC 24 152852892 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.2330638431 Aug 29 03:27:22 AM UTC 24 Aug 29 03:27:25 AM UTC 24 179998227 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.122611325 Aug 29 03:27:17 AM UTC 24 Aug 29 03:27:25 AM UTC 24 4005166166 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.59155813 Aug 29 03:27:23 AM UTC 24 Aug 29 03:27:26 AM UTC 24 146385917 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.3422587203 Aug 29 03:27:25 AM UTC 24 Aug 29 03:27:27 AM UTC 24 155633485 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3672600693 Aug 29 03:27:26 AM UTC 24 Aug 29 03:27:29 AM UTC 24 391837265 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.3922615181 Aug 29 03:27:29 AM UTC 24 Aug 29 03:27:32 AM UTC 24 148123803 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.4163258821 Aug 29 03:27:28 AM UTC 24 Aug 29 03:27:32 AM UTC 24 479376110 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.3106566934 Aug 29 03:27:26 AM UTC 24 Aug 29 03:27:32 AM UTC 24 1078478620 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_enable.1040322668 Aug 29 03:27:32 AM UTC 24 Aug 29 03:27:34 AM UTC 24 42667036 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.234477877 Aug 29 03:27:33 AM UTC 24 Aug 29 03:27:37 AM UTC 24 312053026 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.3164149782 Aug 29 03:27:33 AM UTC 24 Aug 29 03:27:37 AM UTC 24 440767199 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.1682606989 Aug 29 03:27:32 AM UTC 24 Aug 29 03:27:38 AM UTC 24 915944900 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.1304939885 Aug 29 03:27:35 AM UTC 24 Aug 29 03:27:42 AM UTC 24 505390863 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.1655286630 Aug 29 03:27:19 AM UTC 24 Aug 29 03:27:43 AM UTC 24 18557205320 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.1686535371 Aug 29 03:27:44 AM UTC 24 Aug 29 03:27:48 AM UTC 24 482348266 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.2000827213 Aug 29 03:27:46 AM UTC 24 Aug 29 03:27:49 AM UTC 24 146690327 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.3037940148 Aug 29 03:27:46 AM UTC 24 Aug 29 03:27:50 AM UTC 24 215343266 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.970078975 Aug 29 03:27:48 AM UTC 24 Aug 29 03:27:51 AM UTC 24 237340831 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.3558081232 Aug 29 03:27:49 AM UTC 24 Aug 29 03:27:53 AM UTC 24 239887180 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.3985214491 Aug 29 03:27:51 AM UTC 24 Aug 29 03:27:54 AM UTC 24 541333400 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.3735822116 Aug 29 03:27:53 AM UTC 24 Aug 29 03:27:55 AM UTC 24 205738764 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.527958098 Aug 29 03:27:28 AM UTC 24 Aug 29 03:27:59 AM UTC 24 1439619337 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.2068839264 Aug 29 03:27:27 AM UTC 24 Aug 29 03:28:01 AM UTC 24 3849203245 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.2616839061 Aug 29 03:27:59 AM UTC 24 Aug 29 03:28:02 AM UTC 24 241462052 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.1996883087 Aug 29 03:27:42 AM UTC 24 Aug 29 03:28:05 AM UTC 24 4196850179 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.1430301308 Aug 29 03:28:02 AM UTC 24 Aug 29 03:28:05 AM UTC 24 206763778 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.924222271 Aug 29 03:27:55 AM UTC 24 Aug 29 03:28:12 AM UTC 24 11111682483 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.1526261317 Aug 29 03:28:12 AM UTC 24 Aug 29 03:28:15 AM UTC 24 187840229 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.2162892162 Aug 29 03:28:12 AM UTC 24 Aug 29 03:28:15 AM UTC 24 185384943 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.3295230125 Aug 29 03:28:14 AM UTC 24 Aug 29 03:28:16 AM UTC 24 209504640 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2871752682 Aug 29 03:28:14 AM UTC 24 Aug 29 03:28:17 AM UTC 24 499559176 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.4075289048 Aug 29 03:28:16 AM UTC 24 Aug 29 03:28:18 AM UTC 24 158983102 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.3486362798 Aug 29 03:28:16 AM UTC 24 Aug 29 03:28:18 AM UTC 24 172670558 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.821497291 Aug 29 03:28:17 AM UTC 24 Aug 29 03:28:19 AM UTC 24 164564820 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.1498412175 Aug 29 03:28:17 AM UTC 24 Aug 29 03:28:19 AM UTC 24 167534884 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.91764166 Aug 29 03:27:44 AM UTC 24 Aug 29 03:28:20 AM UTC 24 2991232570 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2612845152 Aug 29 03:28:18 AM UTC 24 Aug 29 03:28:21 AM UTC 24 246854894 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.3431528859 Aug 29 03:28:19 AM UTC 24 Aug 29 03:28:22 AM UTC 24 219590931 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.4097552690 Aug 29 03:28:19 AM UTC 24 Aug 29 03:28:22 AM UTC 24 208616977 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.2373979163 Aug 29 03:28:20 AM UTC 24 Aug 29 03:28:23 AM UTC 24 201695156 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.1102289346 Aug 29 03:27:54 AM UTC 24 Aug 29 03:28:23 AM UTC 24 13519585787 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2653688923 Aug 29 03:28:20 AM UTC 24 Aug 29 03:28:23 AM UTC 24 334792132 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.902546386 Aug 29 03:28:22 AM UTC 24 Aug 29 03:28:24 AM UTC 24 47948724 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.2522172373 Aug 29 03:28:21 AM UTC 24 Aug 29 03:28:24 AM UTC 24 185662930 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2964415294 Aug 29 03:28:21 AM UTC 24 Aug 29 03:28:24 AM UTC 24 219773799 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.4134535709 Aug 29 03:28:23 AM UTC 24 Aug 29 03:28:25 AM UTC 24 168959251 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.3346140585 Aug 29 03:28:24 AM UTC 24 Aug 29 03:28:26 AM UTC 24 153762371 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.1405461642 Aug 29 03:28:24 AM UTC 24 Aug 29 03:28:26 AM UTC 24 180838495 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.1066911837 Aug 29 03:28:24 AM UTC 24 Aug 29 03:28:27 AM UTC 24 210285853 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.2039799697 Aug 29 03:27:30 AM UTC 24 Aug 29 03:28:27 AM UTC 24 5127704265 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.720713567 Aug 29 03:27:58 AM UTC 24 Aug 29 03:28:28 AM UTC 24 2099304450 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3149020043 Aug 29 03:28:26 AM UTC 24 Aug 29 03:28:28 AM UTC 24 138052730 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2598449207 Aug 29 03:28:02 AM UTC 24 Aug 29 03:28:28 AM UTC 24 2549851838 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.494953499 Aug 29 03:28:27 AM UTC 24 Aug 29 03:28:30 AM UTC 24 183175122 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.174924779 Aug 29 03:28:27 AM UTC 24 Aug 29 03:28:30 AM UTC 24 221098131 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.672680622 Aug 29 03:28:27 AM UTC 24 Aug 29 03:28:31 AM UTC 24 329970865 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.3899546638 Aug 29 03:28:27 AM UTC 24 Aug 29 03:28:31 AM UTC 24 374341305 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.535558124 Aug 29 03:28:29 AM UTC 24 Aug 29 03:28:31 AM UTC 24 173895062 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.861132247 Aug 29 03:28:29 AM UTC 24 Aug 29 03:28:31 AM UTC 24 195056576 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.3187917837 Aug 29 03:28:29 AM UTC 24 Aug 29 03:28:32 AM UTC 24 218136873 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.3050603733 Aug 29 03:28:31 AM UTC 24 Aug 29 03:28:33 AM UTC 24 182299801 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.2348658564 Aug 29 03:28:31 AM UTC 24 Aug 29 03:28:33 AM UTC 24 177939812 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.1911125567 Aug 29 03:27:20 AM UTC 24 Aug 29 03:28:35 AM UTC 24 24031298653 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.3039911314 Aug 29 03:28:32 AM UTC 24 Aug 29 03:28:36 AM UTC 24 551864961 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2476977434 Aug 29 03:28:32 AM UTC 24 Aug 29 03:28:36 AM UTC 24 681409825 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3672717088 Aug 29 03:28:34 AM UTC 24 Aug 29 03:28:37 AM UTC 24 39344750 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.3646302678 Aug 29 03:28:32 AM UTC 24 Aug 29 03:28:37 AM UTC 24 765246115 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.3409827347 Aug 29 03:28:37 AM UTC 24 Aug 29 03:28:39 AM UTC 24 134318265 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.1460983910 Aug 29 03:28:37 AM UTC 24 Aug 29 03:28:39 AM UTC 24 145077404 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.3185426856 Aug 29 03:28:37 AM UTC 24 Aug 29 03:28:39 AM UTC 24 182561403 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.4091945484 Aug 29 03:28:38 AM UTC 24 Aug 29 03:28:40 AM UTC 24 160883689 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.1227903044 Aug 29 03:28:38 AM UTC 24 Aug 29 03:28:42 AM UTC 24 537665892 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.2206243809 Aug 29 03:28:39 AM UTC 24 Aug 29 03:28:42 AM UTC 24 348557306 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.3432237682 Aug 29 03:28:43 AM UTC 24 Aug 29 03:28:45 AM UTC 24 175388038 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_enable.895392298 Aug 29 03:28:44 AM UTC 24 Aug 29 03:28:46 AM UTC 24 56691916 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.156404436 Aug 29 03:28:35 AM UTC 24 Aug 29 03:28:47 AM UTC 24 3427481789 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.1840941299 Aug 29 03:28:41 AM UTC 24 Aug 29 03:28:48 AM UTC 24 1377406567 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.3135217238 Aug 29 03:28:31 AM UTC 24 Aug 29 03:28:49 AM UTC 24 2349399385 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.2668849440 Aug 29 03:28:48 AM UTC 24 Aug 29 03:28:50 AM UTC 24 159128828 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.486657378 Aug 29 03:28:46 AM UTC 24 Aug 29 03:28:50 AM UTC 24 848734694 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.623780059 Aug 29 03:28:47 AM UTC 24 Aug 29 03:28:50 AM UTC 24 470165701 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.2922972913 Aug 29 03:28:49 AM UTC 24 Aug 29 03:28:53 AM UTC 24 251087059 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.329731943 Aug 29 03:27:26 AM UTC 24 Aug 29 03:28:54 AM UTC 24 34151543468 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.2814024567 Aug 29 03:28:25 AM UTC 24 Aug 29 03:28:59 AM UTC 24 20231091291 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.3875071035 Aug 29 03:28:24 AM UTC 24 Aug 29 03:29:02 AM UTC 24 5955565520 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.504659039 Aug 29 03:29:00 AM UTC 24 Aug 29 03:29:03 AM UTC 24 199658327 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.726847828 Aug 29 03:29:00 AM UTC 24 Aug 29 03:29:03 AM UTC 24 204630256 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.24314657 Aug 29 03:29:03 AM UTC 24 Aug 29 03:29:06 AM UTC 24 187853978 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.3364273840 Aug 29 03:29:04 AM UTC 24 Aug 29 03:29:06 AM UTC 24 231035026 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.2626905976 Aug 29 03:29:13 AM UTC 24 Aug 29 03:29:16 AM UTC 24 247715646 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.1695479134 Aug 29 03:28:25 AM UTC 24 Aug 29 03:29:17 AM UTC 24 10213554999 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.3820668178 Aug 29 03:29:16 AM UTC 24 Aug 29 03:29:19 AM UTC 24 193614584 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.272160079 Aug 29 03:28:23 AM UTC 24 Aug 29 03:29:19 AM UTC 24 18745223483 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.1984005188 Aug 29 03:28:06 AM UTC 24 Aug 29 03:29:20 AM UTC 24 2570300335 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.2168218840 Aug 29 03:29:07 AM UTC 24 Aug 29 03:29:22 AM UTC 24 5306157590 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.116166794 Aug 29 03:28:35 AM UTC 24 Aug 29 03:29:22 AM UTC 24 15461362648 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.190012470 Aug 29 03:29:21 AM UTC 24 Aug 29 03:29:24 AM UTC 24 147339229 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.2334564157 Aug 29 03:28:25 AM UTC 24 Aug 29 03:29:25 AM UTC 24 2434876688 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.3677368919 Aug 29 03:29:23 AM UTC 24 Aug 29 03:29:26 AM UTC 24 150065728 ps
T139 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2041880981 Aug 29 03:29:23 AM UTC 24 Aug 29 03:29:26 AM UTC 24 236674389 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.2375210260 Aug 29 03:29:24 AM UTC 24 Aug 29 03:29:27 AM UTC 24 157047993 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.772765418 Aug 29 03:29:26 AM UTC 24 Aug 29 03:29:28 AM UTC 24 215703215 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.4198584100 Aug 29 03:29:27 AM UTC 24 Aug 29 03:29:29 AM UTC 24 149911042 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.2449930442 Aug 29 03:29:27 AM UTC 24 Aug 29 03:29:30 AM UTC 24 157708483 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.2307566514 Aug 29 03:29:28 AM UTC 24 Aug 29 03:29:31 AM UTC 24 221019690 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.1738738514 Aug 29 03:29:29 AM UTC 24 Aug 29 03:29:32 AM UTC 24 202389683 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.2847209362 Aug 29 03:29:30 AM UTC 24 Aug 29 03:29:32 AM UTC 24 36819580 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.3003869171 Aug 29 03:29:30 AM UTC 24 Aug 29 03:29:33 AM UTC 24 154717152 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3849353784 Aug 29 03:28:06 AM UTC 24 Aug 29 03:29:33 AM UTC 24 2927748679 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.1962035529 Aug 29 03:29:33 AM UTC 24 Aug 29 03:29:36 AM UTC 24 214632390 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.4288747386 Aug 29 03:29:33 AM UTC 24 Aug 29 03:29:36 AM UTC 24 166528930 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.3613324655 Aug 29 03:29:33 AM UTC 24 Aug 29 03:29:36 AM UTC 24 192174596 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.2843677869 Aug 29 03:28:40 AM UTC 24 Aug 29 03:29:37 AM UTC 24 1715572549 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.2381924141 Aug 29 03:29:35 AM UTC 24 Aug 29 03:29:37 AM UTC 24 188445739 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.1659240213 Aug 29 03:29:03 AM UTC 24 Aug 29 03:29:40 AM UTC 24 4972884661 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.1221873583 Aug 29 03:29:38 AM UTC 24 Aug 29 03:29:40 AM UTC 24 161614720 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.3432918619 Aug 29 03:29:38 AM UTC 24 Aug 29 03:29:41 AM UTC 24 366607294 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.1552417782 Aug 29 03:27:56 AM UTC 24 Aug 29 03:29:42 AM UTC 24 3837834170 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.1324566977 Aug 29 03:29:40 AM UTC 24 Aug 29 03:29:43 AM UTC 24 166078985 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.1100295441 Aug 29 03:28:56 AM UTC 24 Aug 29 03:29:43 AM UTC 24 3218642364 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.1976313255 Aug 29 03:29:41 AM UTC 24 Aug 29 03:29:44 AM UTC 24 207886098 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.1644341032 Aug 29 03:29:41 AM UTC 24 Aug 29 03:29:44 AM UTC 24 355400279 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.892096288 Aug 29 03:29:12 AM UTC 24 Aug 29 03:29:44 AM UTC 24 2754002769 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.269276352 Aug 29 03:29:43 AM UTC 24 Aug 29 03:29:46 AM UTC 24 157852053 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.3324844240 Aug 29 03:29:44 AM UTC 24 Aug 29 03:29:46 AM UTC 24 157345594 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.3271227851 Aug 29 03:29:44 AM UTC 24 Aug 29 03:29:47 AM UTC 24 276649733 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.3326243401 Aug 29 03:29:45 AM UTC 24 Aug 29 03:29:48 AM UTC 24 254736453 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.1288960362 Aug 29 03:28:40 AM UTC 24 Aug 29 03:29:48 AM UTC 24 33094545674 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.3506486660 Aug 29 03:29:45 AM UTC 24 Aug 29 03:29:48 AM UTC 24 186018163 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.2601882040 Aug 29 03:29:17 AM UTC 24 Aug 29 03:29:48 AM UTC 24 2587703137 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.1940016384 Aug 29 03:29:49 AM UTC 24 Aug 29 03:29:52 AM UTC 24 32967496 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.121545669 Aug 29 03:29:46 AM UTC 24 Aug 29 03:29:53 AM UTC 24 1262973719 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.2719991837 Aug 29 03:29:49 AM UTC 24 Aug 29 03:29:53 AM UTC 24 483938653 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.512302297 Aug 29 03:29:49 AM UTC 24 Aug 29 03:29:54 AM UTC 24 983044775 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.582848062 Aug 29 03:29:53 AM UTC 24 Aug 29 03:29:55 AM UTC 24 156392441 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.3219182685 Aug 29 03:28:40 AM UTC 24 Aug 29 03:29:55 AM UTC 24 7761160807 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.3071139038 Aug 29 03:29:54 AM UTC 24 Aug 29 03:29:56 AM UTC 24 135878020 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.3249224751 Aug 29 03:29:54 AM UTC 24 Aug 29 03:29:56 AM UTC 24 160863721 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.1294395556 Aug 29 03:29:55 AM UTC 24 Aug 29 03:29:57 AM UTC 24 152051602 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.4276887478 Aug 29 03:29:56 AM UTC 24 Aug 29 03:29:59 AM UTC 24 305463905 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.3510462534 Aug 29 03:28:30 AM UTC 24 Aug 29 03:30:02 AM UTC 24 2915686416 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.2501005293 Aug 29 03:29:56 AM UTC 24 Aug 29 03:30:03 AM UTC 24 1140425695 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.785631760 Aug 29 03:29:09 AM UTC 24 Aug 29 03:30:04 AM UTC 24 5440980761 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.1387705738 Aug 29 03:29:07 AM UTC 24 Aug 29 03:30:04 AM UTC 24 24797344695 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.2821795080 Aug 29 03:29:57 AM UTC 24 Aug 29 03:30:04 AM UTC 24 347736804 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.611385829 Aug 29 03:30:03 AM UTC 24 Aug 29 03:30:05 AM UTC 24 178468496 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.3383229621 Aug 29 03:30:00 AM UTC 24 Aug 29 03:30:05 AM UTC 24 871142576 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_enable.838167966 Aug 29 03:30:04 AM UTC 24 Aug 29 03:30:06 AM UTC 24 44149479 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.1962804417 Aug 29 03:29:20 AM UTC 24 Aug 29 03:30:06 AM UTC 24 3759604828 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.2957883862 Aug 29 03:29:37 AM UTC 24 Aug 29 03:30:06 AM UTC 24 5774650548 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.2854358294 Aug 29 03:30:05 AM UTC 24 Aug 29 03:30:08 AM UTC 24 218424056 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.954954184 Aug 29 03:29:50 AM UTC 24 Aug 29 03:30:08 AM UTC 24 9654529955 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.1498933843 Aug 29 03:30:05 AM UTC 24 Aug 29 03:30:08 AM UTC 24 325008032 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.197635970 Aug 29 03:30:05 AM UTC 24 Aug 29 03:30:08 AM UTC 24 859168049 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.1527170750 Aug 29 03:29:45 AM UTC 24 Aug 29 03:30:09 AM UTC 24 1821243093 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.3643581630 Aug 29 03:28:35 AM UTC 24 Aug 29 03:30:09 AM UTC 24 31133332843 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.1553886919 Aug 29 03:30:09 AM UTC 24 Aug 29 03:30:11 AM UTC 24 137017992 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.318107186 Aug 29 03:30:09 AM UTC 24 Aug 29 03:30:11 AM UTC 24 164317140 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.720513535 Aug 29 03:30:06 AM UTC 24 Aug 29 03:30:12 AM UTC 24 293259925 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.3256007386 Aug 29 03:30:10 AM UTC 24 Aug 29 03:30:13 AM UTC 24 222981291 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.2415206866 Aug 29 03:30:12 AM UTC 24 Aug 29 03:30:15 AM UTC 24 228966298 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.1940866329 Aug 29 03:30:14 AM UTC 24 Aug 29 03:30:16 AM UTC 24 261551072 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.2406862161 Aug 29 03:29:35 AM UTC 24 Aug 29 03:30:18 AM UTC 24 4259195750 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.3025537258 Aug 29 03:30:16 AM UTC 24 Aug 29 03:30:18 AM UTC 24 203492790 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.19521979 Aug 29 03:30:19 AM UTC 24 Aug 29 03:30:22 AM UTC 24 222627978 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.3561073702 Aug 29 03:28:32 AM UTC 24 Aug 29 03:30:25 AM UTC 24 7203101675 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.566702606 Aug 29 03:30:22 AM UTC 24 Aug 29 03:30:25 AM UTC 24 167055829 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.924604098 Aug 29 03:29:31 AM UTC 24 Aug 29 03:30:25 AM UTC 24 13295484696 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.566208190 Aug 29 03:30:26 AM UTC 24 Aug 29 03:30:28 AM UTC 24 206835548 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.2864418909 Aug 29 03:30:26 AM UTC 24 Aug 29 03:30:28 AM UTC 24 197827066 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_stress_usb_traffic.2606665857 Aug 29 03:29:47 AM UTC 24 Aug 29 03:30:28 AM UTC 24 6340378991 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.3942759116 Aug 29 03:30:26 AM UTC 24 Aug 29 03:30:28 AM UTC 24 158641098 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.1792219330 Aug 29 03:27:48 AM UTC 24 Aug 29 03:30:29 AM UTC 24 14054897406 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.869710913 Aug 29 03:29:37 AM UTC 24 Aug 29 03:30:30 AM UTC 24 20161838376 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.2186715133 Aug 29 03:30:13 AM UTC 24 Aug 29 03:30:30 AM UTC 24 4756764834 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.48355425 Aug 29 03:30:29 AM UTC 24 Aug 29 03:30:32 AM UTC 24 179719518 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.1696507981 Aug 29 03:30:30 AM UTC 24 Aug 29 03:30:32 AM UTC 24 146304405 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.1290854796 Aug 29 03:30:29 AM UTC 24 Aug 29 03:30:32 AM UTC 24 185612298 ps
T263 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.2019939219 Aug 29 03:30:29 AM UTC 24 Aug 29 03:30:32 AM UTC 24 249939302 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.3461819352 Aug 29 03:30:30 AM UTC 24 Aug 29 03:30:33 AM UTC 24 236788694 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.2889909698 Aug 29 03:30:31 AM UTC 24 Aug 29 03:30:33 AM UTC 24 93202212 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.898634936 Aug 29 03:29:50 AM UTC 24 Aug 29 03:30:34 AM UTC 24 20830634380 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.595407514 Aug 29 03:30:33 AM UTC 24 Aug 29 03:30:35 AM UTC 24 253748620 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.299724446 Aug 29 03:30:33 AM UTC 24 Aug 29 03:30:35 AM UTC 24 175210846 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.2980669479 Aug 29 03:30:33 AM UTC 24 Aug 29 03:30:36 AM UTC 24 207386332 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.3450799891 Aug 29 03:30:33 AM UTC 24 Aug 29 03:30:36 AM UTC 24 176331266 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.969984341 Aug 29 03:29:58 AM UTC 24 Aug 29 03:30:37 AM UTC 24 5662130441 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.981688210 Aug 29 03:30:36 AM UTC 24 Aug 29 03:30:39 AM UTC 24 173803811 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.2133434739 Aug 29 03:30:37 AM UTC 24 Aug 29 03:30:39 AM UTC 24 179759971 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.2239611508 Aug 29 03:30:36 AM UTC 24 Aug 29 03:30:39 AM UTC 24 264196801 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.1463581771 Aug 29 03:30:12 AM UTC 24 Aug 29 03:30:40 AM UTC 24 7736080426 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.4131775711 Aug 29 03:30:37 AM UTC 24 Aug 29 03:30:40 AM UTC 24 364951261 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.68104899 Aug 29 03:30:38 AM UTC 24 Aug 29 03:30:40 AM UTC 24 202372143 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.3814347921 Aug 29 03:30:14 AM UTC 24 Aug 29 03:30:42 AM UTC 24 2722298289 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.3575746706 Aug 29 03:30:40 AM UTC 24 Aug 29 03:30:42 AM UTC 24 163886456 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.2766687542 Aug 29 03:30:40 AM UTC 24 Aug 29 03:30:42 AM UTC 24 200121514 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.686167917 Aug 29 03:30:40 AM UTC 24 Aug 29 03:30:42 AM UTC 24 238926942 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.3242789322 Aug 29 03:30:41 AM UTC 24 Aug 29 03:30:44 AM UTC 24 168146451 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.1332615818 Aug 29 03:30:41 AM UTC 24 Aug 29 03:30:44 AM UTC 24 178039189 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_low_speed_traffic.3192272587 Aug 29 03:30:13 AM UTC 24 Aug 29 03:30:47 AM UTC 24 3431290929 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.1921230174 Aug 29 03:30:45 AM UTC 24 Aug 29 03:30:48 AM UTC 24 479741488 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.1486083303 Aug 29 03:30:47 AM UTC 24 Aug 29 03:30:49 AM UTC 24 60744722 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.3871445403 Aug 29 03:30:46 AM UTC 24 Aug 29 03:30:49 AM UTC 24 435354045 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.3182959429 Aug 29 03:30:44 AM UTC 24 Aug 29 03:30:49 AM UTC 24 982099636 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.536733767 Aug 29 03:29:37 AM UTC 24 Aug 29 03:30:49 AM UTC 24 10036388292 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_freq_phase.2507115420 Aug 29 03:27:42 AM UTC 24 Aug 29 03:30:52 AM UTC 24 85194936125 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_max_usb_traffic.1073502738 Aug 29 03:30:17 AM UTC 24 Aug 29 03:30:52 AM UTC 24 2487233409 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.1449123744 Aug 29 03:27:38 AM UTC 24 Aug 29 03:30:52 AM UTC 24 89320048054 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.1690512745 Aug 29 03:30:51 AM UTC 24 Aug 29 03:30:53 AM UTC 24 140311102 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.2588424985 Aug 29 03:30:51 AM UTC 24 Aug 29 03:30:53 AM UTC 24 177122590 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.854807702 Aug 29 03:30:50 AM UTC 24 Aug 29 03:30:53 AM UTC 24 151790291 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.3086921038 Aug 29 03:30:51 AM UTC 24 Aug 29 03:30:53 AM UTC 24 146520829 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.1346188438 Aug 29 03:29:45 AM UTC 24 Aug 29 03:30:54 AM UTC 24 2395739075 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.3683267359 Aug 29 03:29:20 AM UTC 24 Aug 29 03:30:55 AM UTC 24 2841968062 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.1418661581 Aug 29 03:30:54 AM UTC 24 Aug 29 03:30:56 AM UTC 24 152602688 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.2495478291 Aug 29 03:30:54 AM UTC 24 Aug 29 03:30:57 AM UTC 24 291697582 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_enable.3579098093 Aug 29 03:30:55 AM UTC 24 Aug 29 03:30:58 AM UTC 24 64561644 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.3897657289 Aug 29 03:30:54 AM UTC 24 Aug 29 03:30:58 AM UTC 24 730316528 ps
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T536 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.1428261644 Aug 29 03:30:57 AM UTC 24 Aug 29 03:31:00 AM UTC 24 382150944 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.3097871235 Aug 29 03:29:52 AM UTC 24 Aug 29 03:31:00 AM UTC 24 30287527094 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.332755562 Aug 29 03:30:58 AM UTC 24 Aug 29 03:31:00 AM UTC 24 281269994 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.4137124881 Aug 29 03:30:55 AM UTC 24 Aug 29 03:31:01 AM UTC 24 958523811 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.2361769058 Aug 29 03:30:58 AM UTC 24 Aug 29 03:31:03 AM UTC 24 490083107 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.2752844636 Aug 29 03:31:03 AM UTC 24 Aug 29 03:31:05 AM UTC 24 146770240 ps
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T702 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.3284424671 Aug 29 03:30:54 AM UTC 24 Aug 29 03:31:06 AM UTC 24 422509375 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.354234603 Aug 29 03:31:04 AM UTC 24 Aug 29 03:31:06 AM UTC 24 218009860 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.1760049634 Aug 29 03:30:48 AM UTC 24 Aug 29 03:31:07 AM UTC 24 5386481295 ps
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T705 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.2226781502 Aug 29 03:31:07 AM UTC 24 Aug 29 03:31:10 AM UTC 24 254182552 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_resume_link_active.882920566 Aug 29 03:30:34 AM UTC 24 Aug 29 03:31:11 AM UTC 24 20162584041 ps
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T707 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.4166134985 Aug 29 03:31:11 AM UTC 24 Aug 29 03:31:13 AM UTC 24 191906901 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_rand_bus_resets.88954161 Aug 29 03:30:34 AM UTC 24 Aug 29 03:31:17 AM UTC 24 7028627344 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.495143418 Aug 29 03:31:07 AM UTC 24 Aug 29 03:31:19 AM UTC 24 4135707539 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.379780145 Aug 29 03:31:18 AM UTC 24 Aug 29 03:31:21 AM UTC 24 154652131 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_buffer.4190738556 Aug 29 03:30:32 AM UTC 24 Aug 29 03:31:21 AM UTC 24 16110906405 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.2532747435 Aug 29 03:31:19 AM UTC 24 Aug 29 03:31:22 AM UTC 24 144712963 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.3212942428 Aug 29 03:30:48 AM UTC 24 Aug 29 03:31:22 AM UTC 24 19399534658 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.2620072468 Aug 29 03:31:21 AM UTC 24 Aug 29 03:31:24 AM UTC 24 211059060 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.715904190 Aug 29 03:31:23 AM UTC 24 Aug 29 03:31:25 AM UTC 24 189846329 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.1227240412 Aug 29 03:31:23 AM UTC 24 Aug 29 03:31:25 AM UTC 24 177348453 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.3383668016 Aug 29 03:31:23 AM UTC 24 Aug 29 03:31:26 AM UTC 24 186076867 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.1153224392 Aug 29 03:31:25 AM UTC 24 Aug 29 03:31:28 AM UTC 24 214545634 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.2369833124 Aug 29 03:31:26 AM UTC 24 Aug 29 03:31:29 AM UTC 24 156135827 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.1647931085 Aug 29 03:31:26 AM UTC 24 Aug 29 03:31:29 AM UTC 24 210431414 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.2751817328 Aug 29 03:31:26 AM UTC 24 Aug 29 03:31:29 AM UTC 24 241372936 ps
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