Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	1833	1			T264	1		T64	3		T601	1
range_16_to_126	160647	1			T1	1		T2	1		T17	1
fifteen	3236	1			T64	3		T103	8		T117	4
range_2_to_14	18531	1			T20	1		T24	1		T87	1
seven	2180	1			T110	4		T64	6		T103	8
one	1644	1			T31	1		T34	2		T64	8
zero	1509	1			T20	1		T161	5		T83	1

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

17293

1

T1

1

T20

1

T21

4

three

14379

1

T17

1

T21

3

T28

2

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	118	1			T166	9		T117	1		T491	1
range_127	three	111	1			T166	9		T490	1		T181	1
range_16_to_126	seven	15504	1			T1	1		T20	1		T21	4
range_16_to_126	three	12487	1			T17	1		T21	3		T28	2
fifteen	seven	200	1			T117	1		T181	1		T491	1
fifteen	three	255	1			T117	1		T490	1		T602	1
range_2_to_14	seven	1286	1			T87	1		T110	1		T64	5
range_2_to_14	three	1319	1			T64	8		T103	1		T603	17
seven	seven	127	1			T110	1		T64	1		T103	1
seven	three	146	1			T396	8		T490	1		T604	1
one	seven	104	1			T279	42		T196	1		T605	1
one	three	109	1			T279	44		T196	2		T604	1
zero	seven	81	1			T103	1		T196	1		T606	1
zero	three	98	1			T103	1		T607	13		T602	44