Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	18	0	18	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_pkt_len	9	0	9	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_pkt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pktlen_X_dir	18	0	18	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

117107

1

T1

1

T2

1

T17

1

auto[1]

45953

1

T18

7

T21

17

T28

12

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Summary for Variable cp_pkt_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_pkt_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	29580	1			T18	1		T28	2		T30	1
max_len_m1	778	1			T18	1		T34	2		T43	3
max_len_m2	874	1			T70	1		T43	2		T5	2
max_len_m3	824	1			T21	2		T70	1		T43	3
five	1220	1			T7	2		T30	1		T43	2
four	1190	1			T70	1		T43	3		T71	1
three	732	1			T21	1		T43	2		T45	1
one	819	1			T43	2		T4	1		T617	2
zero	11359	1			T17	1		T18	7		T21	9

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Summary for Cross cr_pktlen_X_dir

Samples crossed: cp_pkt_len cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	18	0	18	100.00

Automatically Generated Cross Bins for cr_pktlen_X_dir

Bins

cp_pkt_len	cp_dir	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_len	auto[0]	23807	1			T18	1		T28	1		T30	1
max_len	auto[1]	5773	1			T28	1		T118	1		T4	1
max_len_m1	auto[0]	548	1			T18	1		T34	1		T43	3
max_len_m1	auto[1]	230	1			T34	1		T5	1		T6	1
max_len_m2	auto[0]	589	1			T70	1		T43	2		T5	1
max_len_m2	auto[1]	285	1			T5	1		T187	1		T171	1
max_len_m3	auto[0]	564	1			T21	1		T70	1		T43	3
max_len_m3	auto[1]	260	1			T21	1		T187	1		T158	1
five	auto[0]	636	1			T7	1		T30	1		T43	2
five	auto[1]	584	1			T7	1		T4	1		T5	1
four	auto[0]	622	1			T70	1		T43	3		T71	1
four	auto[1]	568	1			T4	1		T158	1		T171	1
three	auto[0]	385	1			T21	1		T43	2		T51	1
three	auto[1]	347	1			T45	1		T91	9		T279	7
one	auto[0]	369	1			T43	2		T4	1		T617	1
one	auto[1]	450	1			T617	1		T91	5		T618	1
zero	auto[0]	570	1			T17	1		T28	1		T43	2
zero	auto[1]	10789	1			T18	7		T21	9		T28	1