Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_dir	2	0	2	100.00	100	1	1	2
cp_endp	12	0	12	100.00	100	1	1	0
cp_pid	4	0	4	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::data_tog_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_dir_X_endp	96	0	96	100.00	100	1	1	0

Summary for Variable cp_dir

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_dir

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138805

1

T1

2

T2

2

T18

12

auto[1]

78179

1

T18

14

T21

28

T28

24

---

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
endpoints[0x0]	16160	1			T21	12		T23	16		T28	4
endpoints[0x1]	12945	1			T28	4		T6	28		T49	16
endpoints[0x2]	18945	1			T21	4		T28	4		T30	21
endpoints[0x3]	19315	1			T21	5		T28	4		T29	14
endpoints[0x4]	17863	1			T21	10		T28	4		T70	21
endpoints[0x5]	15482	1			T21	2		T28	4		T72	4
endpoints[0x6]	20582	1			T21	4		T28	4		T7	4
endpoints[0x7]	24662	1			T1	2		T21	8		T28	4
endpoints[0x8]	15911	1			T21	2		T28	4		T118	4
endpoints[0x9]	16269	1			T21	7		T28	4		T4	20
endpoints[0xa]	16797	1			T2	2		T21	2		T28	4
endpoints[0xb]	22053	1			T18	26		T21	6		T28	4

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	1515	1			T21	5		T30	2		T70	2
ack	104674	1			T1	1		T2	1		T18	13
data1	51068	1			T18	3		T21	17		T30	5
data0	59659	1			T1	1		T2	1		T18	10

---

Summary for Cross cr_pid_X_dir_X_endp

Samples crossed: cp_pid cp_dir cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	96	0	96	100.00

Automatically Generated Cross Bins for cr_pid_X_dir_X_endp

Bins

cp_pid	cp_dir	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
nak	auto[0]	endpoints[0x0]	97	1			T103	12		T127	1		T619	9
nak	auto[0]	endpoints[0x1]	88	1			T49	1		T50	1		T381	1
nak	auto[0]	endpoints[0x2]	104	1			T30	2		T117	10		T181	10
nak	auto[0]	endpoints[0x3]	121	1			T620	1		T117	16		T602	8
nak	auto[0]	endpoints[0x4]	148	1			T70	2		T621	1		T126	1
nak	auto[0]	endpoints[0x5]	106	1			T72	1		T578	1		T580	1
nak	auto[0]	endpoints[0x6]	152	1			T139	1		T195	10		T490	10
nak	auto[0]	endpoints[0x7]	53	1			T622	1		T142	1		T623	1
nak	auto[0]	endpoints[0x8]	79	1			T145	1		T624	1		T625	6
nak	auto[0]	endpoints[0x9]	146	1			T196	18		T626	1		T148	1
nak	auto[0]	endpoints[0xa]	101	1			T579	1		T627	1		T346	1
nak	auto[0]	endpoints[0xb]	122	1			T71	2		T64	15		T154	1
nak	auto[1]	endpoints[0x0]	17	1			T21	1		T628	2		T629	1
nak	auto[1]	endpoints[0x1]	14	1			T630	1		T631	1		T632	2
nak	auto[1]	endpoints[0x2]	10	1			T633	1		T634	1		T635	1
nak	auto[1]	endpoints[0x3]	16	1			T114	1		T629	1		T636	1
nak	auto[1]	endpoints[0x4]	21	1			T21	1		T114	1		T633	1
nak	auto[1]	endpoints[0x5]	23	1			T628	1		T289	1		T636	1
nak	auto[1]	endpoints[0x6]	20	1			T114	1		T637	1		T636	1
nak	auto[1]	endpoints[0x7]	19	1			T21	1		T110	1		T114	2
nak	auto[1]	endpoints[0x8]	14	1			T114	1		T628	1		T289	1
nak	auto[1]	endpoints[0x9]	15	1			T114	1		T633	1		T628	1
nak	auto[1]	endpoints[0xa]	10	1			T21	1		T630	1		T638	1
nak	auto[1]	endpoints[0xb]	19	1			T21	1		T633	1		T637	1
ack	auto[0]	endpoints[0x0]	4624	1			T21	3		T23	8		T28	1
ack	auto[0]	endpoints[0x1]	3444	1			T28	1		T6	7		T49	7
ack	auto[0]	endpoints[0x2]	5772	1			T21	2		T28	1		T30	8
ack	auto[0]	endpoints[0x3]	5773	1			T21	1		T28	1		T29	7
ack	auto[0]	endpoints[0x4]	5411	1			T21	1		T28	1		T70	8
ack	auto[0]	endpoints[0x5]	4199	1			T21	1		T28	1		T72	1
ack	auto[0]	endpoints[0x6]	6934	1			T21	2		T28	1		T7	1
ack	auto[0]	endpoints[0x7]	8710	1			T1	1		T21	3		T28	1
ack	auto[0]	endpoints[0x8]	4529	1			T28	1		T118	1		T58	1
ack	auto[0]	endpoints[0x9]	4512	1			T21	2		T28	1		T4	5
ack	auto[0]	endpoints[0xa]	4655	1			T2	1		T28	1		T44	2
ack	auto[0]	endpoints[0xb]	7654	1			T18	6		T21	2		T28	1
ack	auto[1]	endpoints[0x0]	3168	1			T21	1		T28	1		T33	1
ack	auto[1]	endpoints[0x1]	2746	1			T28	1		T6	7		T157	2
ack	auto[1]	endpoints[0x2]	3433	1			T28	1		T4	5		T162	1
ack	auto[1]	endpoints[0x3]	3545	1			T21	1		T28	1		T4	5
ack	auto[1]	endpoints[0x4]	3195	1			T21	3		T28	1		T108	3
ack	auto[1]	endpoints[0x5]	3202	1			T28	1		T159	1		T6	7
ack	auto[1]	endpoints[0x6]	2999	1			T28	1		T7	1		T6	7
ack	auto[1]	endpoints[0x7]	3345	1			T28	1		T160	1		T4	5
ack	auto[1]	endpoints[0x8]	3131	1			T28	1		T118	1		T58	1
ack	auto[1]	endpoints[0x9]	3234	1			T21	1		T28	1		T4	5
ack	auto[1]	endpoints[0xa]	3407	1			T28	1		T59	8		T44	1
ack	auto[1]	endpoints[0xb]	3052	1			T18	7		T28	1		T4	5
data1	auto[0]	endpoints[0x0]	2050	1			T21	2		T4	2		T161	3
data1	auto[0]	endpoints[0x1]	1452	1			T49	4		T157	2		T110	1
data1	auto[0]	endpoints[0x2]	2616	1			T21	2		T30	5		T162	1
data1	auto[0]	endpoints[0x3]	2547	1			T4	1		T171	4		T91	17
data1	auto[0]	endpoints[0x4]	2498	1			T21	1		T70	5		T4	2
data1	auto[0]	endpoints[0x5]	1826	1			T72	1		T6	2		T91	15
data1	auto[0]	endpoints[0x6]	3202	1			T21	1		T6	3		T111	2
data1	auto[0]	endpoints[0x7]	4029	1			T4	2		T46	1		T6	3
data1	auto[0]	endpoints[0x8]	2003	1			T65	2		T91	14		T166	1
data1	auto[0]	endpoints[0x9]	2064	1			T21	2		T4	1		T5	17
data1	auto[0]	endpoints[0xa]	2025	1			T44	1		T65	1		T91	16
data1	auto[0]	endpoints[0xb]	3563	1			T18	1		T21	2		T71	5
data1	auto[1]	endpoints[0x0]	1717	1			T21	1		T4	2		T161	5
data1	auto[1]	endpoints[0x1]	1504	1			T6	7		T157	2		T65	3
data1	auto[1]	endpoints[0x2]	1883	1			T4	5		T162	1		T6	3
data1	auto[1]	endpoints[0x3]	2003	1			T21	1		T4	4		T171	9
data1	auto[1]	endpoints[0x4]	1778	1			T21	3		T108	6		T4	3
data1	auto[1]	endpoints[0x5]	1788	1			T6	5		T64	8		T91	16
data1	auto[1]	endpoints[0x6]	1630	1			T6	3		T111	2		T65	2
data1	auto[1]	endpoints[0x7]	1850	1			T4	2		T46	1		T6	3
data1	auto[1]	endpoints[0x8]	1693	1			T21	1		T65	2		T91	14
data1	auto[1]	endpoints[0x9]	1761	1			T21	1		T4	3		T5	17
data1	auto[1]	endpoints[0xa]	1882	1			T59	7		T44	1		T65	2
data1	auto[1]	endpoints[0xb]	1704	1			T18	2		T4	2		T6	5
data0	auto[0]	endpoints[0x0]	2951	1			T21	1		T23	8		T28	1
data0	auto[0]	endpoints[0x1]	2366	1			T28	1		T6	7		T49	4
data0	auto[0]	endpoints[0x2]	3515	1			T28	1		T30	6		T32	1
data0	auto[0]	endpoints[0x3]	3702	1			T21	1		T28	1		T29	7
data0	auto[0]	endpoints[0x4]	3272	1			T28	1		T70	6		T4	3
data0	auto[0]	endpoints[0x5]	2805	1			T21	1		T28	1		T72	1
data0	auto[0]	endpoints[0x6]	4171	1			T21	1		T28	1		T7	1
data0	auto[0]	endpoints[0x7]	5065	1			T1	1		T21	3		T28	1
data0	auto[0]	endpoints[0x8]	2939	1			T28	1		T118	1		T58	1
data0	auto[0]	endpoints[0x9]	2982	1			T28	1		T4	4		T429	1
data0	auto[0]	endpoints[0xa]	3094	1			T2	1		T28	1		T44	1
data0	auto[0]	endpoints[0xb]	4516	1			T18	5		T28	1		T71	6
data0	auto[1]	endpoints[0x0]	1533	1			T21	3		T28	1		T33	1
data0	auto[1]	endpoints[0x1]	1322	1			T28	1		T158	1		T65	1
data0	auto[1]	endpoints[0x2]	1604	1			T28	1		T6	4		T158	1
data0	auto[1]	endpoints[0x3]	1604	1			T21	1		T28	1		T4	1
data0	auto[1]	endpoints[0x4]	1535	1			T21	1		T28	1		T108	5
data0	auto[1]	endpoints[0x5]	1525	1			T28	1		T159	1		T6	2
data0	auto[1]	endpoints[0x6]	1466	1			T28	1		T7	1		T34	1
data0	auto[1]	endpoints[0x7]	1586	1			T21	1		T28	1		T160	1
data0	auto[1]	endpoints[0x8]	1520	1			T21	1		T28	1		T118	1
data0	auto[1]	endpoints[0x9]	1552	1			T21	1		T28	1		T4	2
data0	auto[1]	endpoints[0xa]	1614	1			T21	1		T28	1		T59	10
data0	auto[1]	endpoints[0xb]	1420	1			T18	5		T21	1		T28	1