Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv


Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_in_enable 2 0 2 100.00 100 1 1 2
cp_in_iso 2 0 2 100.00 100 1 1 2
cp_in_stall 2 0 2 100.00 100 1 1 2
cp_pid 2 0 2 100.00 100 1 1 0


Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_in_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_pid_x_epconfig 16 0 16 100.00 100 1 1 0


Summary for Variable cp_in_enable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_enable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 9356 1 T20 2 T24 2 T264 4
auto[1] 54823 1 T18 7 T20 7 T21 17


Summary for Variable cp_in_iso

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_iso

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 56366 1 T18 7 T20 9 T21 17
auto[1] 7813 1 T24 4 T32 1 T105 1


Summary for Variable cp_in_stall

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_in_stall

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 57809 1 T18 7 T20 8 T21 17
auto[1] 6370 1 T20 1 T24 3 T31 1


Summary for Variable cp_pid

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_pid

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] 4947 1 T20 2 T24 2 T264 1
pkt_types[PidTypeInToken] 59232 1 T18 7 T20 7 T21 17


Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_in_enable cp_in_iso cp_in_stall
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_pid_x_epconfig

Bins
cp_pidcp_in_enablecp_in_isocp_in_stallCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
ignore_pre[PidTypePre] auto[0] auto[0] auto[0] 1546 1 T64 20 T178 2 T103 7
ignore_pre[PidTypePre] auto[0] auto[0] auto[1] 802 1 T264 1 T64 45 T103 39
ignore_pre[PidTypePre] auto[0] auto[1] auto[0] 80 1 T178 1 T249 3 T639 1
ignore_pre[PidTypePre] auto[0] auto[1] auto[1] 17 1 T562 1 T513 1 T464 1
ignore_pre[PidTypePre] auto[1] auto[0] auto[0] 1636 1 T20 2 T24 1 T64 23
ignore_pre[PidTypePre] auto[1] auto[0] auto[1] 750 1 T64 17 T103 7 T448 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[0] 104 1 T178 1 T249 3 T566 1
ignore_pre[PidTypePre] auto[1] auto[1] auto[1] 12 1 T24 1 T522 1 T528 1
pkt_types[PidTypeInToken] auto[0] auto[0] auto[0] 4492 1 T20 1 T24 1 T64 59
pkt_types[PidTypeInToken] auto[0] auto[0] auto[1] 2319 1 T20 1 T264 3 T64 121
pkt_types[PidTypeInToken] auto[0] auto[1] auto[0] 46 1 T562 1 T514 1 T458 3
pkt_types[PidTypeInToken] auto[0] auto[1] auto[1] 54 1 T24 1 T566 1 T532 1
pkt_types[PidTypeInToken] auto[1] auto[0] auto[0] 42445 1 T18 7 T20 5 T21 17
pkt_types[PidTypeInToken] auto[1] auto[0] auto[1] 2376 1 T31 1 T107 1 T264 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[0] 7460 1 T24 1 T32 1 T105 1
pkt_types[PidTypeInToken] auto[1] auto[1] auto[1] 40 1 T24 1 T566 1 T463 2

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