Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

Group : usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.03	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	192	2	190	98.96

Variables for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_out_enable	2	0	2	100.00	100	1	1	2
cp_out_iso	2	0	2	100.00	100	1	1	2
cp_out_stall	2	0	2	100.00	100	1	1	2
cp_pid	3	0	3	100.00	100	1	1	0
cp_rxenable_out	2	0	2	100.00	100	1	1	2
cp_rxenable_setup	2	0	2	100.00	100	1	1	2
cp_set_nak_out	2	0	2	100.00	100	1	1	2

Crosses for Group usbdev_env_pkg::usbdev_env_cov::ep_out_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_x_epconfig	192	2	190	98.96	100	1	1	0

Summary for Variable cp_out_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18490

1

T20

14

T24

4

T43

131

auto[1]

84346

1

T1

1

T2

1

T17

1

---

Summary for Variable cp_out_iso

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_iso

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100410

1

T1

1

T2

1

T17

1

auto[1]

2426

1

T24

6

T86

1

T115

4

---

Summary for Variable cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_out_stall

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

88902

1

T1

1

T2

1

T17

1

auto[1]

13934

1

T20

1

T24

6

T73

1

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
ignore_pre[PidTypePre]	9958	1			T20	1		T24	1		T264	11
pkt_types[PidTypeSetupToken]	21426	1			T1	1		T20	4		T23	8
pkt_types[PidTypeOutToken]	71386	1			T2	1		T17	1		T18	6

---

Summary for Variable cp_rxenable_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19676

1

T1

1

T20

5

T24

3

auto[1]

83160

1

T2

1

T17

1

T18

6

---

Summary for Variable cp_rxenable_setup

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_rxenable_setup

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

68513

1

T2

1

T17

1

T18

6

auto[1]

34323

1

T1

1

T20

4

T23

8

---

Summary for Variable cp_set_nak_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_set_nak_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102157

1

T1

1

T2

1

T17

1

auto[1]

679

1

T24

4

T72

2

T432

1

---

Summary for Cross cr_pid_x_epconfig

Samples crossed: cp_pid cp_out_enable cp_rxenable_setup cp_rxenable_out cp_set_nak_out cp_out_iso cp_out_stall

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	192	2	190	98.96	2

Automatically Generated Cross Bins for cr_pid_x_epconfig

Uncovered bins

cp_pid	cp_out_enable	cp_rxenable_setup	cp_rxenable_out	cp_set_nak_out	cp_out_iso	cp_out_stall	COUNT	AT LEAST	NUMBER	STATUS
[ignore_pre[PidTypePre]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[pkt_types[PidTypeOutToken]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_pid

cp_out_enable

cp_rxenable_setup

cp_rxenable_out

cp_set_nak_out

cp_out_iso

cp_out_stall

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

647

1

T264

7

T64

12

T178

3

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

560

1

T264

2

T103

16

T433

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

87

1

T178

1

T250

2

T434

5

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T435

1

T436

1

T437

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T438

1

T439

1

T440

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T436

1

T441

1

T442

2

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T443

1

T444

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

4

1

T445

1

T446

1

T447

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

429

1

T20

1

T64

10

T103

31

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

438

1

T448

2

T195

15

T449

3

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T450

1

T451

1

T452

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T444

1

T453

1

T454

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

5

1

T455

1

T456

1

T457

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T458

1

T459

1

T460

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T115

1

T461

1

T462

1

ignore_pre[PidTypePre]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T463

1

T464

1

T465

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

696

1

T64

40

T178

1

T249

5

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

645

1

T64

13

T103

10

T117

16

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

73

1

T178

1

T249

2

T250

3

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T466

1

T467

1

T468

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T441

1

T469

1

T470

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T456

1

T471

1

T468

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T472

1

T473

1

T474

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T475

1

T472

1

T476

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

583

1

T264

2

T64

13

T103

18

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

525

1

T64

15

T103

15

T448

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T477

1

T478

1

T460

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T479

1

T457

1

T480

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T481

1

T482

1

-

-

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T483

1

T484

2

T485

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T455

1

T486

1

T487

1

ignore_pre[PidTypePre]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T459

1

T488

1

T489

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

457

1

T117

12

T490

12

T491

12

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

586

1

T117

45

T195

12

T196

45

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T492

2

T493

2

T494

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T495

1

T496

1

T441

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

4

1

T497

1

T498

1

T499

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T500

1

T456

1

T501

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T444

1

T474

1

T454

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

600

1

T103

12

T249

3

T250

4

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

516

1

T64

26

T117

15

T195

23

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

91

1

T178

4

T249

8

T502

2

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

7

1

T503

1

T504

1

T486

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T505

1

T506

1

T498

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

9

1

T483

1

T495

1

T507

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T445

1

T435

1

T508

1

ignore_pre[PidTypePre]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T465

1

T459

1

T509

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1072

1

T24

1

T64

7

T103

14

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

19

1

T64

1

T490

1

T510

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

2

1

T497

1

T485

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T511

1

T467

1

T512

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

1

1

T513

1

-

-

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T445

1

T439

1

T444

2

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T115

1

T514

1

T497

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

2

1

T515

1

T516

1

-

-

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

1624

1

T64

16

T178

3

T103

33

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T117

3

T195

3

T181

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

77

1

T249

2

T250

1

T434

3

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T517

2

T458

1

T518

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T519

1

T520

1

T521

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T522

1

T441

1

T523

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T451

2

T459

1

T492

1

ignore_pre[PidTypePre]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T524

1

T525

1

T526

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

771

1

T264

4

T64

30

T448

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

813

1

T264

2

T103

25

T448

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

7

1

T440

1

T501

1

T527

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T435

2

T528

1

T529

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T439

1

T524

1

T530

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T443

1

T436

1

T474

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

1

1

T443

1

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T531

1

T532

1

T510

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

709

1

T20

1

T64

28

T103

38

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

694

1

T448

1

T195

24

T449

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

2

1

T472

1

T462

1

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T24

1

T444

1

T520

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

2

1

T533

2

-

-

-

-

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T496

1

T534

1

T459

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

6

1

T535

1

T465

1

T482

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T439

1

T479

1

T461

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1010

1

T20

3

T64

92

T448

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

969

1

T64

19

T103

22

T448

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T480

1

T527

1

T460

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T466

1

T517

1

T467

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T536

1

T537

1

T529

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T536

2

T456

1

T538

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T539

1

T462

1

T540

3

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T536

1

T514

1

T541

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

911

1

T264

1

T64

18

T103

28

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

757

1

T264

1

T64

22

T103

34

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

4

1

T542

1

T471

1

T478

2

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T24

2

T543

1

T479

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T544

1

T545

1

T454

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T529

3

T541

1

T441

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

8

1

T450

1

T546

1

T512

1

pkt_types[PidTypeSetupToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T510

1

T547

1

T548

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

745

1

T247

1

T248

1

T549

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

944

1

T536

1

T117

94

T195

14

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

11

1

T550

1

T551

1

T515

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T514

2

T496

2

T441

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

10

1

T513

2

T543

3

T444

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T537

1

T500

1

T552

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T24

1

T438

1

T454

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T458

1

T484

1

T553

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

787

1

T103

30

T79

2

T82

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

747

1

T64

50

T117

21

T195

50

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

10

1

T463

1

T543

1

T438

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T506

1

T504

2

T486

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T463

1

T554

1

T555

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T505

1

T495

1

T476

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

3

1

T479

1

T508

1

T462

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

6

1

T517

1

T556

1

T557

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1920

1

T1

1

T88

1

T49

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

42

1

T64

1

T103

1

T195

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

10

1

T497

2

T455

1

T558

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T445

1

T440

1

T559

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

5

1

T514

1

T560

1

T561

2

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T24

1

T497

3

T539

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

4

1

T562

1

T563

1

T436

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T564

1

T565

1

T472

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

8876

1

T23

8

T29

7

T4

12

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

62

1

T107

1

T199

1

T103

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

368

1

T249

4

T566

1

T250

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T504

1

T567

2

T568

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

7

1

T535

1

T515

1

T558

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T544

1

T569

1

T560

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T451

2

T475

1

T444

1

pkt_types[PidTypeSetupToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T24

1

T451

1

T551

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

1026

1

T43

131

T83

1

T264

3

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

832

1

T20

1

T264

2

T103

23

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

3

1

T564

1

T501

1

T559

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

10

1

T522

1

T517

2

T529

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

3

1

T445

1

T470

2

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T475

1

T474

1

T570

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T539

1

T571

1

T526

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T536

1

T444

1

T498

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

696

1

T20

7

T64

26

T103

41

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

646

1

T448

1

T195

31

T449

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T514

1

T569

1

T511

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T546

1

T456

1

T572

2

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T497

1

T458

1

T456

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T115

1

T499

1

T442

1

pkt_types[PidTypeOutToken]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T487

1

-

-

-

-

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

969

1

T20

1

T64

59

T448

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1010

1

T64

26

T103

19

T117

28

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

6

1

T566

1

T573

1

T478

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T486

1

T561

1

T437

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

10

1

T536

1

T537

5

T438

2

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T503

1

T456

1

T574

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

9

1

T531

1

T564

1

T472

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T551

1

T456

1

T476

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

848

1

T24

1

T64

16

T103

20

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

753

1

T64

22

T103

49

T448

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

8

1

T562

1

T497

1

T438

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T439

1

T563

1

T570

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T544

2

T530

1

T575

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T463

1

T543

1

T576

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T450

2

T514

1

T522

1

pkt_types[PidTypeOutToken]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T544

1

T516

1

T577

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

763

1

T578

1

T579

1

T580

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

906

1

T117

78

T195

25

T196

68

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

9

1

T115

1

T445

1

T564

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T466

1

T581

1

T537

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

58

1

T72

1

T139

1

T145

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

7

1

T435

2

T461

1

T582

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T458

1

T541

1

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T438

1

T515

1

T508

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

50725

1

T2

1

T17

1

T18

6

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

883

1

T73

1

T243

1

T64

47

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

856

1

T86

1

T239

1

T106

23

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T475

1

T445

1

T456

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

54

1

T72

1

T115

1

T139

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

56

1

T432

1

T583

1

T584

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T435

1

T497

1

T479

1

pkt_types[PidTypeOutToken]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T537

1

T500

1

T473

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

1593

1

T115

1

T64

23

T103

24

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

28

1

T64

1

T585

1

T586

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

5

1

T455

1

T496

1

T436

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T536

1

T537

1

T587

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

12

1

T581

1

T506

1

T556

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

8

1

T569

1

T539

2

T444

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

6

1

T536

1

T587

2

T563

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T435

1

T479

1

T515

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

7997

1

T4

8

T44

1

T45

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

60

1

T107

1

T199

1

T190

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

368

1

T249

3

T250

3

T251

8

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T517

1

T544

1

T529

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

8

1

T450

1

T588

1

T582

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T588

1

T498

1

-

-

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T531

1

T517

1

T587

1

pkt_types[PidTypeOutToken]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T24

1

T564

1

T524

1