Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	84232	1			T1	4		T2	6		T3	3
all_pins[1]	84232	1			T1	4		T2	6		T3	3
all_pins[2]	84232	1			T1	4		T2	6		T3	3
all_pins[3]	84232	1			T1	4		T2	6		T3	3
all_pins[4]	84232	1			T1	4		T2	6		T3	3
all_pins[5]	84232	1			T1	4		T2	6		T3	3
all_pins[6]	84232	1			T1	4		T2	6		T3	3
all_pins[7]	84232	1			T1	4		T2	6		T3	3
all_pins[8]	84232	1			T1	4		T2	6		T3	3
all_pins[9]	84232	1			T1	4		T2	6		T3	3
all_pins[10]	84232	1			T1	4		T2	6		T3	3
all_pins[11]	84232	1			T1	4		T2	6		T3	3
all_pins[12]	84232	1			T1	4		T2	6		T3	3
all_pins[13]	84232	1			T1	4		T2	6		T3	3
all_pins[14]	84232	1			T1	4		T2	6		T3	3
all_pins[15]	84232	1			T1	4		T2	6		T3	3
all_pins[16]	84232	1			T1	4		T2	6		T3	3
all_pins[17]	84232	1			T1	4		T2	6		T3	3

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2693224	1			T1	128		T2	191		T3	96
values[0x1]	2200	1			T2	1		T16	2		T17	1
transitions[0x0=>0x1]	1940	1			T2	1		T16	2		T17	1
transitions[0x1=>0x0]	1940	1			T2	1		T16	2		T17	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	84127	1			T1	4		T2	6		T3	3
all_pins[0]	values[0x1]	105	1			T429	1		T430	1		T431	1
all_pins[0]	transitions[0x0=>0x1]	87	1			T429	1		T430	1		T431	1
all_pins[0]	transitions[0x1=>0x0]	844	1			T28	12		T7	1		T33	1
all_pins[1]	values[0x0]	83370	1			T1	4		T2	6		T3	3
all_pins[1]	values[0x1]	862	1			T28	12		T7	1		T33	1
all_pins[1]	transitions[0x0=>0x1]	851	1			T28	12		T7	1		T33	1
all_pins[1]	transitions[0x1=>0x0]	108	1			T19	1		T62	1		T63	1
all_pins[2]	values[0x0]	84113	1			T1	4		T2	6		T3	3
all_pins[2]	values[0x1]	119	1			T19	1		T62	1		T63	1
all_pins[2]	transitions[0x0=>0x1]	94	1			T19	1		T62	1		T63	1
all_pins[2]	transitions[0x1=>0x0]	44	1			T43	1		T230	1		T232	1
all_pins[3]	values[0x0]	84163	1			T1	4		T2	6		T3	3
all_pins[3]	values[0x1]	69	1			T43	1		T230	1		T232	1
all_pins[3]	transitions[0x0=>0x1]	37	1			T43	1		T230	1		T232	1
all_pins[3]	transitions[0x1=>0x0]	65	1			T42	1		T230	1		T232	3
all_pins[4]	values[0x0]	84135	1			T1	4		T2	6		T3	3
all_pins[4]	values[0x1]	97	1			T42	1		T230	1		T232	3
all_pins[4]	transitions[0x0=>0x1]	74	1			T42	1		T230	1		T232	1
all_pins[4]	transitions[0x1=>0x0]	37	1			T233	1		T230	2		T232	2
all_pins[5]	values[0x0]	84172	1			T1	4		T2	6		T3	3
all_pins[5]	values[0x1]	60	1			T233	1		T230	2		T232	4
all_pins[5]	transitions[0x0=>0x1]	41	1			T230	2		T232	4		T326	1
all_pins[5]	transitions[0x1=>0x0]	99	1			T66	1		T68	1		T69	1
all_pins[6]	values[0x0]	84114	1			T1	4		T2	6		T3	3
all_pins[6]	values[0x1]	118	1			T66	1		T68	1		T69	1
all_pins[6]	transitions[0x0=>0x1]	105	1			T66	1		T68	1		T69	1
all_pins[6]	transitions[0x1=>0x0]	46	1			T2	1		T47	1		T48	1
all_pins[7]	values[0x0]	84173	1			T1	4		T2	5		T3	3
all_pins[7]	values[0x1]	59	1			T2	1		T47	1		T48	1
all_pins[7]	transitions[0x0=>0x1]	51	1			T2	1		T47	1		T48	1
all_pins[7]	transitions[0x1=>0x0]	61	1			T53	1		T54	1		T55	1
all_pins[8]	values[0x0]	84163	1			T1	4		T2	6		T3	3
all_pins[8]	values[0x1]	69	1			T53	1		T54	1		T55	1
all_pins[8]	transitions[0x0=>0x1]	53	1			T53	1		T54	1		T55	1
all_pins[8]	transitions[0x1=>0x0]	62	1			T16	2		T60	2		T61	2
all_pins[9]	values[0x0]	84154	1			T1	4		T2	6		T3	3
all_pins[9]	values[0x1]	78	1			T16	2		T60	2		T61	2
all_pins[9]	transitions[0x0=>0x1]	58	1			T16	2		T60	2		T61	2
all_pins[9]	transitions[0x1=>0x0]	42	1			T328	1		T330	1		T333	2
all_pins[10]	values[0x0]	84170	1			T1	4		T2	6		T3	3
all_pins[10]	values[0x1]	62	1			T232	1		T326	1		T327	1
all_pins[10]	transitions[0x0=>0x1]	50	1			T232	1		T327	1		T328	1
all_pins[10]	transitions[0x1=>0x0]	84	1			T74	1		T75	1		T76	1
all_pins[11]	values[0x0]	84136	1			T1	4		T2	6		T3	3
all_pins[11]	values[0x1]	96	1			T74	1		T75	1		T76	1
all_pins[11]	transitions[0x0=>0x1]	93	1			T74	1		T75	1		T76	1
all_pins[11]	transitions[0x1=>0x0]	59	1			T77	1		T78	1		T80	1
all_pins[12]	values[0x0]	84170	1			T1	4		T2	6		T3	3
all_pins[12]	values[0x1]	62	1			T77	1		T78	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	53	1			T77	1		T78	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	100	1			T17	1		T83	1		T84	1
all_pins[13]	values[0x0]	84123	1			T1	4		T2	6		T3	3
all_pins[13]	values[0x1]	109	1			T17	1		T83	1		T84	1
all_pins[13]	transitions[0x0=>0x1]	98	1			T17	1		T83	1		T84	1
all_pins[13]	transitions[0x1=>0x0]	49	1			T233	3		T230	2		T231	2
all_pins[14]	values[0x0]	84172	1			T1	4		T2	6		T3	3
all_pins[14]	values[0x1]	60	1			T233	3		T230	3		T231	2
all_pins[14]	transitions[0x0=>0x1]	40	1			T233	3		T230	3		T231	2
all_pins[14]	transitions[0x1=>0x0]	43	1			T232	1		T326	3		T325	2
all_pins[15]	values[0x0]	84169	1			T1	4		T2	6		T3	3
all_pins[15]	values[0x1]	63	1			T232	1		T326	3		T325	2
all_pins[15]	transitions[0x0=>0x1]	50	1			T232	1		T326	3		T325	1
all_pins[15]	transitions[0x1=>0x0]	58	1			T30	4		T70	4		T71	4
all_pins[16]	values[0x0]	84161	1			T1	4		T2	6		T3	3
all_pins[16]	values[0x1]	71	1			T30	4		T70	4		T71	4
all_pins[16]	transitions[0x0=>0x1]	64	1			T30	4		T70	4		T71	4
all_pins[16]	transitions[0x1=>0x0]	34	1			T56	1		T57	1		T233	1
all_pins[17]	values[0x0]	84191	1			T1	4		T2	6		T3	3
all_pins[17]	values[0x1]	41	1			T56	1		T57	1		T233	1
all_pins[17]	transitions[0x0=>0x1]	41	1			T56	1		T57	1		T233	1