Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

Group : usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

---

Summary for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	19	0	19	100.00
Crosses	48	0	48	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_endp	16	0	16	100.00	100	1	1	0
cp_pid	3	0	3	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::pid_type_endp_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_pid_X_endp	48	0	48	100.00	100	1	1	0

Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for cp_endp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
invalid_ep[0xc]	5180	1			T4	10		T115	1		T64	105
invalid_ep[0xd]	5016	1			T4	8		T64	81		T185	6
invalid_ep[0xe]	5054	1			T4	5		T115	1		T64	91
invalid_ep[0xf]	5135	1			T24	1		T4	8		T115	1
endpoints[0x0]	12754	1			T21	7		T23	8		T24	2
endpoints[0x1]	12041	1			T24	1		T28	2		T6	15
endpoints[0x2]	14949	1			T21	2		T24	2		T28	2
endpoints[0x3]	14379	1			T17	1		T21	3		T28	2
endpoints[0x4]	14138	1			T21	5		T24	2		T28	2
endpoints[0x5]	12652	1			T20	15		T21	1		T24	1
endpoints[0x6]	14926	1			T21	2		T28	2		T7	2
endpoints[0x7]	17293	1			T1	1		T20	1		T21	4
endpoints[0x8]	12502	1			T20	2		T21	2		T24	3
endpoints[0x9]	12881	1			T21	4		T24	2		T28	2
endpoints[0xa]	13004	1			T2	1		T21	1		T24	2
endpoints[0xb]	15496	1			T18	13		T20	5		T21	3

---

Summary for Variable cp_pid

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_pid

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	26070	1			T1	1		T20	4		T23	8
pkt_types[PidTypeOutToken]	78169	1			T2	1		T17	1		T18	6
pkt_types[PidTypeInToken]	63694	1			T18	7		T20	7		T21	17

---

Summary for Cross cr_pid_X_endp

Samples crossed: cp_pid cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	0	48	100.00

Automatically Generated Cross Bins for cr_pid_X_endp

Bins

cp_pid	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pkt_types[PidTypeSetupToken]	invalid_ep[0xc]	1161	1			T115	1		T64	27		T103	17
pkt_types[PidTypeSetupToken]	invalid_ep[0xd]	1162	1			T64	20		T103	27		T117	24
pkt_types[PidTypeSetupToken]	invalid_ep[0xe]	1140	1			T64	23		T103	31		T117	20
pkt_types[PidTypeSetupToken]	invalid_ep[0xf]	1181	1			T64	22		T103	23		T536	1
pkt_types[PidTypeSetupToken]	endpoints[0x0]	1679	1			T23	8		T24	1		T161	5
pkt_types[PidTypeSetupToken]	endpoints[0x1]	1773	1			T6	7		T157	3		T264	1
pkt_types[PidTypeSetupToken]	endpoints[0x2]	1893	1			T4	5		T162	1		T264	1
pkt_types[PidTypeSetupToken]	endpoints[0x3]	1993	1			T29	7		T4	4		T107	1
pkt_types[PidTypeSetupToken]	endpoints[0x4]	1683	1			T24	1		T4	1		T45	1
pkt_types[PidTypeSetupToken]	endpoints[0x5]	1781	1			T20	1		T24	1		T88	1
pkt_types[PidTypeSetupToken]	endpoints[0x6]	1701	1			T6	1		T64	27		T65	2
pkt_types[PidTypeSetupToken]	endpoints[0x7]	1850	1			T1	1		T46	1		T64	23
pkt_types[PidTypeSetupToken]	endpoints[0x8]	1744	1			T24	2		T165	1		T64	28
pkt_types[PidTypeSetupToken]	endpoints[0x9]	1676	1			T24	1		T4	2		T168	1
pkt_types[PidTypeSetupToken]	endpoints[0xa]	1903	1			T44	1		T64	19		T65	1
pkt_types[PidTypeSetupToken]	endpoints[0xb]	1750	1			T20	3		T6	4		T247	1
pkt_types[PidTypeOutToken]	invalid_ep[0xc]	1763	1			T4	10		T64	32		T185	9
pkt_types[PidTypeOutToken]	invalid_ep[0xd]	1630	1			T4	8		T64	18		T185	6
pkt_types[PidTypeOutToken]	invalid_ep[0xe]	1694	1			T4	5		T64	17		T185	10
pkt_types[PidTypeOutToken]	invalid_ep[0xf]	1696	1			T24	1		T4	8		T64	30
pkt_types[PidTypeOutToken]	endpoints[0x0]	5197	1			T21	3		T28	1		T33	1
pkt_types[PidTypeOutToken]	endpoints[0x1]	3889	1			T24	1		T28	1		T49	8
pkt_types[PidTypeOutToken]	endpoints[0x2]	6218	1			T21	2		T28	1		T30	11
pkt_types[PidTypeOutToken]	endpoints[0x3]	5817	1			T17	1		T21	1		T28	1
pkt_types[PidTypeOutToken]	endpoints[0x4]	5910	1			T21	1		T28	1		T70	11
pkt_types[PidTypeOutToken]	endpoints[0x5]	4651	1			T20	7		T21	1		T28	1
pkt_types[PidTypeOutToken]	endpoints[0x6]	7367	1			T21	2		T28	1		T7	1
pkt_types[PidTypeOutToken]	endpoints[0x7]	9033	1			T21	3		T28	1		T160	1
pkt_types[PidTypeOutToken]	endpoints[0x8]	5168	1			T20	1		T28	1		T118	1
pkt_types[PidTypeOutToken]	endpoints[0x9]	5023	1			T21	2		T24	1		T28	1
pkt_types[PidTypeOutToken]	endpoints[0xa]	5071	1			T2	1		T28	1		T44	1
pkt_types[PidTypeOutToken]	endpoints[0xb]	8042	1			T18	6		T20	1		T21	2
pkt_types[PidTypeInToken]	invalid_ep[0xc]	1121	1			T64	23		T103	15		T536	1
pkt_types[PidTypeInToken]	invalid_ep[0xd]	1093	1			T64	24		T103	18		T117	18
pkt_types[PidTypeInToken]	invalid_ep[0xe]	1126	1			T64	22		T103	21		T536	1
pkt_types[PidTypeInToken]	invalid_ep[0xf]	1122	1			T115	1		T64	24		T103	10
pkt_types[PidTypeInToken]	endpoints[0x0]	4634	1			T21	4		T24	1		T28	1
pkt_types[PidTypeInToken]	endpoints[0x1]	5127	1			T28	1		T6	8		T157	2
pkt_types[PidTypeInToken]	endpoints[0x2]	5590	1			T24	1		T28	1		T32	1
pkt_types[PidTypeInToken]	endpoints[0x3]	5232	1			T21	2		T28	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0x4]	5384	1			T21	4		T28	1		T108	11
pkt_types[PidTypeInToken]	endpoints[0x5]	4892	1			T20	4		T28	1		T159	1
pkt_types[PidTypeInToken]	endpoints[0x6]	4610	1			T28	1		T7	1		T34	1
pkt_types[PidTypeInToken]	endpoints[0x7]	5132	1			T20	1		T21	1		T24	1
pkt_types[PidTypeInToken]	endpoints[0x8]	4419	1			T20	1		T21	2		T24	1
pkt_types[PidTypeInToken]	endpoints[0x9]	4946	1			T21	2		T28	1		T4	6
pkt_types[PidTypeInToken]	endpoints[0xa]	4817	1			T21	1		T24	1		T28	1
pkt_types[PidTypeInToken]	endpoints[0xb]	4449	1			T18	7		T20	1		T21	1