Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	169871	1			T1	7		T2	3		T3	4
all_values[1]	169871	1			T1	7		T2	3		T3	4
all_values[2]	169871	1			T1	7		T2	3		T3	4
all_values[3]	169871	1			T1	7		T2	3		T3	4
all_values[4]	169871	1			T1	7		T2	3		T3	4
all_values[5]	169871	1			T1	7		T2	3		T3	4
all_values[6]	169871	1			T1	7		T2	3		T3	4
all_values[7]	169871	1			T1	7		T2	3		T3	4
all_values[8]	169871	1			T1	7		T2	3		T3	4
all_values[9]	169871	1			T1	7		T2	3		T3	4
all_values[10]	169871	1			T1	7		T2	3		T3	4
all_values[11]	169871	1			T1	7		T2	3		T3	4
all_values[12]	169871	1			T1	7		T2	3		T3	4
all_values[13]	169871	1			T1	7		T2	3		T3	4
all_values[14]	169871	1			T1	7		T2	3		T3	4
all_values[15]	169871	1			T1	7		T2	3		T3	4
all_values[16]	169871	1			T1	7		T2	3		T3	4
all_values[17]	169871	1			T1	7		T2	3		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5426119

1

T1

219

T2

94

T3

128

auto[1]

9753

1

T1

5

T2

2

T28

3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4662693

1

T1

210

T2

85

T3

110

auto[1]

773179

1

T1

14

T2

11

T3

18

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	141960	1			T1	7		T2	3		T3	3
all_values[0]	auto[0]	auto[1]	24571	1			T3	1		T28	3		T30	2
all_values[0]	auto[1]	auto[0]	3220	1			T49	3		T51	3		T52	3
all_values[0]	auto[1]	auto[1]	120	1			T400	1		T401	1		T402	1
all_values[1]	auto[0]	auto[0]	165393	1			T1	7		T2	3		T3	4
all_values[1]	auto[0]	auto[1]	3086	1			T29	2		T32	2		T36	1
all_values[1]	auto[1]	auto[0]	521	1			T33	2		T35	2		T17	2
all_values[1]	auto[1]	auto[1]	871	1			T33	1		T35	12		T17	1
all_values[2]	auto[0]	auto[0]	4408	1			T1	6		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	165196	1			T1	1		T2	2		T3	3
all_values[2]	auto[1]	auto[0]	125	1			T41	1		T64	1		T65	1
all_values[2]	auto[1]	auto[1]	142	1			T41	1		T64	1		T65	1
all_values[3]	auto[0]	auto[0]	167981	1			T1	7		T2	3		T3	4
all_values[3]	auto[0]	auto[1]	297	1			T66	1		T67	1		T68	1
all_values[3]	auto[1]	auto[0]	1535	1			T66	1429		T221	4		T223	2
all_values[3]	auto[1]	auto[1]	58	1			T66	1		T223	1		T224	2
all_values[4]	auto[0]	auto[0]	4417	1			T1	6		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	165308	1			T1	1		T2	2		T3	3
all_values[4]	auto[1]	auto[0]	82	1			T50	1		T221	1		T223	2
all_values[4]	auto[1]	auto[1]	64	1			T50	1		T221	6		T223	1
all_values[5]	auto[0]	auto[0]	169349	1			T1	7		T2	3		T3	4
all_values[5]	auto[0]	auto[1]	349	1			T7	1		T18	1		T8	1
all_values[5]	auto[1]	auto[0]	100	1			T221	3		T224	3		T291	3
all_values[5]	auto[1]	auto[1]	73	1			T221	1		T223	3		T224	1
all_values[6]	auto[0]	auto[0]	169423	1			T1	7		T2	3		T3	4
all_values[6]	auto[0]	auto[1]	223	1			T7	1		T9	1		T96	1
all_values[6]	auto[1]	auto[0]	107	1			T221	1		T223	5		T291	3
all_values[6]	auto[1]	auto[1]	118	1			T20	1		T69	1		T70	1
all_values[7]	auto[0]	auto[0]	115249	1			T2	3		T41	2		T42	2
all_values[7]	auto[0]	auto[1]	54459	1			T1	7		T3	4		T28	6
all_values[7]	auto[1]	auto[0]	101	1			T53	2		T221	1		T224	3
all_values[7]	auto[1]	auto[1]	62	1			T53	1		T221	1		T223	2
all_values[8]	auto[0]	auto[0]	168945	1			T1	7		T2	3		T3	4
all_values[8]	auto[0]	auto[1]	244	1			T55	2		T168	2		T302	2
all_values[8]	auto[1]	auto[0]	595	1			T21	10		T56	10		T57	10
all_values[8]	auto[1]	auto[1]	87	1			T21	1		T56	1		T57	1
all_values[9]	auto[0]	auto[0]	169610	1			T1	2		T2	3		T3	4
all_values[9]	auto[0]	auto[1]	69	1			T221	1		T223	3		T224	2
all_values[9]	auto[1]	auto[0]	115	1			T1	3		T62	3		T63	3
all_values[9]	auto[1]	auto[1]	77	1			T1	2		T62	2		T63	2
all_values[10]	auto[0]	auto[0]	169311	1			T1	7		T2	3		T3	4
all_values[10]	auto[0]	auto[1]	383	1			T32	1		T34	2		T60	1
all_values[10]	auto[1]	auto[0]	112	1			T221	4		T223	1		T224	2
all_values[10]	auto[1]	auto[1]	65	1			T223	2		T224	2		T300	2
all_values[11]	auto[0]	auto[0]	168918	1			T1	7		T2	2		T3	4
all_values[11]	auto[0]	auto[1]	700	1			T2	1		T37	4		T39	4
all_values[11]	auto[1]	auto[0]	154	1			T19	1		T73	1		T74	1
all_values[11]	auto[1]	auto[1]	99	1			T19	1		T73	1		T74	1
all_values[12]	auto[0]	auto[0]	169491	1			T1	7		T2	3		T3	4
all_values[12]	auto[0]	auto[1]	205	1			T76	1		T78	1		T79	1
all_values[12]	auto[1]	auto[0]	116	1			T23	2		T75	2		T77	2
all_values[12]	auto[1]	auto[1]	59	1			T23	1		T75	1		T77	1
all_values[13]	auto[0]	auto[0]	169543	1			T1	7		T2	1		T3	4
all_values[13]	auto[0]	auto[1]	66	1			T76	1		T78	1		T79	1
all_values[13]	auto[1]	auto[0]	157	1			T2	1		T80	1		T81	1
all_values[13]	auto[1]	auto[1]	105	1			T2	1		T80	1		T81	1
all_values[14]	auto[0]	auto[0]	35615	1			T1	7		T2	3		T3	4
all_values[14]	auto[0]	auto[1]	134090	1			T41	1		T43	1		T61	1
all_values[14]	auto[1]	auto[0]	109	1			T221	4		T223	4		T224	5
all_values[14]	auto[1]	auto[1]	57	1			T221	1		T223	3		T224	1
all_values[15]	auto[0]	auto[0]	4433	1			T1	6		T2	1		T3	1
all_values[15]	auto[0]	auto[1]	165268	1			T1	1		T2	2		T3	3
all_values[15]	auto[1]	auto[0]	109	1			T221	3		T223	5		T224	2
all_values[15]	auto[1]	auto[1]	61	1			T221	2		T223	1		T224	1
all_values[16]	auto[0]	auto[0]	168804	1			T1	7		T2	3		T3	4
all_values[16]	auto[0]	auto[1]	861	1			T30	1		T32	1		T72	1
all_values[16]	auto[1]	auto[0]	122	1			T37	4		T39	4		T71	4
all_values[16]	auto[1]	auto[1]	84	1			T37	4		T39	4		T71	4
all_values[17]	auto[0]	auto[0]	114160	1			T1	5		T28	1		T42	2
all_values[17]	auto[0]	auto[1]	55540	1			T1	2		T2	3		T3	4
all_values[17]	auto[1]	auto[0]	109	1			T28	2		T24	2		T59	2
all_values[17]	auto[1]	auto[1]	62	1			T28	1		T24	1		T59	1