Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.39 98.22 96.08 97.44 94.92 98.38 98.17 98.55


Total tests in report: 3905
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
61.69 61.69 85.31 85.31 61.82 61.82 55.44 55.44 47.46 47.46 76.77 76.77 90.85 90.85 14.21 14.21 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3881319653
69.95 8.26 89.29 3.98 72.36 10.54 82.20 26.76 47.46 0.00 87.02 10.24 91.26 0.41 20.09 5.88 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.403264552
74.39 4.43 91.68 2.39 75.95 3.59 84.65 2.45 57.63 10.17 89.55 2.53 93.29 2.03 27.96 7.87 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.1960198952
78.01 3.62 92.68 1.00 80.69 4.73 86.14 1.49 64.41 6.78 91.83 2.28 93.29 0.00 37.01 9.05 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.3806302233
80.31 2.30 93.38 0.70 80.80 0.12 88.49 2.35 64.41 0.00 91.83 0.00 93.50 0.20 49.77 12.76 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_intr_test.3159437493
82.12 1.81 94.86 1.48 84.54 3.73 89.13 0.64 64.41 0.00 95.02 3.19 93.50 0.00 53.39 3.62 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2040826768
83.72 1.60 94.94 0.08 84.85 0.31 89.34 0.21 71.19 6.78 95.15 0.12 93.50 0.00 57.10 3.71 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.3559971300
84.86 1.14 95.03 0.09 86.77 1.93 90.62 1.28 71.19 0.00 95.27 0.12 93.50 0.00 61.63 4.52 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.680905513
85.83 0.97 95.79 0.76 87.94 1.17 91.47 0.85 71.19 0.00 95.31 0.04 94.51 1.02 64.62 2.99 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_tl_errors.2980454673
86.60 0.77 96.02 0.23 88.65 0.71 91.47 0.00 74.58 3.39 95.44 0.12 94.51 0.00 65.52 0.90 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.1111222305
87.28 0.68 96.23 0.21 88.92 0.26 92.11 0.64 77.97 3.39 95.69 0.25 94.51 0.00 65.52 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.1279451067
87.95 0.67 96.25 0.02 88.99 0.07 95.95 3.84 77.97 0.00 95.73 0.04 94.72 0.20 66.06 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2935406743
88.50 0.55 96.42 0.17 89.08 0.10 95.95 0.00 81.36 3.39 95.89 0.17 94.72 0.00 66.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2157063687
88.98 0.48 96.42 0.00 89.08 0.00 95.95 0.00 84.75 3.39 95.89 0.00 94.72 0.00 66.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/35.usbdev_tx_rx_disruption.1455710115
89.46 0.48 96.76 0.34 89.27 0.19 95.95 0.00 84.75 0.00 95.89 0.00 97.56 2.85 66.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_aliasing.2946406223
89.89 0.43 97.50 0.74 90.39 1.12 95.95 0.00 84.75 0.00 97.06 1.16 97.56 0.00 66.06 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.1913671664
90.26 0.36 97.50 0.00 90.39 0.00 95.95 0.00 84.75 0.00 97.06 0.00 97.56 0.00 68.60 2.53 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/6.usbdev_intr_test.3452918854
90.61 0.36 97.76 0.27 91.32 0.93 96.16 0.21 84.75 0.00 97.59 0.54 97.56 0.00 69.14 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.3848979322
90.96 0.34 97.76 0.00 91.37 0.05 96.38 0.21 86.44 1.69 97.59 0.00 97.56 0.00 69.59 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.974365043
91.29 0.34 97.82 0.06 92.96 1.59 96.38 0.00 86.44 0.00 97.68 0.08 97.56 0.00 70.23 0.63 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1975355314
91.59 0.29 97.84 0.02 93.08 0.12 96.38 0.00 88.14 1.69 97.72 0.04 97.56 0.00 70.41 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_stress_usb_traffic.2246870686
91.85 0.26 97.88 0.04 93.08 0.00 96.38 0.00 89.83 1.69 97.80 0.08 97.56 0.00 70.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2623081646
92.10 0.26 97.90 0.02 93.13 0.05 96.38 0.00 91.53 1.69 97.84 0.04 97.56 0.00 70.41 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.2309614
92.36 0.25 97.91 0.02 93.22 0.10 96.38 0.00 91.53 0.00 97.88 0.04 97.56 0.00 72.04 1.63 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_intg_err.3281172392
92.61 0.25 97.91 0.00 93.27 0.05 96.38 0.00 91.53 0.00 97.88 0.00 97.56 0.00 73.76 1.72 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_device_address.1689122852
92.85 0.24 97.91 0.00 93.27 0.00 96.38 0.00 93.22 1.69 97.88 0.00 97.56 0.00 73.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/224.usbdev_tx_rx_disruption.2544564527
93.10 0.24 97.91 0.00 93.27 0.00 96.38 0.00 94.92 1.69 97.88 0.00 97.56 0.00 73.76 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/388.usbdev_tx_rx_disruption.2285171685
93.30 0.20 97.91 0.00 93.41 0.14 96.38 0.00 94.92 0.00 97.97 0.08 97.76 0.20 74.75 1.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.952648368
93.46 0.16 97.93 0.02 93.77 0.36 96.70 0.32 94.92 0.00 98.01 0.04 97.76 0.00 75.11 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.2672639484
93.61 0.16 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 76.20 1.09 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/49.usbdev_endpoint_types.801264495
93.74 0.13 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 77.10 0.90 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/11.usbdev_device_address.410788197
93.87 0.13 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 78.01 0.90 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/15.usbdev_endpoint_types.1118922503
93.97 0.10 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 78.73 0.72 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_intr_test.2708235148
94.08 0.10 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 79.46 0.72 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/197.usbdev_endpoint_types.1256933852
94.18 0.10 97.93 0.00 93.77 0.00 96.70 0.00 94.92 0.00 98.01 0.00 97.76 0.00 80.18 0.72 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/33.usbdev_endpoint_types.634542294
94.28 0.10 97.93 0.00 93.82 0.05 96.91 0.21 94.92 0.00 98.01 0.00 97.76 0.00 80.63 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.4124185787
94.38 0.10 97.93 0.00 93.86 0.05 97.12 0.21 94.92 0.00 98.01 0.00 97.76 0.00 81.09 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3051580359
94.48 0.10 97.97 0.04 93.98 0.12 97.12 0.00 94.92 0.00 98.09 0.08 97.76 0.00 81.54 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.491486305
94.57 0.09 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 82.17 0.63 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/136.usbdev_endpoint_types.3128328413
94.65 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 82.71 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/108.usbdev_endpoint_types.3489554924
94.73 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 83.26 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/111.usbdev_endpoint_types.201874752
94.81 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 83.80 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/140.usbdev_endpoint_types.3823758255
94.88 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 84.34 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/26.usbdev_endpoint_types.412586455
94.96 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 84.89 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/48.usbdev_endpoint_types.4250688392
95.04 0.08 97.97 0.00 93.98 0.00 97.12 0.00 94.92 0.00 98.09 0.00 97.76 0.00 85.43 0.54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/7.usbdev_data_toggle_restore.2437405314
95.11 0.08 98.03 0.06 94.01 0.02 97.12 0.00 94.92 0.00 98.18 0.08 97.76 0.00 85.79 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/15.usbdev_fifo_levels.1345215680
95.18 0.06 98.03 0.00 94.01 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.76 0.00 86.24 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/12.usbdev_endpoint_types.21889475
95.24 0.06 98.03 0.00 94.01 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.76 0.00 86.70 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/144.usbdev_endpoint_types.1020160152
95.31 0.06 98.03 0.00 94.01 0.00 97.12 0.00 94.92 0.00 98.18 0.00 97.76 0.00 87.15 0.45 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/41.usbdev_endpoint_types.3897912728
95.37 0.06 98.09 0.06 94.03 0.02 97.12 0.00 94.92 0.00 98.18 0.00 97.76 0.00 87.51 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2253427460
95.43 0.06 98.09 0.00 94.24 0.21 97.12 0.00 94.92 0.00 98.18 0.00 97.97 0.20 87.51 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.3561422686
95.49 0.06 98.09 0.00 94.34 0.10 97.12 0.00 94.92 0.00 98.22 0.04 97.97 0.00 87.78 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.2504573942
95.54 0.05 98.09 0.00 94.34 0.00 97.12 0.00 94.92 0.00 98.22 0.00 97.97 0.00 88.14 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/12.usbdev_device_address.2416781294
95.59 0.05 98.09 0.00 94.34 0.00 97.12 0.00 94.92 0.00 98.22 0.00 97.97 0.00 88.51 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/152.usbdev_endpoint_types.1826580576
95.64 0.05 98.09 0.00 94.34 0.00 97.12 0.00 94.92 0.00 98.22 0.00 97.97 0.00 88.87 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/167.usbdev_endpoint_types.4193499275
95.70 0.05 98.09 0.00 94.34 0.00 97.12 0.00 94.92 0.00 98.22 0.00 97.97 0.00 89.23 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/183.usbdev_endpoint_types.4052608569
95.75 0.05 98.09 0.00 94.34 0.00 97.12 0.00 94.92 0.00 98.22 0.00 97.97 0.00 89.59 0.36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/55.usbdev_endpoint_types.4172228530
95.80 0.05 98.14 0.06 94.41 0.07 97.33 0.21 94.92 0.00 98.22 0.00 97.97 0.00 89.59 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3070311032
95.84 0.04 98.14 0.00 94.53 0.12 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 89.77 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.2450353260
95.88 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 90.05 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_intg_err.534344075
95.92 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 90.32 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1670098675
95.96 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 90.59 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/139.usbdev_endpoint_types.3629367545
95.99 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 90.86 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/153.usbdev_endpoint_types.3281330014
96.03 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 91.13 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/173.usbdev_endpoint_types.3084717427
96.07 0.04 98.14 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.22 0.00 97.97 0.00 91.40 0.27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/97.usbdev_endpoint_types.1494158985
96.11 0.03 98.16 0.02 94.53 0.00 97.33 0.00 94.92 0.00 98.26 0.04 97.97 0.00 91.58 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.1848862337
96.14 0.03 98.16 0.00 94.53 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.20 91.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_rw.4106274858
96.16 0.03 98.16 0.00 94.72 0.19 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 91.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_errors.1911541507
96.19 0.03 98.16 0.00 94.91 0.19 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 91.58 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.3938366580
96.22 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 91.76 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_intr_test.1990627338
96.24 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 91.95 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.1229915021
96.27 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 92.13 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.420098204
96.29 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 92.31 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/101.usbdev_endpoint_types.1732929584
96.32 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 92.49 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/169.usbdev_endpoint_types.1149089408
96.35 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 92.67 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/23.usbdev_rx_full.2155217350
96.37 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 92.85 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/37.usbdev_endpoint_types.130627516
96.40 0.03 98.16 0.00 94.91 0.00 97.33 0.00 94.92 0.00 98.26 0.00 98.17 0.00 93.03 0.18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/50.usbdev_endpoint_types.8407449
96.42 0.02 98.20 0.04 94.91 0.00 97.33 0.00 94.92 0.00 98.30 0.04 98.17 0.00 93.12 0.09 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.3334191063
96.44 0.02 98.20 0.00 95.05 0.14 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.12 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/4.usbdev_rand_bus_resets.149585403
96.46 0.02 98.20 0.00 95.10 0.05 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.21 0.09 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_low_speed_traffic.996693290
96.48 0.02 98.20 0.00 95.22 0.12 97.33 0.00 94.92 0.00 98.30 0.00 98.17 0.00 93.21 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/12.usbdev_phy_pins_sense.1194317030
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97.38 0.01 98.22 0.00 96.00 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/35.usbdev_nak_trans.3080653671
97.39 0.01 98.22 0.00 96.03 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/38.usbdev_nak_trans.810710049
97.39 0.01 98.22 0.00 96.05 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/6.usbdev_nak_trans.487042303
97.39 0.01 98.22 0.00 96.08 0.02 97.44 0.00 94.92 0.00 98.38 0.00 98.17 0.00 98.55 0.00 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/6.usbdev_stress_usb_traffic.3301552544

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_bit_bash.582883201
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3505532425
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.891630681
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_partial_access.38803703
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_mem_walk.1951799938
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1882059782
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/0.usbdev_tl_intg_err.2461395658
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_aliasing.2826272382
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_bit_bash.693613695
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_hw_reset.1314407543
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.2011681898
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_csr_rw.3030610736
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_intr_test.1605009574
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_partial_access.2135794605
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_mem_walk.3663247728
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.3034039251
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.190564101
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_csr_rw.374302825
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.1856674946
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_errors.1294403370
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/10.usbdev_tl_intg_err.1881941011
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3082864102
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_csr_rw.3507895150
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_intr_test.4103191679
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.368080478
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_errors.672399090
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/11.usbdev_tl_intg_err.326075219
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.109020917
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_csr_rw.840803133
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.872970658
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/12.usbdev_tl_errors.1492951099
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.524235802
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_csr_rw.1939321847
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_intr_test.1617068670
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.328434192
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_errors.1304788816
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/13.usbdev_tl_intg_err.551140912
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.880751508
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_csr_rw.2058047866
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_intr_test.3387491423
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.518973130
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_errors.4084883788
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/14.usbdev_tl_intg_err.3892348966
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.2496327997
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_csr_rw.3869191622
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_intr_test.2406626183
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3154010828
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_errors.367311978
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/15.usbdev_tl_intg_err.4134648441
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.4237727176
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_csr_rw.2566857537
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_intr_test.2021372868
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3592266981
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_errors.1722756756
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/16.usbdev_tl_intg_err.1511193548
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.731117959
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_csr_rw.377820862
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_intr_test.1225664373
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1096297874
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_errors.413670575
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/17.usbdev_tl_intg_err.1819393070
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2932630605
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_csr_rw.2226329371
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_intr_test.4209706897
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.2987152405
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_errors.517630079
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/18.usbdev_tl_intg_err.2799828431
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.278323036
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_csr_rw.1977451468
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_intr_test.3509401750
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1933041375
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/19.usbdev_tl_errors.47603896
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_aliasing.2128437817
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_bit_bash.988718202
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3593406292
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1592659839
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_csr_rw.3423780437
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_intr_test.687388321
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_partial_access.858048116
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_mem_walk.2896951987
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.1471141609
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/2.usbdev_tl_errors.3375376581
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/20.usbdev_intr_test.1901479682
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/21.usbdev_intr_test.456789512
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/22.usbdev_intr_test.3259318138
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/23.usbdev_intr_test.3888177267
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/24.usbdev_intr_test.2339349094
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/25.usbdev_intr_test.1511496168
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/26.usbdev_intr_test.1966829313
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/27.usbdev_intr_test.2711450328
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/28.usbdev_intr_test.2728800838
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/29.usbdev_intr_test.1972576490
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_aliasing.2266457567
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3197625881
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_hw_reset.259163254
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3861316404
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_csr_rw.3912636066
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_intr_test.1203908971
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_partial_access.1494392942
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_mem_walk.3605873861
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3692373170
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_errors.4140002320
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/3.usbdev_tl_intg_err.700267385
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/30.usbdev_intr_test.3729581615
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/31.usbdev_intr_test.1253834103
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/32.usbdev_intr_test.3420289697
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/33.usbdev_intr_test.1718404243
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/34.usbdev_intr_test.882289695
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/35.usbdev_intr_test.3013723457
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/36.usbdev_intr_test.4215551883
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/37.usbdev_intr_test.3091721727
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/38.usbdev_intr_test.1153562794
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/39.usbdev_intr_test.1528878164
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_aliasing.808224557
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1064082847
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_hw_reset.1900943003
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.152866369
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_csr_rw.1697782495
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_intr_test.2388261030
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_partial_access.1277547406
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_mem_walk.3868855128
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.4189693833
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_errors.1537192367
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/4.usbdev_tl_intg_err.3343576920
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/40.usbdev_intr_test.1479905710
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/41.usbdev_intr_test.3695380829
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/42.usbdev_intr_test.3263386887
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/43.usbdev_intr_test.1155005813
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/44.usbdev_intr_test.2491397142
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/45.usbdev_intr_test.2498754604
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/46.usbdev_intr_test.4044100188
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/47.usbdev_intr_test.4211325916
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/48.usbdev_intr_test.4111455083
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/49.usbdev_intr_test.1746931980
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1223254565
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_csr_rw.533874639
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_intr_test.2676588285
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1316429321
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_max_non_iso_usb_traffic.3397969443
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_min_inter_pkt_delay.4095833660
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_phy_pins_sense.3481413419
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_pkt_received.1667415791
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/9.usbdev_resume_link_active.1844727862
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/96.usbdev_endpoint_types.1006214298
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/98.usbdev_endpoint_types.1223476865
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/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/99.usbdev_endpoint_types.873681940
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Total test records in report: 3905
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TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_av_overflow.3938366580 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:05 PM UTC 24 131530157 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_bitstuff_err.4124185787 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:05 PM UTC 24 176754548 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_av_buffer.2716416385 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:06 PM UTC 24 212932677 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_av_empty.487774550 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:06 PM UTC 24 175723987 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_enable.2057674776 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:08 PM UTC 24 48980345 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_clear.3881319653 Sep 01 12:44:05 PM UTC 24 Sep 01 12:44:08 PM UTC 24 399680401 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_disconnected.974365043 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:08 PM UTC 24 138006658 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_types.2985571148 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:09 PM UTC 24 343372422 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_levels.1848862337 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:09 PM UTC 24 262839523 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_disable_endpoint.403264552 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:09 PM UTC 24 1146465750 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_in_stall.1508221608 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:10 PM UTC 24 184518961 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_data_toggle_restore.1111222305 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:10 PM UTC 24 738421102 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_in_trans.2534486089 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:11 PM UTC 24 186192849 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_in_err.1795155610 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:11 PM UTC 24 250750674 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_endpoint_access.2040826768 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:11 PM UTC 24 750564567 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_in_iso.1815658371 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:11 PM UTC 24 206586735 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.491486305 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:12 PM UTC 24 510814516 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_reset.2618868847 Sep 01 12:44:09 PM UTC 24 Sep 01 12:44:12 PM UTC 24 186396637 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_fifo_rst.2027411509 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:12 PM UTC 24 454211800 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_out_err.1660987224 Sep 01 12:44:09 PM UTC 24 Sep 01 12:44:13 PM UTC 24 497541207 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_out_transaction.815230694 Sep 01 12:44:11 PM UTC 24 Sep 01 12:44:14 PM UTC 24 199470567 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_max_length_in_transaction.203099450 Sep 01 12:44:11 PM UTC 24 Sep 01 12:44:14 PM UTC 24 240969040 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_out_transaction.3814077690 Sep 01 12:44:12 PM UTC 24 Sep 01 12:44:15 PM UTC 24 138135304 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_min_length_in_transaction.825362094 Sep 01 12:44:12 PM UTC 24 Sep 01 12:44:15 PM UTC 24 151789257 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_nak_trans.2974083878 Sep 01 12:44:13 PM UTC 24 Sep 01 12:44:15 PM UTC 24 176638359 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_out_stall.3467780679 Sep 01 12:44:14 PM UTC 24 Sep 01 12:44:16 PM UTC 24 185886559 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_out_iso.3963385126 Sep 01 12:44:14 PM UTC 24 Sep 01 12:44:16 PM UTC 24 176041870 ps
T71 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1402357469 Sep 01 12:44:12 PM UTC 24 Sep 01 12:44:17 PM UTC 24 486108065 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pending_in_trans.3859111282 Sep 01 12:44:15 PM UTC 24 Sep 01 12:44:17 PM UTC 24 159954519 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_out_trans_nak.475217303 Sep 01 12:44:15 PM UTC 24 Sep 01 12:44:17 PM UTC 24 198429301 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.3491499187 Sep 01 12:44:16 PM UTC 24 Sep 01 12:44:18 PM UTC 24 152980442 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_pinflip.2009659352 Sep 01 12:44:16 PM UTC 24 Sep 01 12:44:19 PM UTC 24 240159835 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rx_dp_dn.1598013650 Sep 01 12:44:16 PM UTC 24 Sep 01 12:44:19 PM UTC 24 205414158 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_rand_bus_type.468295486 Sep 01 12:44:16 PM UTC 24 Sep 01 12:44:19 PM UTC 24 245766191 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_usb_ref_disable.1243490997 Sep 01 12:44:17 PM UTC 24 Sep 01 12:44:20 PM UTC 24 141842820 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2696715239 Sep 01 12:44:17 PM UTC 24 Sep 01 12:44:20 PM UTC 24 200391169 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.2157063687 Sep 01 12:44:17 PM UTC 24 Sep 01 12:44:20 PM UTC 24 332994588 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_phy_pins_sense.1913671664 Sep 01 12:44:19 PM UTC 24 Sep 01 12:44:21 PM UTC 24 37923929 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_received.1670098675 Sep 01 12:44:19 PM UTC 24 Sep 01 12:44:21 PM UTC 24 199948572 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_in_transaction.4176990577 Sep 01 12:44:20 PM UTC 24 Sep 01 12:44:22 PM UTC 24 226595755 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_random_length_out_transaction.2183139330 Sep 01 12:44:20 PM UTC 24 Sep 01 12:44:22 PM UTC 24 190385573 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_reset.2623081646 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:23 PM UTC 24 14375471416 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_sent.3382546166 Sep 01 12:44:20 PM UTC 24 Sep 01 12:44:23 PM UTC 24 246141384 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_suspend.3592712263 Sep 01 12:44:10 PM UTC 24 Sep 01 12:44:24 PM UTC 24 4339043649 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_disconnect.1960198952 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:24 PM UTC 24 10226149271 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rx_crc_err.3051580359 Sep 01 12:44:22 PM UTC 24 Sep 01 12:44:25 PM UTC 24 215727018 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_link_resume.3559971300 Sep 01 12:44:09 PM UTC 24 Sep 01 12:44:25 PM UTC 24 8465342721 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rx_full.3848979322 Sep 01 12:44:22 PM UTC 24 Sep 01 12:44:25 PM UTC 24 245068691 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_setup_stage.4044808620 Sep 01 12:44:24 PM UTC 24 Sep 01 12:44:26 PM UTC 24 156681419 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rx_pid_err.4250076105 Sep 01 12:44:24 PM UTC 24 Sep 01 12:44:26 PM UTC 24 194246276 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_av_empty.3714628118 Sep 01 12:44:32 PM UTC 24 Sep 01 12:44:34 PM UTC 24 179176850 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority_over_stall_response.3847179759 Sep 01 12:44:24 PM UTC 24 Sep 01 12:44:26 PM UTC 24 317186424 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_device_timeout.2150837217 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:27 PM UTC 24 2524295127 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_host_lost.2408150913 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:27 PM UTC 24 4215917097 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_setup_trans_ignored.4097761107 Sep 01 12:44:25 PM UTC 24 Sep 01 12:44:27 PM UTC 24 146106469 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_setup_priority.2504573942 Sep 01 12:44:24 PM UTC 24 Sep 01 12:44:27 PM UTC 24 418548931 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stall_trans.788527040 Sep 01 12:44:26 PM UTC 24 Sep 01 12:44:28 PM UTC 24 156830320 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stall_priority_over_nak.3334191063 Sep 01 12:44:26 PM UTC 24 Sep 01 12:44:29 PM UTC 24 188449176 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_smoke.4070670025 Sep 01 12:44:26 PM UTC 24 Sep 01 12:44:29 PM UTC 24 221396136 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_invalid_sync.380091388 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:31 PM UTC 24 2399935964 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stream_len_max.1466497508 Sep 01 12:44:27 PM UTC 24 Sep 01 12:44:31 PM UTC 24 769428570 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_alert_test.3070311032 Sep 01 12:44:30 PM UTC 24 Sep 01 12:44:32 PM UTC 24 44982935 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_sec_cm.2935406743 Sep 01 12:44:29 PM UTC 24 Sep 01 12:44:32 PM UTC 24 499367355 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_min_inter_pkt_delay.4085693850 Sep 01 12:44:12 PM UTC 24 Sep 01 12:44:32 PM UTC 24 1628222832 ps
T110 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_tx_rx_disruption.2672639484 Sep 01 12:44:28 PM UTC 24 Sep 01 12:44:32 PM UTC 24 481531676 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_max_non_iso_usb_traffic.2825107384 Sep 01 12:44:11 PM UTC 24 Sep 01 12:44:33 PM UTC 24 1941399177 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_av_buffer.3192957970 Sep 01 12:44:31 PM UTC 24 Sep 01 12:44:33 PM UTC 24 159860201 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_av_overflow.3863506553 Sep 01 12:44:32 PM UTC 24 Sep 01 12:44:35 PM UTC 24 141137534 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_bitstuff_err.2717090454 Sep 01 12:44:32 PM UTC 24 Sep 01 12:44:35 PM UTC 24 221796399 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_clear.3069865073 Sep 01 12:44:33 PM UTC 24 Sep 01 12:44:37 PM UTC 24 618176537 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_enable.3181134681 Sep 01 12:44:36 PM UTC 24 Sep 01 12:44:38 PM UTC 24 31920306 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_disconnected.2130163742 Sep 01 12:44:36 PM UTC 24 Sep 01 12:44:38 PM UTC 24 136750682 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_iso_retraction.2524073557 Sep 01 12:44:08 PM UTC 24 Sep 01 12:44:39 PM UTC 24 4023627240 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_data_toggle_restore.420098204 Sep 01 12:44:33 PM UTC 24 Sep 01 12:44:40 PM UTC 24 1186573861 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_max_inter_pkt_delay.848826903 Sep 01 12:44:11 PM UTC 24 Sep 01 12:44:40 PM UTC 24 3172484513 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_access.873141901 Sep 01 12:44:36 PM UTC 24 Sep 01 12:44:41 PM UTC 24 694987899 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_disable_endpoint.1574817764 Sep 01 12:44:36 PM UTC 24 Sep 01 12:44:42 PM UTC 24 1080611349 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_endpoint_types.4291199 Sep 01 12:44:38 PM UTC 24 Sep 01 12:44:42 PM UTC 24 335606537 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_levels.25856971 Sep 01 12:44:39 PM UTC 24 Sep 01 12:44:42 PM UTC 24 250351566 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_fifo_rst.874575640 Sep 01 12:44:39 PM UTC 24 Sep 01 12:44:43 PM UTC 24 271261454 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_streaming_out.2788608611 Sep 01 12:44:27 PM UTC 24 Sep 01 12:44:44 PM UTC 24 2054248486 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_timeout_missing_host_handshake.2577675591 Sep 01 12:44:06 PM UTC 24 Sep 01 12:44:44 PM UTC 24 3431920614 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_in_iso.1745892636 Sep 01 12:44:43 PM UTC 24 Sep 01 12:44:46 PM UTC 24 222808190 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_in_stall.533793799 Sep 01 12:44:44 PM UTC 24 Sep 01 12:44:47 PM UTC 24 179113921 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_low_speed_traffic.3806302233 Sep 01 12:44:11 PM UTC 24 Sep 01 12:44:48 PM UTC 24 2443315347 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_spurious_pids_ignored.1169449212 Sep 01 12:44:26 PM UTC 24 Sep 01 12:44:48 PM UTC 24 1762231135 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_in_trans.4064605505 Sep 01 12:44:45 PM UTC 24 Sep 01 12:44:48 PM UTC 24 210379446 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_link_in_err.133852892 Sep 01 12:44:47 PM UTC 24 Sep 01 12:44:50 PM UTC 24 186437699 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_aon_wake_resume.990024938 Sep 01 12:44:03 PM UTC 24 Sep 01 12:44:52 PM UTC 24 28461606481 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_out_transaction.1814246252 Sep 01 12:44:49 PM UTC 24 Sep 01 12:44:52 PM UTC 24 191534680 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_max_length_in_transaction.3980708765 Sep 01 12:44:49 PM UTC 24 Sep 01 12:44:52 PM UTC 24 258608650 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_in_transaction.2393762890 Sep 01 12:44:53 PM UTC 24 Sep 01 12:44:55 PM UTC 24 169739423 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_min_length_out_transaction.2753051682 Sep 01 12:44:56 PM UTC 24 Sep 01 12:44:59 PM UTC 24 148085606 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_reset.1523709387 Sep 01 12:44:30 PM UTC 24 Sep 01 12:44:59 PM UTC 24 18940118581 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_pkt_buffer.952648368 Sep 01 12:44:19 PM UTC 24 Sep 01 12:44:59 PM UTC 24 9201344456 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_disconnect.2759630003 Sep 01 12:44:30 PM UTC 24 Sep 01 12:45:00 PM UTC 24 11096990328 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_link_suspend.549130840 Sep 01 12:44:48 PM UTC 24 Sep 01 12:45:00 PM UTC 24 4270622013 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_device_address.680905513 Sep 01 12:44:06 PM UTC 24 Sep 01 12:45:00 PM UTC 24 21048599909 ps
T126 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_nak_trans.2253427460 Sep 01 12:44:59 PM UTC 24 Sep 01 12:45:02 PM UTC 24 182252094 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_max_usb_traffic.3039673073 Sep 01 12:44:12 PM UTC 24 Sep 01 12:45:02 PM UTC 24 1852936018 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_out_iso.3757141019 Sep 01 12:45:00 PM UTC 24 Sep 01 12:45:03 PM UTC 24 169104676 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_out_stall.2837176827 Sep 01 12:45:00 PM UTC 24 Sep 01 12:45:03 PM UTC 24 169210551 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_out_trans_nak.680693010 Sep 01 12:45:00 PM UTC 24 Sep 01 12:45:03 PM UTC 24 200328624 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_timeout_missing_host_handshake.3084394238 Sep 01 12:44:35 PM UTC 24 Sep 01 12:45:04 PM UTC 24 1010844969 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_pending_in_trans.745080350 Sep 01 12:45:02 PM UTC 24 Sep 01 12:45:04 PM UTC 24 144729823 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_pinflip.3620267039 Sep 01 12:45:02 PM UTC 24 Sep 01 12:45:05 PM UTC 24 250219809 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_device_timeout.3808234246 Sep 01 12:44:35 PM UTC 24 Sep 01 12:45:05 PM UTC 24 1409073216 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_phy_pins_sense.708780776 Sep 01 12:45:03 PM UTC 24 Sep 01 12:45:05 PM UTC 24 35650754 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_usb_ref_disable.2744105944 Sep 01 12:45:03 PM UTC 24 Sep 01 12:45:06 PM UTC 24 136992170 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_phy_config_rand_bus_type.1098192734 Sep 01 12:45:03 PM UTC 24 Sep 01 12:45:06 PM UTC 24 241016700 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_resets.2450353260 Sep 01 12:44:21 PM UTC 24 Sep 01 12:45:07 PM UTC 24 3807857749 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_received.2139982877 Sep 01 12:45:04 PM UTC 24 Sep 01 12:45:07 PM UTC 24 215575984 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_sent.2166443020 Sep 01 12:45:06 PM UTC 24 Sep 01 12:45:09 PM UTC 24 211602259 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_out_transaction.3428239804 Sep 01 12:45:06 PM UTC 24 Sep 01 12:45:09 PM UTC 24 146210676 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_random_length_in_transaction.4065903722 Sep 01 12:45:06 PM UTC 24 Sep 01 12:45:09 PM UTC 24 164394289 ps
T73 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rx_crc_err.3581357600 Sep 01 12:45:08 PM UTC 24 Sep 01 12:45:10 PM UTC 24 162623013 ps
T75 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rx_pid_err.543828385 Sep 01 12:45:08 PM UTC 24 Sep 01 12:45:10 PM UTC 24 185986404 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rx_full.2007839129 Sep 01 12:45:08 PM UTC 24 Sep 01 12:45:11 PM UTC 24 252802581 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority_over_stall_response.833872402 Sep 01 12:45:09 PM UTC 24 Sep 01 12:45:12 PM UTC 24 208992118 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_setup_priority.2304217807 Sep 01 12:45:09 PM UTC 24 Sep 01 12:45:12 PM UTC 24 391378371 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_setup_stage.2662084193 Sep 01 12:45:10 PM UTC 24 Sep 01 12:45:12 PM UTC 24 165560272 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_setup_trans_ignored.3795708820 Sep 01 12:45:11 PM UTC 24 Sep 01 12:45:14 PM UTC 24 174012954 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_smoke.1003729528 Sep 01 12:45:11 PM UTC 24 Sep 01 12:45:14 PM UTC 24 286393782 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_resume_link_active.2309614 Sep 01 12:44:21 PM UTC 24 Sep 01 12:45:14 PM UTC 24 20192741351 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_stall_priority_over_nak.621075475 Sep 01 12:45:12 PM UTC 24 Sep 01 12:45:15 PM UTC 24 166083983 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_link_resume.1980605264 Sep 01 12:44:48 PM UTC 24 Sep 01 12:45:16 PM UTC 24 14361976790 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_stall_trans.3487047339 Sep 01 12:45:13 PM UTC 24 Sep 01 12:45:16 PM UTC 24 188979692 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_stream_len_max.91729819 Sep 01 12:45:15 PM UTC 24 Sep 01 12:45:19 PM UTC 24 664921438 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_pkt_buffer.441753154 Sep 01 12:45:04 PM UTC 24 Sep 01 12:45:53 PM UTC 24 17155589585 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_max_usb_traffic.1819531513 Sep 01 12:44:53 PM UTC 24 Sep 01 12:45:19 PM UTC 24 2297939169 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_alert_test.3781560399 Sep 01 12:45:17 PM UTC 24 Sep 01 12:45:19 PM UTC 24 95986295 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_tx_rx_disruption.3001613775 Sep 01 12:45:16 PM UTC 24 Sep 01 12:45:20 PM UTC 24 496891037 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_sec_cm.1247800850 Sep 01 12:45:17 PM UTC 24 Sep 01 12:45:20 PM UTC 24 318755719 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_av_buffer.1868124863 Sep 01 12:45:20 PM UTC 24 Sep 01 12:45:22 PM UTC 24 163866813 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_aon_wake_resume.3542888563 Sep 01 12:44:30 PM UTC 24 Sep 01 12:45:22 PM UTC 24 28771971300 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_av_empty.3197342535 Sep 01 12:45:20 PM UTC 24 Sep 01 12:45:23 PM UTC 24 152528567 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_av_overflow.2846727833 Sep 01 12:45:21 PM UTC 24 Sep 01 12:45:24 PM UTC 24 153904051 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_bitstuff_err.150086120 Sep 01 12:45:21 PM UTC 24 Sep 01 12:45:24 PM UTC 24 148872796 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_max_inter_pkt_delay.3203563740 Sep 01 12:44:49 PM UTC 24 Sep 01 12:45:26 PM UTC 24 3250382007 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_min_inter_pkt_delay.2198460640 Sep 01 12:44:53 PM UTC 24 Sep 01 12:45:27 PM UTC 24 2869211826 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_restore.3919266950 Sep 01 12:45:24 PM UTC 24 Sep 01 12:45:27 PM UTC 24 389383359 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_data_toggle_clear.696686406 Sep 01 12:45:24 PM UTC 24 Sep 01 12:45:27 PM UTC 24 442200000 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_enable.796230014 Sep 01 12:45:27 PM UTC 24 Sep 01 12:45:30 PM UTC 24 32517892 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_disconnected.3453196312 Sep 01 12:45:27 PM UTC 24 Sep 01 12:45:30 PM UTC 24 146029425 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_types.2716071104 Sep 01 12:45:29 PM UTC 24 Sep 01 12:45:32 PM UTC 24 323308503 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_disable_endpoint.2553246135 Sep 01 12:45:27 PM UTC 24 Sep 01 12:45:33 PM UTC 24 978796236 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_levels.2913897502 Sep 01 12:45:30 PM UTC 24 Sep 01 12:45:33 PM UTC 24 264916719 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_endpoint_access.491511 Sep 01 12:45:28 PM UTC 24 Sep 01 12:45:33 PM UTC 24 902405487 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_fifo_rst.1612913521 Sep 01 12:45:30 PM UTC 24 Sep 01 12:45:35 PM UTC 24 291274820 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rand_suspends.1699529301 Sep 01 12:45:06 PM UTC 24 Sep 01 12:45:39 PM UTC 24 5763725150 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_device_timeout.4137703922 Sep 01 12:45:25 PM UTC 24 Sep 01 12:45:42 PM UTC 24 1565260452 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_in_iso.1571630392 Sep 01 12:45:40 PM UTC 24 Sep 01 12:45:43 PM UTC 24 234396557 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_disconnect.3575619669 Sep 01 12:45:19 PM UTC 24 Sep 01 12:45:43 PM UTC 24 9992508673 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_in_stall.3229906984 Sep 01 12:45:43 PM UTC 24 Sep 01 12:45:46 PM UTC 24 152305481 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_in_trans.977120650 Sep 01 12:45:44 PM UTC 24 Sep 01 12:45:47 PM UTC 24 238564938 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_device_address.1690417609 Sep 01 12:44:33 PM UTC 24 Sep 01 12:45:47 PM UTC 24 37338984652 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_reset.1279451067 Sep 01 12:45:20 PM UTC 24 Sep 01 12:45:48 PM UTC 24 16356187904 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_link_in_err.406379003 Sep 01 12:45:46 PM UTC 24 Sep 01 12:45:49 PM UTC 24 169521386 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_resume_link_active.1189282883 Sep 01 12:45:06 PM UTC 24 Sep 01 12:45:52 PM UTC 24 20170447174 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_timeout_missing_host_handshake.1839650848 Sep 01 12:45:25 PM UTC 24 Sep 01 12:45:53 PM UTC 24 2482807010 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_in_transaction.2332297054 Sep 01 12:45:52 PM UTC 24 Sep 01 12:45:54 PM UTC 24 274494413 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_max_length_out_transaction.3532653958 Sep 01 12:45:53 PM UTC 24 Sep 01 12:45:55 PM UTC 24 206580755 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_in_transaction.1459066010 Sep 01 12:45:57 PM UTC 24 Sep 01 12:46:00 PM UTC 24 146829395 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_min_length_out_transaction.306180821 Sep 01 12:45:57 PM UTC 24 Sep 01 12:46:00 PM UTC 24 174733447 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_link_suspend.4151287998 Sep 01 12:45:48 PM UTC 24 Sep 01 12:46:02 PM UTC 24 5818690628 ps
T141 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_nak_trans.2721240400 Sep 01 12:46:01 PM UTC 24 Sep 01 12:46:04 PM UTC 24 204459323 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_out_iso.2150367768 Sep 01 12:46:01 PM UTC 24 Sep 01 12:46:04 PM UTC 24 205777026 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_max_non_iso_usb_traffic.924957336 Sep 01 12:44:51 PM UTC 24 Sep 01 12:46:05 PM UTC 24 1920887389 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_out_stall.69928475 Sep 01 12:46:03 PM UTC 24 Sep 01 12:46:06 PM UTC 24 154608850 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_out_trans_nak.2571173286 Sep 01 12:46:04 PM UTC 24 Sep 01 12:46:07 PM UTC 24 153065526 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_pending_in_trans.3124721688 Sep 01 12:46:05 PM UTC 24 Sep 01 12:46:08 PM UTC 24 182853046 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_pinflip.3299694457 Sep 01 12:46:05 PM UTC 24 Sep 01 12:46:09 PM UTC 24 320596814 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_resets.3316318104 Sep 01 12:45:06 PM UTC 24 Sep 01 12:46:09 PM UTC 24 2681702187 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_usb_ref_disable.4120259132 Sep 01 12:46:06 PM UTC 24 Sep 01 12:46:09 PM UTC 24 165336969 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_phy_config_rand_bus_type.3448906734 Sep 01 12:46:06 PM UTC 24 Sep 01 12:46:10 PM UTC 24 195588013 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_phy_pins_sense.3723416943 Sep 01 12:46:08 PM UTC 24 Sep 01 12:46:10 PM UTC 24 32827799 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_received.3254886206 Sep 01 12:46:10 PM UTC 24 Sep 01 12:46:12 PM UTC 24 176874394 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_in_transaction.391625752 Sep 01 12:46:10 PM UTC 24 Sep 01 12:46:13 PM UTC 24 207590260 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_pkt_sent.3961733184 Sep 01 12:46:10 PM UTC 24 Sep 01 12:46:13 PM UTC 24 264318462 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_random_length_out_transaction.1789395748 Sep 01 12:46:11 PM UTC 24 Sep 01 12:46:14 PM UTC 24 177495400 ps
T74 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_rx_crc_err.204304791 Sep 01 12:46:13 PM UTC 24 Sep 01 12:46:16 PM UTC 24 167500671 ps
T76 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_stress_usb_traffic.1975355314 Sep 01 12:44:27 PM UTC 24 Sep 01 12:46:17 PM UTC 24 6077317909 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_rx_full.4069549663 Sep 01 12:46:14 PM UTC 24 Sep 01 12:46:17 PM UTC 24 282102824 ps
T77 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_rx_pid_err.2565044526 Sep 01 12:46:17 PM UTC 24 Sep 01 12:46:19 PM UTC 24 181227503 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_max_non_iso_usb_traffic.3634348523 Sep 01 12:45:54 PM UTC 24 Sep 01 12:46:20 PM UTC 24 2571470268 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority_over_stall_response.2611924430 Sep 01 12:46:18 PM UTC 24 Sep 01 12:46:20 PM UTC 24 230825900 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rand_bus_disconnects.3561422686 Sep 01 12:44:21 PM UTC 24 Sep 01 12:46:21 PM UTC 24 4065679573 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_setup_priority.2453682589 Sep 01 12:46:18 PM UTC 24 Sep 01 12:46:21 PM UTC 24 361982777 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_setup_stage.1097229260 Sep 01 12:46:19 PM UTC 24 Sep 01 12:46:21 PM UTC 24 165006206 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_min_inter_pkt_delay.2683687557 Sep 01 12:45:55 PM UTC 24 Sep 01 12:46:21 PM UTC 24 2427376289 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_streaming_out.2558272844 Sep 01 12:45:14 PM UTC 24 Sep 01 12:46:22 PM UTC 24 2211784399 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_setup_trans_ignored.1646974675 Sep 01 12:46:20 PM UTC 24 Sep 01 12:46:22 PM UTC 24 165254563 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_stall_trans.2884713998 Sep 01 12:46:22 PM UTC 24 Sep 01 12:46:24 PM UTC 24 160262343 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_stall_priority_over_nak.3700202645 Sep 01 12:46:21 PM UTC 24 Sep 01 12:46:24 PM UTC 24 167230141 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_smoke.2880427939 Sep 01 12:46:21 PM UTC 24 Sep 01 12:46:24 PM UTC 24 239992401 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_aon_wake_resume.174270947 Sep 01 12:45:20 PM UTC 24 Sep 01 12:46:27 PM UTC 24 28669382442 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_sec_cm.4232160836 Sep 01 12:46:25 PM UTC 24 Sep 01 12:46:28 PM UTC 24 244523947 ps
T209 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_alert_test.891372138 Sep 01 12:46:26 PM UTC 24 Sep 01 12:46:29 PM UTC 24 44045114 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_invalid_sync.1776611468 Sep 01 12:45:36 PM UTC 24 Sep 01 12:46:29 PM UTC 24 4595927425 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_stream_len_max.3987761476 Sep 01 12:46:23 PM UTC 24 Sep 01 12:46:29 PM UTC 24 1018398492 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_tx_rx_disruption.2571751637 Sep 01 12:46:25 PM UTC 24 Sep 01 12:46:29 PM UTC 24 579739918 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_av_overflow.1388815590 Sep 01 12:46:30 PM UTC 24 Sep 01 12:46:33 PM UTC 24 158799350 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_bitstuff_err.3312914904 Sep 01 12:46:30 PM UTC 24 Sep 01 12:46:33 PM UTC 24 164172193 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_av_empty.150818194 Sep 01 12:46:30 PM UTC 24 Sep 01 12:46:33 PM UTC 24 154453177 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_av_buffer.747428509 Sep 01 12:46:30 PM UTC 24 Sep 01 12:46:33 PM UTC 24 164411002 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_rand_bus_disconnects.2197872935 Sep 01 12:45:06 PM UTC 24 Sep 01 12:46:36 PM UTC 24 3586295185 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_clear.1312842638 Sep 01 12:46:33 PM UTC 24 Sep 01 12:46:36 PM UTC 24 184726780 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_invalid_sync.316733674 Sep 01 12:44:43 PM UTC 24 Sep 01 12:46:38 PM UTC 24 3898244274 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_data_toggle_restore.1361633661 Sep 01 12:46:33 PM UTC 24 Sep 01 12:46:39 PM UTC 24 1046699427 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_disable_endpoint.1889273864 Sep 01 12:46:37 PM UTC 24 Sep 01 12:46:42 PM UTC 24 809573828 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_enable.1571712399 Sep 01 12:46:40 PM UTC 24 Sep 01 12:46:42 PM UTC 24 40691724 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_disconnected.2662068082 Sep 01 12:46:40 PM UTC 24 Sep 01 12:46:42 PM UTC 24 133805402 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_timeout_missing_host_handshake.204897565 Sep 01 12:46:36 PM UTC 24 Sep 01 12:46:44 PM UTC 24 276538759 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_types.125288720 Sep 01 12:46:43 PM UTC 24 Sep 01 12:46:46 PM UTC 24 241834419 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_levels.3486402868 Sep 01 12:46:43 PM UTC 24 Sep 01 12:46:46 PM UTC 24 275464247 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_dpi_config_host.1229915021 Sep 01 12:44:06 PM UTC 24 Sep 01 12:46:47 PM UTC 24 5112645604 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_fifo_rst.2271251971 Sep 01 12:46:44 PM UTC 24 Sep 01 12:46:48 PM UTC 24 260979131 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_endpoint_access.1584412795 Sep 01 12:46:43 PM UTC 24 Sep 01 12:46:48 PM UTC 24 896418929 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_max_inter_pkt_delay.1554964935 Sep 01 12:45:49 PM UTC 24 Sep 01 12:46:48 PM UTC 24 3888350606 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_in_stall.492346889 Sep 01 12:46:49 PM UTC 24 Sep 01 12:46:51 PM UTC 24 143366843 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_in_iso.1316615904 Sep 01 12:46:49 PM UTC 24 Sep 01 12:46:52 PM UTC 24 248995644 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_streaming_out.945858952 Sep 01 12:46:23 PM UTC 24 Sep 01 12:46:52 PM UTC 24 2554803627 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_spurious_pids_ignored.2338153716 Sep 01 12:45:11 PM UTC 24 Sep 01 12:46:54 PM UTC 24 3056635406 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_in_trans.889365808 Sep 01 12:46:52 PM UTC 24 Sep 01 12:46:55 PM UTC 24 222103148 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_link_in_err.1360042863 Sep 01 12:46:53 PM UTC 24 Sep 01 12:46:56 PM UTC 24 214338140 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_device_timeout.837933861 Sep 01 12:46:34 PM UTC 24 Sep 01 12:46:56 PM UTC 24 2268709422 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/1.usbdev_iso_retraction.1170432813 Sep 01 12:44:45 PM UTC 24 Sep 01 12:46:57 PM UTC 24 7888824647 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_rand_suspends.1534348050 Sep 01 12:44:21 PM UTC 24 Sep 01 12:46:58 PM UTC 24 9902653848 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_spurious_pids_ignored.1508896887 Sep 01 12:46:21 PM UTC 24 Sep 01 12:46:58 PM UTC 24 2839852298 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_disconnect.2131402078 Sep 01 12:46:28 PM UTC 24 Sep 01 12:46:59 PM UTC 24 9770713607 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_aon_wake_reset.304152914 Sep 01 12:46:28 PM UTC 24 Sep 01 12:46:59 PM UTC 24 21077405383 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_in_transaction.2828071176 Sep 01 12:46:57 PM UTC 24 Sep 01 12:47:00 PM UTC 24 250718490 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/2.usbdev_link_resume.232464252 Sep 01 12:45:48 PM UTC 24 Sep 01 12:47:00 PM UTC 24 32978039866 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_max_length_out_transaction.3230212175 Sep 01 12:46:58 PM UTC 24 Sep 01 12:47:01 PM UTC 24 197179199 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_in_transaction.2807848510 Sep 01 12:47:00 PM UTC 24 Sep 01 12:47:02 PM UTC 24 159562713 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_min_length_out_transaction.3357281827 Sep 01 12:47:01 PM UTC 24 Sep 01 12:47:03 PM UTC 24 142987226 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_nak_trans.2561755434 Sep 01 12:47:01 PM UTC 24 Sep 01 12:47:04 PM UTC 24 231008607 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_out_iso.754059845 Sep 01 12:47:02 PM UTC 24 Sep 01 12:47:04 PM UTC 24 146538100 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_out_stall.705807013 Sep 01 12:47:03 PM UTC 24 Sep 01 12:47:06 PM UTC 24 179878398 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/0.usbdev_freq_hiclk_max.1123040672 Sep 01 12:44:06 PM UTC 24 Sep 01 12:47:06 PM UTC 24 89262625741 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_out_trans_nak.651502358 Sep 01 12:47:04 PM UTC 24 Sep 01 12:47:07 PM UTC 24 183860115 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_pending_in_trans.4014182280 Sep 01 12:47:04 PM UTC 24 Sep 01 12:47:07 PM UTC 24 148916578 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_pinflip.2319560731 Sep 01 12:47:05 PM UTC 24 Sep 01 12:47:08 PM UTC 24 249261935 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_phy_pins_sense.18901264 Sep 01 12:47:07 PM UTC 24 Sep 01 12:47:09 PM UTC 24 37578809 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_usb_ref_disable.3643682870 Sep 01 12:47:07 PM UTC 24 Sep 01 12:47:10 PM UTC 24 152486772 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_phy_config_rand_bus_type.3181969353 Sep 01 12:47:07 PM UTC 24 Sep 01 12:47:10 PM UTC 24 282285133 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_received.231305891 Sep 01 12:47:07 PM UTC 24 Sep 01 12:47:10 PM UTC 24 158061097 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_pkt_sent.1717300733 Sep 01 12:47:09 PM UTC 24 Sep 01 12:47:11 PM UTC 24 260948640 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_link_suspend.2447088419 Sep 01 12:46:56 PM UTC 24 Sep 01 12:47:13 PM UTC 24 10875909062 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/coverage/default/3.usbdev_random_length_out_transaction.1080543339 Sep 01 12:47:11 PM UTC 24 Sep 01 12:47:13 PM UTC 24 152868152 ps
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