Unified Coverage Report :: Group :: usbdev_env_pkg::usbdev_env_cov::address_cg

Group : usbdev_env_pkg::usbdev_env_cov::address_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/usbdev-sim-vcs/default/sim-vcs/../src/lowrisc_dv_usbdev_env_0.1/usbdev_env_cov.sv

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Summary for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	9	0	9	100.00
Crosses	14	0	14	100.00

Variables for Group usbdev_env_pkg::usbdev_env_cov::address_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_address	7	0	7	100.00	100	1	1	0
cp_endp	2	0	2	100.00	100	1	1	0

Crosses for Group usbdev_env_pkg::usbdev_env_cov::address_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_address_X_endp	14	0	14	100.00	100	1	1	0

Summary for Variable cp_address

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_address

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	936	1			T243	1		T68	2		T567	3
range_16_to_126	161576	1			T2	1		T28	1		T29	13
fifteen	545	1			T243	1		T55	8		T68	1
range_2_to_14	20279	1			T3	1		T42	1		T30	8
seven	568	1			T42	1		T85	1		T68	3
one	1007	1			T49	3		T68	2		T116	8
zero	2313	1			T43	1		T52	3		T68	4

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Summary for Variable cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_endp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

seven

13152

1

T31

1

T32

1

T33

2

three

14069

1

T28

1

T42

1

T43

19

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Summary for Cross cr_address_X_endp

Samples crossed: cp_address cp_endp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	0	14	100.00

Automatically Generated Cross Bins for cr_address_X_endp

Bins

cp_address	cp_endp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
range_127	seven	47	1			T68	1		T182	2		T458	2
range_127	three	60	1			T568	1		T569	1		T455	34
range_16_to_126	seven	11476	1			T31	1		T32	1		T33	2
range_16_to_126	three	12015	1			T28	1		T42	1		T43	16
fifteen	seven	27	1			T455	1		T570	1		T571	2
fifteen	three	46	1			T182	1		T572	2		T573	1
range_2_to_14	seven	1418	1			T159	1		T68	2		T81	1
range_2_to_14	three	1637	1			T43	2		T72	2		T160	3
seven	seven	39	1			T177	9		T458	1		T574	2
seven	three	58	1			T117	1		T182	1		T177	9
one	seven	69	1			T116	1		T575	9		T576	1
one	three	54	1			T116	1		T575	9		T577	1
zero	seven	115	1			T479	16		T573	1		T577	2
zero	three	257	1			T43	1		T479	16		T570	1